GitLab

TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML

This project provides utility libraries that can be used by several MBE tools such as RAMSES, TTool or RDALTE

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

Multi-temporal speckle reduction with self-supervised deep neural networks

Modified version of QEMU for teaching (M2 SETI Embedded Linux, SE758 Linux Device Drivers...).

A hardware / software architecture protecting the external memories of an SoC

RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/

Nouveau thème Beamer aux couleur de Télécom Paris

Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).

TD équation de Kaya, transition énergétique et développement durable

Python implementation of the GLRT based linear features detector proposed by N.Gasnier, L.Denis, F.Liège, R.Fjørtoft, and F.Tupin in Narrow River Extraction from SAR ImagesUsing Exogenous Information (Submitted to IEEE JSTARS).

SAR Image Despeckling by Deep Neural Networks: from a pre-trained model to an end-to-end training strategy - Notebook implementation usable on Google Colaboratory

A Benchmark of Incremental Model Transformation Tools based on an Industrial Case Study with AADL

Nouveau thème Beamer aux couleur de Télécom Paris