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TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML

simple python script to convert Synapses csv schedules to ics calendars.

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

This is the repository containing the code of the PEPR - PC7 project

This project provides utility libraries that can be used by several MBE tools such as RAMSES, TTool or RDALTE

RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/

Alternate free software firmware for DFRobot DFR0592 DC motor driver hat