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Renaud Pacalet / secbus
CeCILL Free Software License Agreement v2.1A hardware / software architecture protecting the external memories of an SoC
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ring / SAR2SAR
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ring / SAR-CNN
GNU General Public License v3.0 or laterSAR Image Despeckling by Deep Neural Networks: from a pre-trained model to an end-to-end training strategy - Notebook implementation usable on Google Colaboratory
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Renaud Pacalet / sab4z
CeCILL Free Software License Agreement v2.1A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
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Renaud Pacalet / sab4u
CeCILL Free Software License Agreement v2.1A simple example design for Zynq Ultrascale+ based boards.
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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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mbe-tools / RAMSES-2
Eclipse Public License 2.0RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/
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RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.
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QoE testbed for sampling constrained applications like Skype
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Modified version of QEMU for teaching (M2 SETI Embedded Linux, SE758 Linux Device Drivers...).
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