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Commit 00458acd authored by Ludovic Apvrille's avatar Ludovic Apvrille
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Resolving a few test after updates on the simulator

parent db176041
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.idea/misc.xml
View file @ 00458acd
......@@ -38,7 +38,7 @@
<property name="caretWidth" class="java.lang.Integer" />
</properties>
</component>
<component name="ProjectRootManager" version="2" languageLevel="JDK_1_8" default="false" project-jdk-name="1.8" project-jdk-type="JavaSDK">
<component name="ProjectRootManager" version="2" languageLevel="JDK_11" project-jdk-name="11" project-jdk-type="JavaSDK">
<output url="file://$PROJECT_DIR$/build" />
</component>
</project>
</project>
\ No newline at end of file
.idea/runConfigurations/TTool.xml
View file @ 00458acd
......@@ -5,6 +5,7 @@
<option name="MAIN_CLASS_NAME" value="Main" />
<module name="ttool" />
<option name="PROGRAM_PARAMETERS" value="-debug -proverif -experimental -config bin/config.xml" />
<option name="WORKING_DIRECTORY" value="$PROJECT_DIR$/bin" />
<method v="2">
<option name="Make" enabled="true" />
<option name="BuildArtifacts" enabled="true">
......
Makefile
View file @ 00458acd
......@@ -70,7 +70,7 @@ make git Update the build number.
Please report bugs or suggestions of improvements to:
ttool.telecom-paristech.fr/support.html
ttool.telecom-paris.fr/support.html
endef
export HELP_message
......
graphminimize/src/main/java/GraphMinimize.java
View file @ 00458acd
......@@ -56,9 +56,9 @@ import java.io.File;
public class GraphMinimize {
public static void printCopyright() {
System.out.println("GraphMinimize: (C) Telecom ParisTech, Ludovic APVRILLE ludovic.apvrille, andrea.enrici@telecom-paristech.fr");
System.out.println("GraphMinimize: (C) Telecom Paris, Ludovic APVRILLE, Andrea ENRICI. ludovic.apvrille@telecom-paris.fr");
System.out.println("GraphMinimize is released under a CECILL License. See http://www.cecill.info/index.en.html");
System.out.println("For more information on TTool related technologies, please consult http://ttool.telecom-paristech.fr/");
System.out.println("For more information on TTool related technologies, please consult http://ttool.telecom-paris.fr/");
System.out.println("Enjoy!!!\n");
}
......
rundse/src/main/java/RunDSE.java
View file @ 00458acd
......@@ -63,9 +63,9 @@ public class RunDSE {
public static void printCopyright() {
System.out.println("RunDSE: (C) Institut Telecom / Telecom ParisTech, Ludovic Apvrille, Ludovic.Apvrille@telecom-paristech.fr");
System.out.println("RunDSE: (C) Institut Mines Telecom / Telecom Paris, Ludovic Apvrille, Ludovic.Apvrille@telecom-paris.fr");
System.out.println("RunDSE is released under a CECILL License. See http://www.cecill.info/index.en.html");
System.out.println("For more information on TTool related technologies, please consult http://ttool.telecom-paristech.fr");
System.out.println("For more information on TTool related technologies, please consult https://ttool.telecom-paris.fr");
System.out.println("Enjoy!!!\n");
}
......
simulationcontrol/src/main/java/RemoteSimulationControl.java
View file @ 00458acd
......@@ -68,10 +68,10 @@ public class RemoteSimulationControl extends Thread {
}
public static void printCopyright() {
System.out.println("RemoteSimulationControl: (C) GET/ENST, Ludovic Apvrille, Ludovic.Apvrille@enst.fr");
System.out.println("RemoteSimulationControl: (C) Institut Mines Telecom / Telecom Paris, Ludovic Apvrille, Ludovic.Apvrille@telecom-paris.fr");
System.out.println("RemoteSimulationControl is released under a CECILL License. See http://www.cecill.info/index.en.html");
System.out.println("For more information on TTool related technologies, please consult http://labsoc.comelec.enst.fr/turtle/ttoolindex.html");
System.out.println("For more information on TTool related technologies, please consult https://ttool.telecom-paris.fr");
System.out.println("Enjoy!!!\n");
}
......
src/main/java/ui/interactivesimulation/JFrameTMLSimulationPanelTimeline.java
View file @ 00458acd
......@@ -284,7 +284,6 @@ public class JFrameTMLSimulationPanelTimeline extends JFrame implements ActionLi
// viewToModel will be Deprecated. replaced by viewToModel2D(JTextComponent, Point2D, Position.Bias[]) in java 9
int pos = viewToModel2D((Point2D)new Point(X,Y));
if (pos >= 0) {
try {
// modelToView will be Deprecated. replaced by modelToView2D(JTextComponent, int, Position.Bias) in java 9
if (timeMarkedPosition.keySet().contains(pos) && Math.abs(LineHighlight.Rectangle2DtoRectangle(modelToView2D(pos)).x - X) < 3) {
......
tiftranslator/src/main/java/TIFTranslator.java
View file @ 00458acd
......@@ -70,11 +70,11 @@ public class TIFTranslator {
public static void printCopyright() {
System.out.println("TIFTranslator: (C) GET/ENST, Ludovic Apvrille, Ludovic.Apvrille@enst.fr");
System.out.println("TIFTranslator: (C) Institut Mines Telecom / Telecom Paris, Ludovic Apvrille, Ludovic.Apvrille@telecom-paris.fr");
System.out.println("TIFTranslator is released under a CECILL License. See http://www.cecill.info/index.en.html");
System.out.println("For more information on TURTLE related technologies, please consult http://labsoc.comelec.enst.fr/turtle/");
System.out.println("Enjoy!\n");
System.out.println("For more information on TTool related technologies, please consult https://ttool.telecom-paris.fr");
System.out.println("Enjoy!!!\n");
}
public static void printUsage() {
......
ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
View file @ 00458acd
......@@ -26,21 +26,21 @@ public class DiplodocusSimulatorTest extends AbstractTest {
final String [] MODELS = {"scp", "ssdf"};
final String DIR_GEN = "test_diplo_simulator/";
final int [] NB_Of_STATES = {119, 1045};
final int [] NB_Of_TRANSTIONS = {118, 1044};
final int [] MIN_CYCLES = {201, 4025};
final int [] MAX_CYCLES = {297, 4025};
final int [] NB_Of_STATES = {119, 1054};
final int [] NB_Of_TRANSTIONS = {118, 1053};
final int [] MIN_CYCLES = {192, 2510};
final int [] MAX_CYCLES = {279, 2510};
//model for daemon task
final String [] MODELS_DAEMON = {"daemontest1", "daemontest2"};
final int [] NB_Of_DAEMON_STATES = {5, 108};
final int [] NB_Of_DAEMON_TRANSTIONS = {4, 107};
final int [] MIN_DAEMON_CYCLES = {26, 3079};
final int [] MAX_DAEMON_CYCLES = {26, 3079};
final int [] NB_Of_DAEMON_STATES = {8, 114};
final int [] NB_Of_DAEMON_TRANSTIONS = {7, 113};
final int [] MIN_DAEMON_CYCLES = {101, 2469};
final int [] MAX_DAEMON_CYCLES = {101, 2469};
// model for Daemon Run To Next Breakpoint
final String MODELS_DAEMON_RTNB = "testDaemon";
final int [] DAEMON_RTNBP_1 = {10, 9, 205, 205};
final int [] DAEMON_RTNBP_2 = {16, 15, 408, 408};
final int [] DAEMON_RTNBP_1 = {11, 10, 85, 85};
final int [] DAEMON_RTNBP_2 = {18, 17, 168, 168};
private String SIM_DIR;
@BeforeClass
......@@ -209,18 +209,18 @@ public class DiplodocusSimulatorTest extends AbstractTest {
graph.buildGraph(graphData);
// States and transitions
System.out.println("executing: nb of states " + graph.getNbOfStates());
System.out.println("executing: nb of states " + graph.getNbOfStates() + " expecting:" + NB_Of_STATES[i]);
assertTrue(NB_Of_STATES[i] == graph.getNbOfStates());
System.out.println("executing: nb of transitions " + graph.getNbOfTransitions());
System.out.println("executing: nb of transitions " + graph.getNbOfTransitions() + " expecting:" + NB_Of_TRANSTIONS[i]);
assertTrue(NB_Of_TRANSTIONS[i] == graph.getNbOfTransitions());
// Min and max cycles
int minValue = graph.getMinValue("allCPUsFPGAsTerminated");
System.out.println("executing: minvalue " + minValue);
System.out.println("executing: minvalue " + minValue + " expecting:" + MIN_CYCLES[i]);
assertTrue(MIN_CYCLES[i] == minValue);
int maxValue = graph.getMaxValue("allCPUsFPGAsTerminated");
System.out.println("executing: maxvalue " + maxValue);
System.out.println("executing: maxvalue " + maxValue + " expecting: " + MAX_CYCLES[i]);
assertTrue(MAX_CYCLES[i] == maxValue);
}
......@@ -373,9 +373,9 @@ public class DiplodocusSimulatorTest extends AbstractTest {
graph.buildGraph(graphData);
// States and transitions
System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates());
assertTrue(NB_Of_DAEMON_STATES[i] == graph.getNbOfStates());
System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions());
System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates() + " ; expecting: " + NB_Of_DAEMON_STATES[i]);
assertTrue(NB_Of_DAEMON_STATES[i] == graph.getNbOfStates() );
System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions() + " ; expecting: " + NB_Of_DAEMON_TRANSTIONS[i]);
assertTrue(NB_Of_DAEMON_TRANSTIONS[i] == graph.getNbOfTransitions());
// Min and max cycles
......@@ -419,6 +419,8 @@ public class DiplodocusSimulatorTest extends AbstractTest {
TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
syntax.checkSyntax();
assertTrue(syntax.hasErrors() == 0);
// Generate SystemC code
System.out.println("executing: sim code gen for " + s);
......@@ -552,18 +554,18 @@ public class DiplodocusSimulatorTest extends AbstractTest {
graph.buildGraph(graphData);
// States and transitions
System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates());
System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates() + " ; expecting: " + DAEMON_RTNBP_1[0]);
assertTrue(DAEMON_RTNBP_1[0] == graph.getNbOfStates());
System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions());
System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions() + " ; expecting: " + DAEMON_RTNBP_1[1]);
assertTrue(DAEMON_RTNBP_1[1] == graph.getNbOfTransitions());
// Min and max cycles
int minValue = graph.getMinValue("allCPUsFPGAsTerminated");
System.out.println("executing: minvalue of " + s + " " + minValue);
System.out.println("executing: minvalue of " + s + " " + minValue + " ; expecting: " + DAEMON_RTNBP_1[2]);
assertTrue(DAEMON_RTNBP_1[2] == minValue);
int maxValue = graph.getMaxValue("allCPUsFPGAsTerminated");
System.out.println("executing: maxvalue of " + s + " " + maxValue);
System.out.println("executing: maxvalue of " + s + " " + maxValue + " ; expecting: " + DAEMON_RTNBP_1[3]);
assertTrue(DAEMON_RTNBP_1[3] == maxValue);
//test for second case
......
ttool/src/test/java/tmltranslator/HTMLParseTest.java
View file @ 00458acd
......@@ -26,10 +26,10 @@ import static org.junit.Assert.*;
public class HTMLParseTest extends AbstractTest {
final String DIR_GEN = "test_diplo_simulator/";
final String [] MODELS_PARSE_HTML = {"parseFPGA_HTML", "parseCPU1_HTML","parseCPU2_HTML"};
final String [] PARSE_FPGA = {"<- idle 471 ->","", "", "", ""};
final String [] PARSE_FPGA = {"<- idle 451 ->","", "", "", ""};
//final String [] PARSE_FPGA = {"","", "", "", ""};
final String [] PARSE_SINGLE_CORE = {"<- idle 366 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->"};
final String [] PARSE_MULTI_CORE = { "", "", "", "", "<- idle 377 ->"};
final String [] PARSE_SINGLE_CORE = {"<- idle 381 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->"};
final String [] PARSE_MULTI_CORE = { "", "", "", "<- idle 389 ->", "<- idle 401 ->"};
final static String EXPECTED_FILE_GET_ALL_TRANS = getBaseResourcesDir() + "tmltranslator/expected/expected_get_all_transactions.txt";
private String SIM_DIR;
......@@ -213,7 +213,7 @@ public class HTMLParseTest extends AbstractTest {
break;
default:
for (int j = 0; j < 5; j++) {
System.out.println("MULTI_CORE " + s + ": " + div.get(j).text());
System.out.println("MULTI_CORE " + s + ": " + div.get(j).text() + " ; expecting: " + PARSE_MULTI_CORE[j]);
assertTrue(PARSE_MULTI_CORE[j].equals(div.get(j).text()));
}
break;
......
ttool/src/test/java/tmltranslator/HelpServerTest.java
View file @ 00458acd
......@@ -82,6 +82,15 @@ public class HelpServerTest extends AbstractTest {
TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
syntax.checkSyntax();
if (syntax.hasErrors() != 0) {
for (TMLError error: syntax.getErrors()) {
System.out.println("Error: " + error.toString());
}
}
assertTrue(syntax.hasErrors() == 0);
// Generate SystemC code
System.out.println("executing: sim code gen for " + s);
......
ttool/src/test/resources/tmltranslator/simulator/daemontest1.tmap
View file @ 00458acd
......@@ -13,4 +13,8 @@ TMLMAPPING
SET ApplicationSimple__T2 priority 0
MAP Src ApplicationSimple__Src
SET ApplicationSimple__Src priority 0
MAP Memory0 ApplicationSimple__chToT1
MAP Bus0 ApplicationSimple__chToT1
MAP Memory0 ApplicationSimple__chToT2
MAP Bus0 ApplicationSimple__chToT2
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/daemontest2.tmap
View file @ 00458acd
......@@ -13,4 +13,8 @@ TMLMAPPING
SET ApplicationSimple__T2 priority 0
MAP Src ApplicationSimple__Src
SET ApplicationSimple__Src priority 0
MAP Memory0 ApplicationSimple__chToT1
MAP Bus0 ApplicationSimple__chToT1
MAP Memory0 ApplicationSimple__chToT2
MAP Bus0 ApplicationSimple__chToT2
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/fpga_clock_divider.tmap
View file @ 00458acd
......@@ -13,4 +13,8 @@ TMLMAPPING
SET ApplicationSimple__T2 priority 0
MAP FPGA0 ApplicationSimple__T1
SET ApplicationSimple__T1 priority 0
MAP Memory0 ApplicationSimple__chToT1
MAP Bus0 ApplicationSimple__chToT1
MAP Memory0 ApplicationSimple__chToT2
MAP Bus0 ApplicationSimple__chToT2
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/parseCPU1_HTML.tmap
View file @ 00458acd
......@@ -17,4 +17,6 @@ TMLMAPPING
SET Application__Task5 priority 0
MAP CPU0 Application__Task4
SET Application__Task4 priority 0
MAP Memory0 Application__ch
MAP Bus0 Application__ch
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/parseCPU2_HTML.tmap
View file @ 00458acd
......@@ -17,4 +17,6 @@ TMLMAPPING
SET Application__Task5 priority 0
MAP CPU0 Application__Task4
SET Application__Task4 priority 0
MAP Memory0 Application__ch
MAP Bus0 Application__ch
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/parseFPGA_HTML.tmap
View file @ 00458acd
......@@ -17,4 +17,6 @@ TMLMAPPING
SET Application__Task3 priority 0
MAP FPGA0 Application__Task4
SET Application__Task4 priority 0
MAP Memory0 Application__ch
MAP Bus0 Application__ch
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/scp.tmap
View file @ 00458acd
......@@ -17,4 +17,18 @@ TMLMAPPING
SET AppC__TCPIP priority 0
MAP HWA0 AppC__Timer
SET AppC__Timer priority 0
MAP Memory0 AppC__fromAtoT
MAP Bus0 AppC__fromAtoT
MAP Memory0 AppC__fromDtoSC
MAP Bus0 AppC__fromDtoSC
MAP Memory0 AppC__fromPtoT
MAP Bus0 AppC__fromPtoT
MAP Memory0 AppC__fromSCtoD
MAP Bus0 AppC__fromSCtoD
MAP Memory0 AppC__fromTtoA
MAP Bus0 AppC__fromTtoA
MAP Memory0 AppC__fromTtoP
MAP Bus0 AppC__fromTtoP
MAP Memory0 AppC__temp
MAP Bus0 AppC__temp
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/ssdf.tmap
View file @ 00458acd
......@@ -27,4 +27,22 @@ TMLMAPPING
SET FORKTASK_S_EVT_S_Application__evtToT3T5__evtToT3__evtToT5 priority 0
MAP FPGA1 JOINTASK_S_Application__chFromT4__chFromT5__chtoDst
SET JOINTASK_S_Application__chFromT4__chFromT5__chtoDst priority 0
MAP Memory0 Application__chFromT4__chFromT5__chtoDst
MAP Bus0 Application__chFromT4__chFromT5__chtoDst
MAP Memory0 Application__chToT1
MAP Bus0 Application__chToT1
MAP Memory0 Application__chToT2
MAP Bus0 Application__chToT2
MAP Memory0 Application__chToT3T5__chToT3__chToT5
MAP Bus0 Application__chToT3T5__chToT3__chToT5
MAP Memory0 Application__chToT4
MAP Bus0 Application__chToT4
MAP Memory0 FORKCHANNEL_S_0_S_Application__chToT3T5__chToT3__chToT5
MAP Bus0 FORKCHANNEL_S_0_S_Application__chToT3T5__chToT3__chToT5
MAP Memory0 FORKCHANNEL_S_1_S_Application__chToT3T5__chToT3__chToT5
MAP Bus0 FORKCHANNEL_S_1_S_Application__chToT3T5__chToT3__chToT5
MAP Memory0 JOINCHANNEL_S_0__Application__chFromT4__chFromT5__chtoDst
MAP Bus0 JOINCHANNEL_S_0__Application__chFromT4__chFromT5__chtoDst
MAP Memory0 JOINCHANNEL_S_1__Application__chFromT4__chFromT5__chtoDst
MAP Bus0 JOINCHANNEL_S_1__Application__chFromT4__chFromT5__chtoDst
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/simulator/testDaemon.tmap
View file @ 00458acd
......@@ -13,4 +13,6 @@ TMLMAPPING
SET FVWithRequest__Periodic priority 0
MAP CPU0 FVWithRequest__AnotherTask
SET FVWithRequest__AnotherTask priority 0
MAP Memory0 FVWithRequest__comm1__FVWithRequest__comm
MAP Bus0 FVWithRequest__comm1__FVWithRequest__comm
ENDTMLMAPPING
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