diff --git a/simulators/c++2/src_simulator/arch/Bus.cpp b/simulators/c++2/src_simulator/arch/Bus.cpp
index bf77be113fb884c08bc293e089f5fd291659aa0b..cdce8b4a006599a30ec56fc091e56212e5c1c5f8 100644
--- a/simulators/c++2/src_simulator/arch/Bus.cpp
+++ b/simulators/c++2/src_simulator/arch/Bus.cpp
@@ -117,7 +117,7 @@ void Bus::calcStartTimeLength(TMLTime iTimeSlice) const{
TMLTime tmp2 = static_cast<TMLTime>(_nextTransaction->getPenalties());
TMLTime tmp3 = static_cast<TMLTime>(_nextTransaction->getStartTime());
//std::cout << "BUS ------------- tmp1:" << tmp1 << " tmp2:" << tmp2 << " tmp3:" << tmp3 << "\n";
- if (tmp1 < tmp2) { tmp1 = tmp2;}
+// if (tmp1 < tmp2) { tmp1 = tmp2;}
//_nextTransaction->setStartTime(max(tmp1+tmp2, tmp3));
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index 5a8b58e349299e1ecad1d78fe130ba1493a739cb..5ea8f21913c4c456b08ca427db29b839ff5bba3b 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -50,18 +50,20 @@
FPGA::FPGA( ID iID,
std::string iName,
WorkloadSource* iScheduler,
- TMLTime iReconfigTime,
+ TMLTime iReconfigTime,
+ TMLTime iTimePerCycle,
unsigned int iChangeIdleModeCycles,
unsigned int iCyclesBeforeIdle,
unsigned int iCyclesPerExeci,
unsigned int iCyclesPerExecc ) : SchedulableDevice(iID, iName, iScheduler)
,_reconfigTime(iReconfigTime)
+ ,_timePerCycle(iTimePerCycle)
,_masterNextTransaction(0)
,_lastTransaction(0)
- ,_changeIdleModeCycles(iChangeIdleModeCycles)
- ,_cyclesBeforeIdle(iCyclesBeforeIdle)
- ,_cyclesPerExeci(iCyclesPerExeci)
- ,_cyclesPerExecc(iCyclesPerExecc)
+ ,_changeIdleModeCycles(iChangeIdleModeCycles * _timePerCycle)
+ ,_cyclesBeforeIdle(iCyclesBeforeIdle * _timePerCycle)
+ ,_cyclesPerExeci(iCyclesPerExeci * _timePerCycle)
+ ,_cyclesPerExecc(iCyclesPerExecc * _timePerCycle)
,_reconfigNumber(0)
,_maxEndTime(0)
@@ -152,8 +154,10 @@ void FPGA::calcStartTimeLength(){
#ifdef BUS_ENABLED
if (_masterNextTransaction==0){
#endif
- _nextTransaction->setLength(max(_nextTransaction->getVirtualLength(),(TMLTime)1));
+ _nextTransaction->setLength(max(_nextTransaction->getVirtualLength() * _cyclesPerExeci,(TMLTime)1));
+#ifdef BUS_ENABLED
}
+#endif
}
@@ -187,7 +191,7 @@ std::cout<<"fpga truncateNextTransAt"<<std::endl;
if (iTime <= _nextTransaction->getStartTime()) return 0; //before: <=
TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
_nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration), (TMLTime)1));
- _nextTransaction->setLength(_nextTransaction->getVirtualLength());
+ _nextTransaction->setLength(_nextTransaction->getVirtualLength() * _cyclesPerExeci);
}
return _nextTransaction->getOverallLength();
}
@@ -257,14 +261,16 @@ std::cout<<"fpga addTransaction"<<std::endl;
if(!_nextTransaction->getCommand()->getTask()->getIsFirstTranExecuted() && (_tempTranName.find("Read") == std::string::npos
&& _tempTranName.find("Wait") == std::string::npos && _tempTranName.find("Notified") == std::string::npos)) {
unsigned int _tempStartTime = _nextTransaction->getStartTime();
- _nextTransaction->setStartTime(_tempStartTime + _reconfigNumber * _reconfigTime);
+ _nextTransaction->setStartTime(_tempStartTime + _reconfigNumber * _reconfigTime * _cyclesPerExeci);
_maxEndTime=max(_maxEndTime,_nextTransaction->getEndTime());
+ _transactListReconfig.push_back(_nextTransaction);
}
_nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
} else if(_tempReconfigNumber>0) {
if(!_nextTransaction->getCommand()->getTask()->getIsFirstTranExecuted()) {
- _nextTransaction->setStartTime(_maxEndTime + _tempReconfigNumber * _reconfigTime);
+ _nextTransaction->setStartTime(_maxEndTime + _tempReconfigNumber * _reconfigTime * _cyclesPerExeci);
_nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
+ _transactListReconfig.push_back(_nextTransaction);
}
}
else{
@@ -395,6 +401,7 @@ void FPGA::reset(){
SchedulableDevice::reset();
_scheduler->reset();
_transactList.clear();
+ if (!_transactListReconfig.empty()) _transactListReconfig.clear();
_nextTransaction=0;
_lastTransaction=0;
_masterNextTransaction=0;
@@ -660,9 +667,17 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
std::cout<<"in!!"<<_htmlCurrTask->toString()<<std::endl;
#endif
TMLTransaction* aCurrTrans = *i;
+ bool reconfigCheck = false;
+ if (!_transactListReconfig.empty()) {
+ std::vector<TMLTransaction*>::iterator it = std::find (_transactListReconfig.begin(), _transactListReconfig.end(), aCurrTrans);
+ if (it != _transactListReconfig.end()) {
+ reconfigCheck = true;
+ }
+ }
+
unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
bool isBlankTooBig = false;
- std::ostringstream tempString;
+ std::ostringstream tempString, tempReconfigIdle;
int tempBlanks;
if(_htmlCurrTask->getEndLastTransaction() >= MIN_RESIZE_THRESHOLD && aBlanks > MIN_RESIZE_TRANS) {
int newBlanks = 0;
@@ -679,6 +694,11 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
isBlankTooBig = true;
changeCssClass = true;
}
+ if (reconfigCheck) {
+ tempReconfigIdle << "dynamic reconfiguration";
+ } else {
+ tempReconfigIdle << " ";
+ }
if ( aBlanks >= 0 && (!(aCurrTrans->getCommand()->getActiveDelay()) && aCurrTrans->getCommand()->isDelayTransaction()) ){
listScale.push_back(aBlanks+1);
tempString << tempBlanks+1;
@@ -686,21 +706,20 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
listScaleTime.push_back(aCurrTrans->getStartTime()+1);
}
if (isBlankTooBig){
- myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
+ myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
} else {
- myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time\" class=\"not\"></td>";
+ myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\"></td>";
}
- }
- else if ( aBlanks > 0 ){
+ } else if ( aBlanks > 0 ){
listScale.push_back(aBlanks);
tempString << tempBlanks;
if(aCurrTrans->getStartTime() > listScaleTime.back()){
listScaleTime.push_back(aCurrTrans->getStartTime());
}
if (isBlankTooBig){
- myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
+ myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
} else {
- myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time\" class=\"not\"></td>";
+ myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\"></td>";
}
}
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index 602f84305d2827a5f8a891f59a8a53699a64fb17..85874ea8a445a7fe619441e30a0411161bcc8048 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -78,7 +78,7 @@ public:
\param iCyclesPerExecc Cycles needed to execute one EXECC unit
*/
- FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
+ FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, TMLTime iTimePerCycle, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
///Destructor
virtual ~FPGA();
///Determines the next FPGA transaction to be executed
@@ -164,6 +164,7 @@ protected:
void calcStartTimeLength();
TMLTime _reconfigTime;
+ TMLTime _timePerCycle;
///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
@@ -199,6 +200,7 @@ protected:
unsigned int _reconfigNumber;
unsigned int maxScale;
TMLTime _maxEndTime;
+ TransactionList _transactListReconfig; // contains the first trans of each tasks when fpga scheduling is enable
unsigned int nextCellClassIndex;
std::map<TMLTask*, std::string> taskCellClasses;
///State variable for the VCD output
diff --git a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
index 09ec16872d71e9b901fe15f8f188a61a26f33ff7..fc80dd3dea97fb22ffc7651604ab0b58ce357322 100644
--- a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
@@ -172,6 +172,8 @@ void SingleCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
//std::cout << "starttime=" << _nextTransaction->getStartTime() << "\n";
if ((_nextTransaction->getStartTime()-_endSchedule) >=_timeBeforeIdle){
_nextTransaction->setIdlePenalty(_changeIdleModeTime);
+ } else {
+ _nextTransaction->setIdlePenalty(0);
}
#endif
}
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
index bcb99f76edf187445b1dee08013a58cadb69045d..593cdb0a4a781db880714817434941a8f0046a94 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
@@ -360,7 +360,7 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
declaration += "FPGA* " + hwFpgaInstName + " = new FPGA(" + hwFpgaNode.getID() + ", \"" + namesGen.hwFpgaName(hwFpgaNode) + "\", "
+ schedulerInstName + ", ";
- declaration += hwFpgaNode.reconfigurationTime + ", " + hwFpgaNode.goIdleTime + ", " + hwFpgaNode.maxConsecutiveIdleCycles + ", "
+ declaration += hwFpgaNode.reconfigurationTime + ", " + hwFpgaNode.clockRatio + ", " + hwFpgaNode.goIdleTime + ", " + hwFpgaNode.maxConsecutiveIdleCycles + ", "
+ hwFpgaNode.execiTime + ", " + hwFpgaNode.execcTime + ")" + SCCR;
// DB: Issue #21 TODO: Should there be a scheduler?? Given the for loop, cores
diff --git a/ttool/src/test/java/tmltranslator/FpgaClockDividerTest.java b/ttool/src/test/java/tmltranslator/FpgaClockDividerTest.java
new file mode 100644
index 0000000000000000000000000000000000000000..b1fa9178b233d6a576b17f3dd807d7c987ca8d8c
--- /dev/null
+++ b/ttool/src/test/java/tmltranslator/FpgaClockDividerTest.java
@@ -0,0 +1,201 @@
+package tmltranslator;
+
+import common.ConfigurationTTool;
+import common.SpecConfigTTool;
+import graph.AUTGraph;
+import myutil.FileUtils;
+import org.junit.Before;
+import org.junit.BeforeClass;
+import org.junit.Test;
+import req.ebrdd.EBRDD;
+import tepe.TEPE;
+import tmltranslator.tomappingsystemc2.DiploSimulatorFactory;
+import tmltranslator.tomappingsystemc2.IDiploSimulatorCodeGenerator;
+import tmltranslator.tomappingsystemc2.Penalties;
+import ui.AbstractUITest;
+import ui.TDiagramPanel;
+import ui.TMLArchiPanel;
+import ui.tmldd.TMLArchiDiagramPanel;
+
+import java.io.BufferedReader;
+import java.io.File;
+import java.io.InputStreamReader;
+import java.util.ArrayList;
+import java.util.List;
+
+import static org.junit.Assert.assertTrue;
+
+public class FpgaClockDividerTest extends AbstractUITest {
+
+ private final String DIR_GEN = "test_diplo_simulator/";
+ private final String [] MODELS_FPGA_CLOCK_DIVIDER = {"fpga_clock_divider"};
+ private String SIM_DIR;
+ private final int [] NB_OF_FCD_STATES = {32};
+ private final int [] NB_OF_FCD_TRANSTIONS = {31};
+ private final int [] MIN_FCD_CYCLES = {220};
+ private final int [] MAX_FCD_CYCLES = {220};
+ private static String CPP_DIR = "../../../../simulators/c++2/";
+ private static String mappingName = "ArchitectureSimple";
+
+ @BeforeClass
+ public static void setUpBeforeClass() throws Exception {
+ RESOURCES_DIR = getBaseResourcesDir() + "/tmltranslator/simulator/";
+ }
+
+ public FpgaClockDividerTest() {
+ super();
+ }
+
+ @Before
+ public void setUp() throws Exception {
+ SIM_DIR = getBaseResourcesDir() + CPP_DIR;
+ }
+
+ @Test(timeout = 600000)
+ public void testMulticoreNotHangingWhenSaveTrace() throws Exception {
+ for (int i = 0; i < MODELS_FPGA_CLOCK_DIVIDER.length; i++) {
+ String s = MODELS_FPGA_CLOCK_DIVIDER[i];
+ SIM_DIR = DIR_GEN + s + "/";
+ System.out.println("executing: checking syntax " + s);
+ // select architecture tab
+ mainGUI.openProjectFromFile(new File(RESOURCES_DIR + s + ".xml"));
+ TMLArchiPanel _tab = findArchiPanel(mappingName);
+ for (TDiagramPanel tdp : _tab.getPanels()) {
+ if (tdp instanceof TMLArchiDiagramPanel) {
+ mainGUI.selectTab(tdp);
+ break;
+ }
+ }
+
+ mainGUI.checkModelingSyntax(true);
+ TMLMapping tmap = mainGUI.gtm.getTMLMapping();
+ TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
+ syntax.checkSyntax();
+ assertTrue(syntax.hasErrors() == 0);
+ // Generate SystemC code
+ System.out.println("executing: sim code gen for " + s);
+ final IDiploSimulatorCodeGenerator tml2systc;
+ List<EBRDD> al = new ArrayList<EBRDD>();
+ List<TEPE> alTepe = new ArrayList<TEPE>();
+ tml2systc = DiploSimulatorFactory.INSTANCE.createCodeGenerator(tmap, al, alTepe);
+ tml2systc.setModelName(s);
+ String error = tml2systc.generateSystemC(false, true);
+ assertTrue(error == null);
+
+ File directory = new File(SIM_DIR);
+ if (!directory.exists()) {
+ directory.mkdirs();
+ }
+
+ // Putting sim files
+ System.out.println("SIM executing: sim lib code copying for " + s);
+ ConfigurationTTool.SystemCCodeDirectory = getBaseResourcesDir() + CPP_DIR;
+ boolean simFiles = SpecConfigTTool.checkAndCreateSystemCDir(SIM_DIR);
+
+ System.out.println("SIM executing: sim lib code copying done with result " + simFiles);
+ assertTrue(simFiles);
+
+ System.out.println("SIM Saving file in: " + SIM_DIR);
+ tml2systc.saveFile(SIM_DIR, "appmodel");
+
+ // Compile it
+ System.out.println("executing: compile");
+ Process proc;
+ BufferedReader proc_in;
+ String str;
+ boolean mustRecompileAll;
+ Penalties penalty = new Penalties(SIM_DIR + "src_simulator");
+ int changed = penalty.handlePenalties(false);
+
+ if (changed == 1) {
+ mustRecompileAll = true;
+ } else {
+ mustRecompileAll = false;
+ }
+
+ if (mustRecompileAll) {
+ System.out.println("executing: " + "make -C " + SIM_DIR + " clean");
+ try {
+ proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + " clean");
+ proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
+ while ((str = proc_in.readLine()) != null) {
+ // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
+ System.out.println("executing: " + str);
+ }
+ } catch (Exception e) {
+ // probably make is not installed
+ System.out.println("FAILED: executing: " + "make -C " + SIM_DIR + " clean");
+ return;
+ }
+ }
+
+ System.out.println("executing: " + "make -C " + SIM_DIR);
+ try {
+ proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + "");
+ proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
+
+ monitorError(proc);
+
+ while ((str = proc_in.readLine()) != null) {
+ // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
+ System.out.println("executing: " + str);
+ }
+ } catch (Exception e) {
+ // Probably make is not installed
+ System.out.println("FAILED: executing: " + "make -C " + SIM_DIR);
+ return;
+ }
+
+ System.out.println("SUCCESS: executing: " + "make -C " + SIM_DIR);
+
+ String graphPath = SIM_DIR + "testgraph_" + s;
+ try {
+
+ String[] params = new String[3];
+
+ params[0] = "./" + SIM_DIR + "run.x";
+ params[1] = "-cmd";
+ params[2] = "1 0; 1 7 100 100 " + graphPath;
+ proc = Runtime.getRuntime().exec(params);
+ proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
+
+ monitorError(proc);
+
+ while ((str = proc_in.readLine()) != null) {
+ // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
+ System.out.println("executing: " + str);
+ }
+ } catch (Exception e) {
+ // Probably make is not installed
+ System.out.println("FAILED: executing simulation " + e.getCause());
+ return;
+ }
+
+ File graphFile = new File(graphPath + ".aut");
+ String graphData = "";
+ try {
+ graphData = FileUtils.loadFileData(graphFile);
+ } catch (Exception e) {
+ assertTrue(false);
+ }
+
+ AUTGraph graph = new AUTGraph();
+ graph.buildGraph(graphData);
+
+ // States and transitions
+ System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates());
+ assertTrue(NB_OF_FCD_STATES[i] == graph.getNbOfStates());
+ System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions());
+ assertTrue(NB_OF_FCD_TRANSTIONS[i] == graph.getNbOfTransitions());
+
+ // Min and max cycles
+ int minValue = graph.getMinValue("allCPUsFPGAsTerminated");
+ System.out.println("executing: minvalue of " + s + " " + minValue);
+ assertTrue(MIN_FCD_CYCLES[i] == minValue);
+
+ int maxValue = graph.getMaxValue("allCPUsFPGAsTerminated");
+ System.out.println("executing: maxvalue of " + s + " " + maxValue);
+ assertTrue(MAX_FCD_CYCLES[i] == maxValue);
+ }
+ }
+}
\ No newline at end of file
diff --git a/ttool/src/test/resources/tmltranslator/simulator/fpga_clock_divider.xml b/ttool/src/test/resources/tmltranslator/simulator/fpga_clock_divider.xml
new file mode 100644
index 0000000000000000000000000000000000000000..e50167577f421b51af8df61a39613b9009149178
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/fpga_clock_divider.xml
@@ -0,0 +1,796 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<TURTLEGMODELING version="1.0beta" ANIMATE_INTERACTIVE_SIMULATION="false" ACTIVATE_PENALTIES="false" UPDATE_INFORMATION_DIPLO_SIM="false" ANIMATE_WITH_INFO_DIPLO_SIM="true" OPEN_DIAG_DIPLO_SIM="false" LAST_SELECTED_MAIN_TAB="1" LAST_SELECTED_SUB_TAB="0">
+
+<Modeling type="TML Component Design" nameTab="ApplicationSimple" tabs="TML Component Task Diagram$Src$T1$T2" >
+<TMLComponentTaskDiagramPanel name="TML Component Task Diagram" minX="10" maxX="2500" minY="10" maxY="1500" channels="true" events="true" requests="true" zoom="1.0" >
+<CONNECTOR type="126" id="1" >
+<cdparam x="335" y="300" />
+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="Connector between ports" />
+<P1 x="322" y="287" id="7" />
+<P2 x="427" y="287" id="20" />
+<AutomaticDrawing data="true" />
+</CONNECTOR>
+<CONNECTOR type="126" id="2" >
+<cdparam x="335" y="236" />
+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="Connector between ports" />
+<P1 x="322" y="224" id="5" />
+<P2 x="427" y="223" id="18" />
+<AutomaticDrawing data="true" />
+</CONNECTOR>
+<CONNECTOR type="126" id="3" >
+<cdparam x="590" y="305" />
+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="Connector between ports" />
+<P1 x="577" y="292" id="24" />
+<P2 x="683" y="289" id="37" />
+<AutomaticDrawing data="true" />
+</CONNECTOR>
+<CONNECTOR type="126" id="4" >
+<cdparam x="590" y="241" />
+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="Connector between ports" />
+<P1 x="577" y="228" id="22" />
+<P2 x="683" y="225" id="35" />
+<AutomaticDrawing data="true" />
+</CONNECTOR>
+<COMPONENT type="1202" id="17" uid="54a56387-8e3f-466e-8313-a55cc1278d79" >
+<cdparam x="122" y="175" />
+<sizeparam width="200" height="150" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Primitive component" value="Src" />
+<TGConnectingPoint num="0" id="9" />
+<TGConnectingPoint num="1" id="10" />
+<TGConnectingPoint num="2" id="11" />
+<TGConnectingPoint num="3" id="12" />
+<TGConnectingPoint num="4" id="13" />
+<TGConnectingPoint num="5" id="14" />
+<TGConnectingPoint num="6" id="15" />
+<TGConnectingPoint num="7" id="16" />
+<extraparam>
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ns" Operation="" />
+<Attribute access="2" id="size" value="10" type="0" typeOther="" />
+</extraparam>
+</COMPONENT>
+<SUBCOMPONENT type="1203" id="6" uid="a7edfb00-dc4e-4ffc-aba6-8dbaed6ff726" >
+<father id="17" num="0" />
+<cdparam x="309" y="224" />
+<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" />
+<infoparam name="Primitive port" value="Channel chToT1" />
+<TGConnectingPoint num="0" id="5" />
+<extraparam>
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+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="null" />
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+<infoparam name="connector" value="null" />
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+</CONNECTOR>
+
+</TMLActivityDiagramPanel>
+
+<TMLActivityDiagramPanel name="T2" minX="10" maxX="2500" minY="10" maxY="1500" zoom="1.0" >
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+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="stop state" value="null" />
+<TGConnectingPoint num="0" id="92" />
+</COMPONENT>
+
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+<hidden value="false" />
+<enabled value="true" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="execI" value="null" />
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+<TGConnectingPoint num="1" id="96" />
+</COMPONENT>
+<SUBCOMPONENT type="-1" id="94" uid="a4d108ca-9688-4c5c-8399-bb086ec5ae7d" >
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+<cdrectangleparam minX="-75" maxX="30" minY="10" maxY="30" />
+<infoparam name="value of the delay" value="size" />
+</SUBCOMPONENT>
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+<COMPONENT type="1009" id="100" uid="afa2957a-8992-4dd0-9df7-327cb9ed77d4" >
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+<hidden value="false" />
+<enabled value="true" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="read channel" value="chToT2(size) " />
+<TGConnectingPoint num="0" id="98" />
+<TGConnectingPoint num="1" id="99" />
+<extraparam>
+<Data channelName="chToT2" nbOfSamples="size" secPattern="" isAttacker="No" isEncForm="Yes" />
+</extraparam>
+</COMPONENT>
+
+<COMPONENT type="1010" id="103" uid="00b4c2cf-2c86-4835-9961-f3a72bca65da" >
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+<hidden value="false" />
+<enabled value="true" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="wait event" value="evtToT2(size) " />
+<TGConnectingPoint num="0" id="101" />
+<TGConnectingPoint num="1" id="102" />
+<extraparam>
+<Data eventName="evtToT2" nbOfParams="5" />
+<Param index="0" value="size" />
+</extraparam>
+</COMPONENT>
+
+<COMPONENT type="1000" id="105" uid="f77f0a02-b19c-47ea-8e5e-339e8c7c3c54" >
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+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="start state" value="null" />
+<TGConnectingPoint num="0" id="104" />
+</COMPONENT>
+
+<CONNECTOR type="115" id="106" >
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+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
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+<CONNECTOR type="115" id="107" >
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+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
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+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="null" />
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+</CONNECTOR>
+
+</TMLActivityDiagramPanel>
+
+</Modeling>
+
+
+
+
+<Modeling type="TML Architecture" nameTab="ArchitectureSimple" >
+<TMLArchiDiagramPanel name="DIPLODOCUS architecture and mapping Diagram" minX="10" maxX="2500" minY="10" maxY="1500" attributes="0" masterClockFrequency="200" zoom="1.0" >
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+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="FPGA0" value="name" />
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+<TGConnectingPoint num="22" id="159" />
+<TGConnectingPoint num="23" id="160" />
+<extraparam>
+<info stereotype="FPGA" nodeName="FPGA0" />
+<attributes capacity="100" byteDataSize="4" mappingPenalty="0" reconfigurationTime="50" goIdleTime="10" maxConsecutiveIdleCycles="10" execiTime="1" execcTime="1" clockRatio="2" operation ="" scheduling ="" />
+</extraparam>
+</COMPONENT>
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="82" minY="0" maxY="160" />
+<infoparam name="TGComponent" value="ApplicationSimple::T1" />
+<TGConnectingPoint num="0" id="110" />
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+<extraparam>
+<info value="ApplicationSimple::T1" taskName="T1" referenceTaskName="ApplicationSimple" priority="0" operationMEC="T1" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
+<SUBCOMPONENT type="1101" id="127" uid="0c0ac20d-5680-4120-bab4-7045bf0d682e" >
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="82" minY="0" maxY="160" />
+<infoparam name="TGComponent" value="ApplicationSimple::T2" />
+<TGConnectingPoint num="0" id="119" />
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+<TGConnectingPoint num="6" id="125" />
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+<extraparam>
+<info value="ApplicationSimple::T2" taskName="T2" referenceTaskName="ApplicationSimple" priority="0" operationMEC="T2" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="77" minY="0" maxY="160" />
+<infoparam name="TGComponent" value="ApplicationSimple::Src" />
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+<TGConnectingPoint num="1" id="129" />
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+<extraparam>
+<info value="ApplicationSimple::Src" taskName="Src" referenceTaskName="ApplicationSimple" priority="0" operationMEC="Src" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
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+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Memory0" value="name" />
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+<extraparam>
+<info stereotype="MEMORY" nodeName="Memory0" />
+<attributes byteDataSize="4" memorySize="1024" clockRatio="2" bufferType="0" />
+</extraparam>
+</COMPONENT>
+
+<COMPONENT type="1102" id="211" uid="2ec2a3b3-7027-4e01-a1b9-d61f986b9914" >
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+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Bus0" value="name" />
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+<TGConnectingPoint num="1" id="188" />
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+<TGConnectingPoint num="23" id="210" />
+<extraparam>
+<info stereotype="BUS-RR" nodeName="Bus0" />
+<attributes byteDataSize="4" arbitrationPolicy="0" sliceTime="10000" pipelineSize="1" clockRatio="2" privacy="0" referenceAttack="null" />
+</extraparam>
+</COMPONENT>
+
+<CONNECTOR type="125" id="212" >
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+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="{info}" />
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+<extraparam>
+<info priority="0" />
+<spy value="false" />
+</extraparam>
+</CONNECTOR>
+<CONNECTOR type="125" id="213" >
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+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="{info}" />
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+<extraparam>
+<info priority="0" />
+<spy value="false" />
+</extraparam>
+</CONNECTOR>
+
+</TMLArchiDiagramPanel>
+
+</Modeling>
+
+
+
+
+</TURTLEGMODELING>
\ No newline at end of file