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mbe-tools
TTool
Commits
075fb308
Commit
075fb308
authored
May 13, 2022
by
Ludovic Apvrille
Browse files
Adding tmpa loading - still to be tested
parent
846e6764
Changes
19
Pipelines
1
Hide whitespace changes
Inline
Side-by-side
modeling/DIPLODOCUS/SmartCardProtocol.xml
View file @
075fb308
<?xml version="1.0" encoding="UTF-8"?>
<TURTLEGMODELING
version=
"1.0beta"
ANIMATE_INTERACTIVE_SIMULATION=
"true"
ACTIVATE_PENALTIES=
"true"
UPDATE_INFORMATION_DIPLO_SIM=
"true"
ANIMATE_WITH_INFO_DIPLO_SIM=
"true"
OPEN_DIAG_DIPLO_SIM=
"false"
LAST_SELECTED_MAIN_TAB=
"
0
"
LAST_SELECTED_SUB_TAB=
"
2
"
>
<TURTLEGMODELING
version=
"1.0beta"
ANIMATE_INTERACTIVE_SIMULATION=
"true"
ACTIVATE_PENALTIES=
"true"
UPDATE_INFORMATION_DIPLO_SIM=
"true"
ANIMATE_WITH_INFO_DIPLO_SIM=
"true"
OPEN_DIAG_DIPLO_SIM=
"false"
LAST_SELECTED_MAIN_TAB=
"
3
"
LAST_SELECTED_SUB_TAB=
"
0
"
>
<Modeling
type=
"TML Component Design"
nameTab=
"AppC"
tabs=
"TML Component Task Diagram$Application$TCPIP$Timer$InterfaceDevice$SmartCard"
>
<TMLComponentTaskDiagramPanel
name=
"TML Component Task Diagram"
minX=
"0"
maxX=
"2724"
minY=
"0"
maxY=
"916"
channels=
"true"
events=
"true"
requests=
"true"
considerExecOperators=
"true"
considerTimingOperators=
"true"
zoom=
"1.0000000000000018"
>
...
...
@@ -2486,7 +2486,7 @@
</SUBCOMPONENT>
<SUBCOMPONENT
type=
"-1"
id=
"474"
index=
"358"
uid=
"1fe5d2e4-894b-4c92-aeeb-f8e9c328c824"
>
<father
id=
"479"
num=
"2"
/>
<cdparam
x=
"3
06
"
y=
"616"
/>
<cdparam
x=
"3
12
"
y=
"616"
/>
<sizeparam
width=
"116"
height=
"15"
minWidth=
"10"
minHeight=
"1"
maxWidth=
"2000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<hidden
value=
"false"
/>
<enabled
value=
"true"
/>
...
...
@@ -2746,7 +2746,7 @@
</COMPONENT>
<COMPONENT
type=
"1001"
id=
"551"
index=
"49"
uid=
"71de86e8-6825-4234-bd32-30f8994a77f8"
>
<cdparam
x=
"3
19
"
y=
"6
14
"
/>
<cdparam
x=
"3
45
"
y=
"6
63
"
/>
<sizeparam
width=
"20"
height=
"20"
minWidth=
"1"
minHeight=
"1"
maxWidth=
"2000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<hidden
value=
"false"
/>
<cdrectangleparam
minX=
"10"
maxX=
"2900"
minY=
"10"
maxY=
"1900"
/>
...
...
@@ -4468,7 +4468,7 @@ On prend b=1 comme exemple
<sizeparam
width=
"0"
height=
"0"
minWidth=
"0"
minHeight=
"0"
maxWidth=
"600"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<infoparam
name=
"connector from choice to stop state"
value=
"null"
/>
<P1
x=
"329"
y=
"579"
id=
"477"
/>
<P2
x=
"3
29
"
y=
"6
09
"
id=
"550"
/>
<P2
x=
"3
55
"
y=
"6
58
"
id=
"550"
/>
<AutomaticDrawing
data=
"true"
/>
</CONNECTOR>
<CONNECTOR
type=
"115"
id=
"1068"
index=
"185"
uid=
"36b1e5f5-7ef0-42b7-b18d-ba43d7bf55eb"
>
...
...
@@ -5693,7 +5693,7 @@ On prend b=1 comme exemple
<COMPONENT
type=
"301"
id=
"1260"
index=
"9"
uid=
"efa68893-2531-4600-8e89-a73485f7cffa"
>
<cdparam
x=
"453"
y=
"214"
/>
<sizeparam
width=
"105"
height=
"
15
"
minWidth=
"50"
minHeight=
"20"
maxWidth=
"2000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<sizeparam
width=
"105"
height=
"
20
"
minWidth=
"50"
minHeight=
"20"
maxWidth=
"2000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<hidden
value=
"false"
/>
<cdrectangleparam
minX=
"10"
maxX=
"1400"
minY=
"10"
maxY=
"900"
/>
<infoparam
name=
"UML Note"
value=
"data exchange
...
...
@@ -7160,8 +7160,8 @@ the smart card and the terminal
<Modeling
type=
"TML Architecture"
nameTab=
"Mapping3"
>
<TMLArchiDiagramPanel
name=
"DIPLODOCUS architecture and mapping Diagram"
minX=
"10"
maxX=
"1400"
minY=
"10"
maxY=
"900"
attributes=
"0"
considerExecOperators=
"true"
considerTimingOperators=
"true"
masterClockFrequency=
"200"
zoom=
"1.0"
>
<COMPONENT
type=
"1105"
id=
"1746"
index=
"0"
uid=
"b246b90f-5bcf-40a2-9b50-9001b85188fc"
>
<cdparam
x=
"
30
9"
y=
"3
58
"
/>
<sizeparam
width=
"
189
"
height=
"1
31
"
minWidth=
"100"
minHeight=
"50"
maxWidth=
"2000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<cdparam
x=
"
26
9"
y=
"3
72
"
/>
<sizeparam
width=
"
268
"
height=
"1
82
"
minWidth=
"100"
minHeight=
"50"
maxWidth=
"2000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<hidden
value=
"false"
/>
<cdrectangleparam
minX=
"10"
maxX=
"1400"
minY=
"10"
maxY=
"900"
/>
<infoparam
name=
"Memory0"
value=
"name"
/>
...
...
@@ -7450,7 +7450,7 @@ the smart card and the terminal
<cdparam
x=
"402"
y=
"367"
/>
<sizeparam
width=
"0"
height=
"0"
minWidth=
"0"
minHeight=
"0"
maxWidth=
"1000"
maxHeight=
"2000"
minDesiredWidth=
"0"
minDesiredHeight=
"0"
/>
<infoparam
name=
"connector from Memory0 to Bus0"
value=
"{info}"
/>
<P1
x=
"403"
y=
"3
58
"
id=
"1723"
/>
<P1
x=
"403"
y=
"3
72
"
id=
"1723"
/>
<P2
x=
"403"
y=
"319"
id=
"1753"
/>
<AutomaticDrawing
data=
"true"
/>
<extraparam>
...
...
src/main/java/tmltranslator/TMLMapping.java
View file @
075fb308
...
...
@@ -177,7 +177,7 @@ public class TMLMapping<E> {
}
public
void
makeMinimumMapping
()
{
TraceManager
.
addDev
(
"M
AKE
minimum mapping"
);
TraceManager
.
addDev
(
"M
ake
minimum mapping"
);
HwCPU
cpu
;
HwMemory
mem
;
...
...
@@ -248,12 +248,17 @@ public class TMLMapping<E> {
}
if
(!
tmla
.
hasMemory
())
{
mem
=
new
HwMemory
(
"defaultMemory"
);
tmla
.
addHwNode
(
mem
);
}
else
{
mem
=
tmla
.
getFirstMemory
();
}
if
(!
tmla
.
hasBus
())
{
bus
=
new
HwBus
(
"defaultBus"
);
mem
=
new
HwMemory
(
"defaultMemory"
);
tmla
.
addHwNode
(
bus
);
tmla
.
addHwNode
(
mem
);
// Connect all possible nodes to that bus
cpt
=
0
;
for
(
HwNode
node:
tmla
.
getHwNodes
())
{
...
...
@@ -266,7 +271,7 @@ public class TMLMapping<E> {
}
}
// Add all channels on that bus
// Add all channels on that bus
and to that memory
Iterator
<
TMLChannel
>
channelIt
=
tmlm
.
getChannels
().
iterator
();
while
(
channelIt
.
hasNext
())
{
...
...
@@ -286,13 +291,16 @@ public class TMLMapping<E> {
makeAutomata
();
// Checking that all channels are mapped to at least on memory
Iterator
<
TMLChannel
>
channelIt
=
tmlm
.
getChannels
().
iterator
();
while
(
channelIt
.
hasNext
())
{
ch
=
channelIt
.
next
();
mem
=
getMemoryOfChannel
(
ch
);
if
(
mem
==
null
)
{
HwMemory
memD
=
getMemoryOfChannel
(
ch
);
if
(
memD
==
null
)
{
if
(
tmla
.
getMemories
().
size
()
==
1
)
{
addCommToHwCommNode
(
ch
,
mem
);
}
}
// TraceManager.addDev("Memory of channel " + ch + " is " + mem);
}
...
...
src/main/java/tmltranslator/TMLSyntaxChecking.java
View file @
075fb308
...
...
@@ -85,6 +85,7 @@ public class TMLSyntaxChecking {
private
final
String
INVALID_CHANNEL_PATH
=
"Channel path is invalid"
;
private
final
String
INVALID_BUS_PATH
=
"Bus path is invalid for channel"
;
// Should be a warning only
private
final
String
INVALID_ROUTING
=
"No possible routing for channel"
;
// Should be a warning only
private
final
String
LINK_ISSUE
=
"All components must be linked to a bus or be a bus"
;
private
final
String
DUPLICATE_PATH_TO_BUS
=
"Path to bus is duplicated"
;
// Should be a warning only
private
final
String
ONLY_ONE_NOC
=
"Only one NoC can be used"
;
// Should be a warning only
...
...
@@ -146,8 +147,10 @@ public class TMLSyntaxChecking {
checkNonDuplicatePathToBuses
();
checkOneNOC
();
checkRouting
();
//TraceManager.addDev("Checking link bus");
checkLinkBuses
();
// Check that if the
i
r is a memory for a channel, the memory is connected to the path
// Check that if ther
e
is a memory for a channel, the memory is connected to the path
}
}
...
...
@@ -866,7 +869,7 @@ public class TMLSyntaxChecking {
}
private
void
checkPathToMemoryFromAllHwCommNode
(
TMLChannel
ch
)
{
TraceManager
.
addDev
(
"Checking checkPathToMemoryFromAllHwCommNode"
);
//
TraceManager.addDev("Checking checkPathToMemoryFromAllHwCommNode");
HwMemory
mem
=
mapping
.
getMemoryOfChannel
(
ch
);
if
(
mem
!=
null
)
{
for
(
HwCommunicationNode
origin
:
mapping
.
getAllCommunicationNodesOfChannel
(
ch
))
{
...
...
@@ -920,7 +923,8 @@ public class TMLSyntaxChecking {
newList
.
add
(
link
.
hwnode
);
map
.
put
(
link
.
bus
,
newList
);
}
else
if
(
list
.
contains
(
link
.
hwnode
))
{
addErrorByReference
(
null
,
null
,
null
,
DUPLICATE_PATH_TO_BUS
+
": from "
+
link
.
hwnode
.
getName
()
+
" to "
+
link
.
bus
.
getName
(),
TMLError
.
ERROR_STRUCTURE
);
addErrorByReference
(
null
,
null
,
null
,
DUPLICATE_PATH_TO_BUS
+
": from "
+
link
.
hwnode
.
getName
()
+
" to "
+
link
.
bus
.
getName
(),
TMLError
.
ERROR_STRUCTURE
);
}
else
{
list
.
add
(
link
.
hwnode
);
}
...
...
@@ -929,7 +933,7 @@ public class TMLSyntaxChecking {
private
void
checkOneNOC
()
{
TraceManager
.
addDev
(
"Checking NOC Nodes"
);
//
TraceManager.addDev("Checking NOC Nodes");
int
nb
=
mapping
.
getNbOfNoCs
();
if
(
nb
>
1
)
{
...
...
@@ -951,6 +955,27 @@ public class TMLSyntaxChecking {
}
}
private
void
checkLinkBuses
()
{
for
(
HwNode
node:
mapping
.
getArch
().
getHwNodes
())
{
if
(!((
node
instanceof
HwBus
)
||
(
node
instanceof
HwNoC
)))
{
// Not a bus
// It must have one link to a bus
//TraceManager.addDev("Working with node=" + node.getName());
boolean
hasALink
=
false
;
for
(
HwLink
link:
mapping
.
getArch
().
getHwLinks
())
{
if
(
link
.
hwnode
==
node
)
{
//TraceManager.addDev("Link found from " + node.getName() + " to bus " + link.bus.getName());
hasALink
=
true
;
break
;
}
}
if
(!
hasALink
)
{
addError
(
null
,
null
,
LINK_ISSUE
+
": "
+
node
.
getName
()
+
" has not link to a bus"
,
TMLError
.
ERROR_STRUCTURE
);
}
}
}
}
}
src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
View file @
075fb308
...
...
@@ -929,7 +929,7 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
if
(
startNode
==
null
)
{
TraceManager
.
addDev
(
"NULL REFERENCE"
);
}
else
{
TraceManager
.
addDev
(
"startNode: "
+
startNode
.
getName
()
);
//
TraceManager.addDev( "startNode: " + startNode.getName() );
}
HwMemory
memory
=
getMemConnectedToBusChannelMapped
(
commNodes
,
null
,
commElemToRoute
);
...
...
@@ -985,8 +985,8 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
// first called with Maping:getCommunicationNodes
List
<
HwCommunicationNode
>
nodesToExplore
;
TraceManager
.
addDev
(
"No of comm nodes "
+
commNodes
.
size
());
TraceManager
.
addDev
(
"startNode="
+
startNode
);
//
TraceManager.addDev("No of comm nodes " + commNodes.size());
//
TraceManager.addDev("startNode=" + startNode);
boolean
busExploreMode
=
((
depth
&
1
)
==
0
);
if
(
busExploreMode
)
{
...
...
@@ -1041,7 +1041,7 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
commNodes
.
add
(
currNode
);
}
TraceManager
.
addDev
(
"Returning false"
);
//
TraceManager.addDev("Returning false");
return
false
;
}
...
...
src/main/java/ui/DrawerTMAPModeling.java
0 → 100644
View file @
075fb308
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
*
* ludovic.apvrille AT enst.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
package
ui
;
import
myutil.GraphicLib
;
import
myutil.TraceManager
;
import
tmltranslator.*
;
import
ui.tmlcompd.TMLCChannelOutPort
;
import
ui.tmlcompd.TMLCPortConnector
;
import
ui.tmldd.*
;
import
java.awt.*
;
import
java.util.HashMap
;
import
java.util.List
;
/**
* Class DrawerTMAPModeling
* Class having a list of different constraints
* Creation: 23/04/2010
*
* @author Ludovic APVRILLE
* @version 1.0 23/04/2010
*/
public
class
DrawerTMAPModeling
{
private
final
static
int
RADIUS
=
400
;
private
final
static
int
XCENTER
=
500
;
private
final
static
int
YCENTER
=
450
;
private
final
static
int
DEC_COMP_Y
=
45
;
private
final
static
int
LOOP_X
=
150
;
private
final
static
int
X_SPACE
=
300
;
private
MainGUI
mgui
;
private
boolean
hasError
;
private
HashMap
<
HwNode
,
TGComponent
>
nodeMap
;
public
DrawerTMAPModeling
(
MainGUI
_mgui
)
{
mgui
=
_mgui
;
}
private
void
check
(
boolean
condition
,
String
text
)
throws
MalformedTMLDesignException
{
if
(!
condition
)
{
throw
new
MalformedTMLDesignException
(
text
);
}
}
// Not thread-safe
public
void
drawTMAPModelingPanel
(
TMLMapping
tmap
,
TMLArchiPanel
panel
)
throws
MalformedTMLDesignException
{
TraceManager
.
addDev
(
"Drawing TMAP spec ..."
);
nodeMap
=
new
HashMap
<>();
hasError
=
false
;
if
(
tmap
==
null
)
{
TraceManager
.
addDev
(
"Null spec"
);
hasError
=
true
;
return
;
}
TMLSyntaxChecking
syntax
=
new
TMLSyntaxChecking
(
tmap
);
syntax
.
checkSyntax
();
if
(
syntax
.
hasErrors
()
>
0
)
{
TraceManager
.
addDev
(
"hasError"
);
TraceManager
.
addDev
(
"Errors found at syntax checking of TMAP:\n"
+
syntax
.
printErrors
());
hasError
=
true
;
return
;
}
TraceManager
.
addDev
(
"Making HW components"
);
makeBuses
(
tmap
,
panel
.
tmlap
);
makeOtherComponentsFromLinks
(
tmap
,
panel
.
tmlap
);
makeTaskMapping
(
tmap
,
panel
.
tmlap
);
makeChannelMapping
(
tmap
,
panel
.
tmlap
);
}
private
void
makeBuses
(
TMLMapping
tmap
,
TMLArchiDiagramPanel
panel
)
throws
MalformedTMLDesignException
{
int
busIndex
=
75
;
final
int
busY
=
350
;
TraceManager
.
addDev
(
"Nb of buses to investigate:"
+
tmap
.
getArch
().
getBUSs
().
size
());
for
(
HwNode
node
:
tmap
.
getArch
().
getBUSs
())
{
HwBus
bus
=
(
HwBus
)
node
;
TraceManager
.
addDev
(
"Adding bus:"
+
bus
.
getName
());
TMLArchiBUSNode
comp
=
new
TMLArchiBUSNode
(
busIndex
,
busY
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
true
,
null
,
panel
);
comp
.
setName
(
bus
.
getName
());
comp
.
setDataSize
(
bus
.
byteDataSize
);
comp
.
setPipelineSize
(
bus
.
pipelineSize
);
comp
.
setSliceTime
(
bus
.
sliceTime
);
comp
.
setBurstSize
(
bus
.
burstSize
);
comp
.
setArbitrationPolicy
(
bus
.
arbitration
);
comp
.
setPrivacy
(
bus
.
privacy
);
comp
.
setClockRatio
(
bus
.
clockRatio
);
comp
.
resize
(
comp
.
getWidth
(),
110
);
panel
.
addBuiltComponent
(
comp
);
nodeMap
.
put
(
bus
,
comp
);
busIndex
+=
comp
.
getWidth
()
+
X_SPACE
;
}
}
private
void
makeOtherComponentsFromLinks
(
TMLMapping
tmap
,
TMLArchiDiagramPanel
panel
)
throws
MalformedTMLDesignException
{
int
cpuIndex
=
50
;
int
memoryIndex
=
75
;
final
int
cpuY
=
50
;
final
int
memY
=
550
;
for
(
HwLink
link
:
tmap
.
getArch
().
getHwLinks
())
{
TGComponent
compBus
=
nodeMap
.
get
(
link
.
bus
);
check
(
compBus
!=
null
,
"Construction of bus failed"
);
TGComponent
tgc
=
nodeMap
.
get
(
link
.
hwnode
);
if
(
tgc
==
null
)
{
// We need to add the component
if
(
link
.
hwnode
instanceof
HwCPU
)
{
tgc
=
addCPU
((
HwCPU
)
(
link
.
hwnode
),
link
.
bus
,
panel
,
cpuIndex
,
cpuY
);
cpuIndex
+=
X_SPACE
;
}
else
if
(
link
.
hwnode
instanceof
HwFPGA
)
{
tgc
=
addFPGA
((
HwFPGA
)
(
link
.
hwnode
),
link
.
bus
,
panel
,
cpuIndex
,
cpuY
);
cpuIndex
+=
X_SPACE
;
}
else
if
(
link
.
hwnode
instanceof
HwA
)
{
tgc
=
addHwA
((
HwA
)
(
link
.
hwnode
),
link
.
bus
,
panel
,
cpuIndex
,
cpuY
);
cpuIndex
+=
X_SPACE
;
}
else
if
(
link
.
hwnode
instanceof
HwMemory
)
{
tgc
=
addMemory
((
HwMemory
)
(
link
.
hwnode
),
link
.
bus
,
panel
,
memoryIndex
,
memY
);
memoryIndex
+=
X_SPACE
;
}
else
if
(
link
.
hwnode
instanceof
HwBridge
)
{
tgc
=
addBridge
((
HwBridge
)
(
link
.
hwnode
),
link
.
bus
,
panel
,
memoryIndex
,
memY
);
memoryIndex
+=
X_SPACE
;
}
}
check
(
tgc
!=
null
,
"Invalid component: could not be added: "
+
link
.
hwnode
.
getClass
().
getName
()
+
" is not supported"
);
panel
.
addBuiltComponent
(
tgc
);
nodeMap
.
put
(
link
.
hwnode
,
tgc
);
addLinkConnector
(
tgc
,
compBus
,
panel
);
}
}
private
TMLArchiCPUNode
addCPU
(
HwCPU
cpu
,
HwBus
bus
,
TMLArchiDiagramPanel
panel
,
int
cpuIndex
,
int
cpuY
)
{
TMLArchiCPUNode
cpuComp
=
new
TMLArchiCPUNode
(
cpuIndex
,
cpuY
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
true
,
null
,
panel
);
cpuComp
.
setName
(
cpu
.
getName
());
cpuComp
.
setNbOfCore
(
cpu
.
nbOfCores
);
cpuComp
.
setByteDataSize
(
cpu
.
byteDataSize
);
cpuComp
.
setPipelineSize
(
cpu
.
pipelineSize
);
cpuComp
.
setGoIdleTime
(
cpu
.
goIdleTime
);
cpuComp
.
setMaxConsecutiveIdleCycles
(
cpu
.
maxConsecutiveIdleCycles
);
cpuComp
.
setExeciTime
(
cpu
.
execiTime
);
cpuComp
.
setExeccTime
(
cpu
.
execcTime
);
cpuComp
.
setTaskSwitchingTime
(
cpu
.
taskSwitchingTime
);
cpuComp
.
setBranchingPredictionPenalty
(
cpu
.
branchingPredictionPenalty
);
cpuComp
.
setCacheMiss
(
cpu
.
cacheMiss
);
cpuComp
.
setSchedulingPolicy
(
cpu
.
schedulingPolicy
);
cpuComp
.
setSliceTime
(
cpu
.
sliceTime
);
cpuComp
.
setEncryption
(
cpu
.
encryption
);
return
cpuComp
;
}
private
TMLArchiHWANode
addHwA
(
HwA
hwa
,
HwBus
bus
,
TMLArchiDiagramPanel
panel
,
int
cpuIndex
,
int
cpuY
)
{
TMLArchiHWANode
hwaComp
=
new
TMLArchiHWANode
(
cpuIndex
,
cpuY
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
true
,
null
,
panel
);
hwaComp
.
setName
(
hwa
.
getName
());
hwaComp
.
setByteDataSize
(
hwa
.
byteDataSize
);
hwaComp
.
setExeciTime
(
hwa
.
execiTime
);
hwaComp
.
setExeccTime
(
hwa
.
execcTime
);
return
hwaComp
;
}
private
TMLArchiFPGANode
addFPGA
(
HwFPGA
fpga
,
HwBus
bus
,
TMLArchiDiagramPanel
panel
,
int
cpuIndex
,
int
cpuY
)
{
TMLArchiFPGANode
fpgaComp
=
new
TMLArchiFPGANode
(
cpuIndex
,
cpuY
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
true
,
null
,
panel
);
fpgaComp
.
setName
(
fpga
.
getName
());
fpgaComp
.
setCapacity
(
fpga
.
capacity
);
fpgaComp
.
setByteDataSize
(
fpga
.
byteDataSize
);
fpgaComp
.
setReconfigurationTime
(
fpga
.
reconfigurationTime
);
fpgaComp
.
setGoIdleTime
(
fpga
.
goIdleTime
);
fpgaComp
.
setMaxConsecutiveIdleCycles
(
fpga
.
maxConsecutiveIdleCycles
);
fpgaComp
.
setExeciTime
(
fpga
.
execiTime
);
fpgaComp
.
setExeccTime
(
fpga
.
execcTime
);
fpgaComp
.
setMappingPenalty
(
fpga
.
mappingPenalty
);
fpgaComp
.
setOperation
(
fpga
.
getOperation
());
fpgaComp
.
setScheduling
(
fpga
.
scheduling
);
return
fpgaComp
;
}
private
TMLArchiMemoryNode
addMemory
(
HwMemory
mem
,
HwBus
bus
,
TMLArchiDiagramPanel
panel
,
int
memIndex
,
int
memY
)
{
TMLArchiMemoryNode
memComp
=
new
TMLArchiMemoryNode
(
memIndex
,
memY
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
true
,
null
,
panel
);
memComp
.
setName
(
mem
.
getName
());
memComp
.
setByteDataSize
(
mem
.
byteDataSize
);
memComp
.
setMemorySize
(
mem
.
memorySize
);
memComp
.
setBufferType
(
mem
.
bufferType
);
return
memComp
;
}
private
TMLArchiBridgeNode
addBridge
(
HwBridge
bridge
,
HwBus
bus
,
TMLArchiDiagramPanel
panel
,
int
memIndex
,
int
memY
)
{
TMLArchiBridgeNode
bridgeComp
=
new
TMLArchiBridgeNode
(
memIndex
,
memY
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
true
,
null
,
panel
);
bridgeComp
.
setName
(
bridge
.
getName
());
bridgeComp
.
setBufferByteDataSize
(
bridge
.
bufferByteSize
);
return
bridgeComp
;
}
@SuppressWarnings
(
"unchecked"
)
private
void
makeTaskMapping
(
TMLMapping
tmap
,
TMLArchiDiagramPanel
panel
)
throws
MalformedTMLDesignException
{
int
cpt
=
0
;
List
<
HwExecutionNode
>
onnodes
=
tmap
.
getNodes
();
List
<
TMLTask
>
tasks
=
tmap
.
getMappedTasks
();
check
(
onnodes
.
size
()
==
tasks
.
size
(),
"Tasks and execution nodes in mapping should be of the same dimension"
);
for
(
cpt
=
0
;
cpt
<
onnodes
.
size
();
cpt
++)
{
HwExecutionNode
node
=
onnodes
.
get
(
cpt
);
TMLTask
task
=
tasks
.
get
(
cpt
);
TGComponent
tgc
=
nodeMap
.
get
(
node
);
check
(
tgc
!=
null
,
"No graphical component corresponding to execution node "
+
node
.
getName
());
check
(
tgc
instanceof
SwallowTGComponent
&&
tgc
instanceof
TMLArchiElementInterface
,
"Invalid graphical component for task "
+
task
.
getName
());
Point
p
=
getRandomCoordinate
(
tgc
);
TMLArchiArtifact
artifact
=
new
TMLArchiArtifact
(
p
.
x
,
p
.
y
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
false
,
tgc
,
panel
);
String
refAndName
=
task
.
getName
();
String
[]
splitName
=
refAndName
.
split
(
"__"
);
if
(
splitName
.
length
>=
2
)
{
artifact
.
setTaskName
(
splitName
[
1
]);
artifact
.
setReferenceTaskName
(
splitName
[
0
]);
}
else
{
artifact
.
setTaskName
(
refAndName
);
}
artifact
.
makeFullValue
();
artifact
.
setPriority
(
task
.
getPriority
());
artifact
.
setOperation
(
task
.
getOperation
());
panel
.
addComponent
(
artifact
,
p
.
x
,
p
.
y
,
true
,
true
);
}
}
@SuppressWarnings
(
"unchecked"
)
private
void
makeChannelMapping
(
TMLMapping
tmap
,
TMLArchiDiagramPanel
panel
)
throws
MalformedTMLDesignException
{
int
cpt
=
0
;
List
<
HwCommunicationNode
>
oncommnodes
=
tmap
.
getCommunicationNodes
();
List
<
TMLElement
>
elts
=
tmap
.
getMappedCommunicationElement
();
check
(
oncommnodes
.
size
()
==
elts
.
size
(),
"Tasks and execution nodes in mapping should be of the same dimension"
);
for
(
cpt
=
0
;
cpt
<
oncommnodes
.
size
();
cpt
++)
{
HwCommunicationNode
node
=
oncommnodes
.
get
(
cpt
);
TMLElement
elt
=
elts
.
get
(
cpt
);
TGComponent
tgc
=
nodeMap
.
get
(
node
);
check
(
tgc
!=
null
,
"No graphical component corresponding to communication node "
+
node
.
getName
());
check
(
tgc
instanceof
SwallowTGComponent
&&
tgc
instanceof
TMLArchiElementInterface
,
"Invalid graphical component for task "
+
node
.
getName
());
Point
p
=
getRandomCoordinate
(
tgc
);
TMLArchiCommunicationArtifact
artifact
=
new
TMLArchiCommunicationArtifact
(
p
.
x
,
p
.
y
,
panel
.
getMinX
(),
panel
.
getMaxX
(),
panel
.
getMinY
(),
panel
.
getMaxY
(),
false
,
tgc
,
panel
);
String
refAndName
=
elt
.
getName
();
String
[]
splitName
=
refAndName
.
split
(
"__"
);
if
(
splitName
.
length
>=
2
)
{
artifact
.
setCommunicationName
(
splitName
[
1
]);
artifact
.
setReferenceCommunicationName
(
splitName
[
0
]);
}
else
{
artifact
.
setCommunicationName
(
refAndName
);
}
panel
.
addComponent
(
artifact
,
p
.
x
,
p
.
y
,
true
,
true
);
}
}
private
void
addLinkConnector
(
TGComponent
p1
,
TGComponent
p2
,
TMLArchiDiagramPanel
panel
)
throws
MalformedTMLDesignException
{
check
(
p1
!=
null
,
"Null component at origin of link connector"
);
check
(
p2
!=
null
,
"Null component at destination of link connector"
);
int
myX
=
p1
.
getX
()
+
p1
.
getWidth
()
/
2
;
int
myY
=
p1
.
getY
()
+
p1
.
getHeight
()
/
2
;
Point
pt1
=
computePoint
(
p1
,
p2
);
Point
pt2
=
computePoint
(
p2
,
p1
);
check
(
pt1
!=
null
,
"No intersection in "
+
p1
.
getName
());
check
(
pt2
!=
null
,
"No intersection in "
+
p2
.
getName
());
TGConnectingPoint
tgcp1
=
p1
.
closerFreeTGConnectingPointCompatibility
(
pt1
.
x
,
pt1
.
y
,
true
,
false
,
TGComponentManager
.
CONNECTOR_NODE_TMLARCHI
);