From 08322f666ce5b1207dec5df4e890ed48e4447f15 Mon Sep 17 00:00:00 2001
From: Daniela Genius <genius@debussy.soc.lip6.fr>
Date: Thu, 30 Aug 2018 12:05:16 +0200
Subject: [PATCH] cleanup
---
MPSoC/mutekh/arch/soclib/deployinfo.h | 7 -
MPSoC/mutekh/arch/soclib/deployinfo_map.h | 118 ----
.../mutekh/arch/soclib/deployinfo_map.h-20-06 | 10 -
.../mutekh/arch/soclib/deployinfo_map.h27-06 | 10 -
MPSoC/mutekh/arch/soclib/deployinfo_ram.h | 175 ------
MPSoC/mutekh/arch/soclib/ldscript.cpp-15-05 | 255 ---------
MPSoC/mutekh/arch/soclib/ldscript.cpp-18-05 | 333 -----------
MPSoC/mutekh/arch/soclib/ldscript.cpp-19-05 | 252 --------
.../mutekh/arch/soclib/ldscript.cpp-2-2-2017 | 255 ---------
MPSoC/mutekh/arch/soclib/ldscript.cpp-20-06 | 255 ---------
MPSoC/mutekh/arch/soclib/ldscript.cpp-26-08 | 255 ---------
MPSoC/mutekh/arch/soclib/ldscript.cpp-27-06 | 255 ---------
MPSoC/mutekh/arch/soclib/ldscript.cpp-6-5 | 228 --------
MPSoC/mutekh/arch/soclib/ldscript.cpp-9-5 | 252 --------
MPSoC/mutekh/arch/soclib/ldscript.cpp-sav | 222 --------
.../__init__.py => mutekh/bin/test} | 0
MPSoC/mutekh/libmwmr/mwmr.config-07-12 | 38 --
MPSoC/mutekh/libmwmr/mwmr.config-1-8 | 38 --
MPSoC/mutekh/libmwmr/mwmr.config-23-06 | 38 --
MPSoC/mutekh/libmwmr/mwmr_soclib.c-01-08 | 401 -------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-02-2017 | 377 ------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-05 | 425 --------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-13-06 | 397 -------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-19-05 | 377 ------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-27-06 | 408 -------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-4-7 | 383 -------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-fonctionne | 409 -------------
.../libmwmr/mwmr_soclib.c-fully-instrumented | 425 --------------
MPSoC/mutekh/libmwmr/mwmr_soclib.c-orig | 377 ------------
.../mutekh/libmwmr/mwmr_soclib_debug_15_12.c | 409 -------------
.../platform_desc | 44 --
...platform_desc_c24f_236058371c7066fb__top.o | Bin 750808 -> 0 bytes
.../caba-vgmn-mutekh_kernel_tutorial/top.cc | 537 ------------------
.../utils/lib/python/sd_parser/__init__.pyc | Bin 165 -> 0 bytes
.../python/sd_parser/component_builder.pyc | Bin 10052 -> 0 bytes
.../utils/lib/python/sd_parser/module.pyc | Bin 13929 -> 0 bytes
.../utils/lib/python/sd_parser/platform.pyc | Bin 4317 -> 0 bytes
.../soclib/utils/lib/python/sd_parser/sd.pyc | Bin 2799 -> 0 bytes
.../lib/python/sd_parser/specialization.pyc | Bin 13924 -> 0 bytes
.../lib/python/soclib_builder/__init__.pyc | Bin 170 -> 0 bytes
.../utils/lib/python/soclib_builder/action.py | 291 ----------
.../lib/python/soclib_builder/action.pyc | Bin 12558 -> 0 bytes
.../utils/lib/python/soclib_builder/bblock.py | 208 -------
.../lib/python/soclib_builder/bblock.pyc | Bin 9020 -> 0 bytes
.../lib/python/soclib_builder/command.py | 190 -------
.../lib/python/soclib_builder/command.pyc | Bin 6918 -> 0 bytes
.../lib/python/soclib_builder/depends.py | 77 ---
.../lib/python/soclib_builder/depends.pyc | Bin 3102 -> 0 bytes
.../lib/python/soclib_builder/fileops.py | 46 --
.../lib/python/soclib_builder/fileops.pyc | Bin 1446 -> 0 bytes
.../lib/python/soclib_builder/mfparser.py | 60 --
.../lib/python/soclib_builder/mfparser.pyc | Bin 1908 -> 0 bytes
.../lib/python/soclib_builder/textfile.py | 55 --
.../lib/python/soclib_builder/textfile.pyc | Bin 1892 -> 0 bytes
.../utils/lib/python/soclib_builder/todo.py | 319 -----------
.../utils/lib/python/soclib_builder/todo.pyc | Bin 11211 -> 0 bytes
.../utils/lib/python/soclib_cc/__init__.pyc | Bin 280 -> 0 bytes
.../lib/python/soclib_cc/actions/__init__.pyc | Bin 288 -> 0 bytes
.../lib/python/soclib_cc/actions/cxx.pyc | Bin 8808 -> 0 bytes
.../lib/python/soclib_cc/actions/hdl.pyc | Bin 4079 -> 0 bytes
.../utils/lib/python/soclib_cc/bugreport.pyc | Bin 5577 -> 0 bytes
.../lib/python/soclib_cc/config/__init__.pyc | Bin 975 -> 0 bytes
.../lib/python/soclib_cc/config/objects.pyc | Bin 11379 -> 0 bytes
.../lib/python/soclib_cc/config/spool.pyc | Bin 7958 -> 0 bytes
.../utils/lib/python/soclib_cc/exceptions.pyc | Bin 414 -> 0 bytes
.../utils/lib/python/soclib_desc/__init__.pyc | Bin 324 -> 0 bytes
.../python/soclib_desc/_warning_formatter.pyc | Bin 910 -> 0 bytes
.../python/soclib_desc/abstraction_levels.pyc | Bin 3252 -> 0 bytes
.../utils/lib/python/soclib_desc/cache.pyc | Bin 4854 -> 0 bytes
.../python/soclib_desc/component_builder.pyc | Bin 1079 -> 0 bytes
.../python/soclib_desc/description_files.pyc | Bin 10204 -> 0 bytes
.../utils/lib/python/soclib_desc/error.pyc | Bin 6818 -> 0 bytes
.../lib/python/soclib_desc/metadata_file.pyc | Bin 6478 -> 0 bytes
.../utils/lib/python/soclib_desc/module.pyc | Bin 6525 -> 0 bytes
.../lib/python/soclib_desc/parameter.pyc | Bin 25313 -> 0 bytes
.../lib/python/soclib_desc/specialization.pyc | Bin 7763 -> 0 bytes
.../lib/python/soclib_utils/__init__.pyc | Bin 283 -> 0 bytes
.../lib/python/soclib_utils/terminal.pyc | Bin 875 -> 0 bytes
modeling/LIP6/monoprocessor.xml | 33 +-
modeling/testforkandjoin.xml | 338 +++++------
80 files changed, 191 insertions(+), 9391 deletions(-)
delete mode 100644 MPSoC/mutekh/arch/soclib/deployinfo.h
delete mode 100644 MPSoC/mutekh/arch/soclib/deployinfo_map.h
delete mode 100644 MPSoC/mutekh/arch/soclib/deployinfo_map.h-20-06
delete mode 100644 MPSoC/mutekh/arch/soclib/deployinfo_map.h27-06
delete mode 100644 MPSoC/mutekh/arch/soclib/deployinfo_ram.h
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-15-05
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-18-05
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-19-05
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-2-2-2017
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-20-06
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-26-08
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-27-06
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-6-5
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-9-5
delete mode 100644 MPSoC/mutekh/arch/soclib/ldscript.cpp-sav
rename MPSoC/{soclib/utils/lib/python/soclib_builder/__init__.py => mutekh/bin/test} (100%)
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr.config-07-12
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr.config-1-8
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr.config-23-06
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-01-08
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-02-2017
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-05
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-13-06
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-19-05
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-27-06
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-4-7
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-fonctionne
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-fully-instrumented
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib.c-orig
delete mode 100644 MPSoC/mutekh/libmwmr/mwmr_soclib_debug_15_12.c
delete mode 100644 MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/platform_desc
delete mode 100644 MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/systemc_64_caba:platform_desc_c24f_236058371c7066fb__top.o
delete mode 100644 MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/top.cc
delete mode 100644 MPSoC/soclib/utils/lib/python/sd_parser/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/sd_parser/component_builder.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/sd_parser/module.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/sd_parser/platform.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/sd_parser/sd.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/sd_parser/specialization.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/action.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/action.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/bblock.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/bblock.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/command.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/command.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/depends.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/depends.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/fileops.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/fileops.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/textfile.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/textfile.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/todo.py
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_builder/todo.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/actions/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/actions/cxx.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/actions/hdl.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/bugreport.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/config/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/config/objects.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/config/spool.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_cc/exceptions.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/_warning_formatter.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/abstraction_levels.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/cache.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/component_builder.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/description_files.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/error.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/metadata_file.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/module.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/parameter.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_desc/specialization.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_utils/__init__.pyc
delete mode 100644 MPSoC/soclib/utils/lib/python/soclib_utils/terminal.pyc
diff --git a/MPSoC/mutekh/arch/soclib/deployinfo.h b/MPSoC/mutekh/arch/soclib/deployinfo.h
deleted file mode 100644
index 6e62ce8967..0000000000
--- a/MPSoC/mutekh/arch/soclib/deployinfo.h
+++ /dev/null
@@ -1,7 +0,0 @@
-
-#define CACHED_RAM0_NAME cram0
-#define CACHED_RAM0_ADDR 0x10000000
-#define CACHED_RAM0_SIZE 0x80000
-#define DEPLOY_RAM0_NAME uram0
-#define DEPLOY_RAM0_ADDR 0x10280000
-#define DEPLOY_RAM0_SIZE 0x80000
diff --git a/MPSoC/mutekh/arch/soclib/deployinfo_map.h b/MPSoC/mutekh/arch/soclib/deployinfo_map.h
deleted file mode 100644
index 205c5bc796..0000000000
--- a/MPSoC/mutekh/arch/soclib/deployinfo_map.h
+++ /dev/null
@@ -1,118 +0,0 @@
-
-#define MAP_A\
-
- .channel0 : {*(section_channel0)} > uram0
-
- .channel1 : {*(section_channel1)} > uram0
-
- .channel2 : {*(section_channel2)} > uram0
-
- .channel3 : {*(section_channel3)} > uram0
-
- .channel4 : {*(section_channel4)} > uram0
-
- .channel5 : {*(section_channel5)} > uram0
-
- .channel6 : {*(section_channel6)} > uram0
-
- .channel7 : {*(section_channel7)} > uram0
-
- .channel8 : {*(section_channel8)} > uram0
-
- .channel9 : {*(section_channel9)} > uram0
-
- .channel10 : {*(section_channel10)} > uram0
-
- .channel11 : {*(section_channel11)} > uram0
-
- .channel12 : {*(section_channel12)} > uram0
-
- .channel13 : {*(section_channel13)} > uram0
-
- .channel14 : {*(section_channel14)} > uram0
-
- .channel15 : {*(section_channel15)} > uram0
-
- .channel16 : {*(section_channel16)} > uram0
-
- .channel17 : {*(section_channel17)} > uram0
-
- .channel18 : {*(section_channel18)} > uram0
-
- .channel19 : {*(section_channel19)} > uram0
-
- .channel20 : {*(section_channel20)} > uram0
-
- .channel21 : {*(section_channel21)} > uram0
-
- .channel22 : {*(section_channel22)} > uram0
-
- .channel23 : {*(section_channel23)} > uram0
-
- .channel24 : {*(section_channel24)} > uram0
-
- .channel25 : {*(section_channel25)} > uram0
-
- .channel26 : {*(section_channel26)} > uram0
-
- .channel27 : {*(section_channel27)} > uram0
-
- .channel28 : {*(section_channel28)} > uram0
-
- .lock0 : { *(section_lock0)} > uram0
-
- .lock1 : { *(section_lock1)} > uram0
-
- .lock2 : { *(section_lock2)} > uram0
-
- .lock3 : { *(section_lock3)} > uram0
-
- .lock4 : { *(section_lock4)} > uram0
-
- .lock5 : { *(section_lock5)} > uram0
-
- .lock6 : { *(section_lock6)} > uram0
-
- .lock7 : { *(section_lock7)} > uram0
-
- .lock8 : { *(section_lock8)} > uram0
-
- .lock9 : { *(section_lock9)} > uram0
-
- .lock10 : { *(section_lock10)} > uram0
-
- .lock11 : { *(section_lock11)} > uram0
-
- .lock12 : { *(section_lock12)} > uram0
-
- .lock13 : { *(section_lock13)} > uram0
-
- .lock14 : { *(section_lock14)} > uram0
-
- .lock15 : { *(section_lock15)} > uram0
-
- .lock16 : { *(section_lock16)} > uram0
-
- .lock17 : { *(section_lock17)} > uram0
-
- .lock18 : { *(section_lock18)} > uram0
-
- .lock19 : { *(section_lock19)} > uram0
-
- .lock20 : { *(section_lock20)} > uram0
-
- .lock21 : { *(section_lock21)} > uram0
-
- .lock22 : { *(section_lock22)} > uram0
-
- .lock23 : { *(section_lock23)} > uram0
-
- .lock24 : { *(section_lock24)} > uram0
-
- .lock25 : { *(section_lock25)} > uram0
-
- .lock26 : { *(section_lock26)} > uram0
-
- .lock27 : { *(section_lock27)} > uram0
-
- .lock28 : { *(section_lock28)} > uram0
diff --git a/MPSoC/mutekh/arch/soclib/deployinfo_map.h-20-06 b/MPSoC/mutekh/arch/soclib/deployinfo_map.h-20-06
deleted file mode 100644
index 1be00be913..0000000000
--- a/MPSoC/mutekh/arch/soclib/deployinfo_map.h-20-06
+++ /dev/null
@@ -1,10 +0,0 @@
-
-#define MAP_A\
-
- .channel0 : { \
-*(section_channel0)\
-} > uram0\
-
- .lock0 : { \
-*(section_lock0)\
-} > vci_locks\
diff --git a/MPSoC/mutekh/arch/soclib/deployinfo_map.h27-06 b/MPSoC/mutekh/arch/soclib/deployinfo_map.h27-06
deleted file mode 100644
index 1be00be913..0000000000
--- a/MPSoC/mutekh/arch/soclib/deployinfo_map.h27-06
+++ /dev/null
@@ -1,10 +0,0 @@
-
-#define MAP_A\
-
- .channel0 : { \
-*(section_channel0)\
-} > uram0\
-
- .lock0 : { \
-*(section_lock0)\
-} > vci_locks\
diff --git a/MPSoC/mutekh/arch/soclib/deployinfo_ram.h b/MPSoC/mutekh/arch/soclib/deployinfo_ram.h
deleted file mode 100644
index 9b0e9b56c1..0000000000
--- a/MPSoC/mutekh/arch/soclib/deployinfo_ram.h
+++ /dev/null
@@ -1,175 +0,0 @@
-
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL) : ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL) : ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL) : ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL) : ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL) : ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL) : ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL) : ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL) : ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL) : ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL) : ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL) : ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL) : ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL) : ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL) : ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL) : ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL) : ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL) : ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL) : ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL) : ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL) : ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-#if defined(DEPLOY_RAM10_NAME)
- DEPLOY_RAM10_NAME (RWAL) : ORIGIN = DEPLOY_RAM10_ADDR, LENGTH = DEPLOY_RAM10_SIZE
-#endif
-#if defined(CACHED_RAM10_NAME)
- CACHED_RAM10_NAME (RWAL) : ORIGIN = CACHED_RAM10_ADDR, LENGTH = CACHED_RAM10_SIZE
-#endif
-#if defined(DEPLOY_RAM11_NAME)
- DEPLOY_RAM11_NAME (RWAL) : ORIGIN = DEPLOY_RAM11_ADDR, LENGTH = DEPLOY_RAM11_SIZE
-#endif
-#if defined(CACHED_RAM11_NAME)
- CACHED_RAM11_NAME (RWAL) : ORIGIN = CACHED_RAM11_ADDR, LENGTH = CACHED_RAM11_SIZE
-#endif
-#if defined(DEPLOY_RAM12_NAME)
- DEPLOY_RAM12_NAME (RWAL) : ORIGIN = DEPLOY_RAM12_ADDR, LENGTH = DEPLOY_RAM12_SIZE
-#endif
-#if defined(CACHED_RAM12_NAME)
- CACHED_RAM12_NAME (RWAL) : ORIGIN = CACHED_RAM12_ADDR, LENGTH = CACHED_RAM12_SIZE
-#endif
-#if defined(DEPLOY_RAM13_NAME)
- DEPLOY_RAM13_NAME (RWAL) : ORIGIN = DEPLOY_RAM13_ADDR, LENGTH = DEPLOY_RAM13_SIZE
-#endif
-#if defined(CACHED_RAM13_NAME)
- CACHED_RAM13_NAME (RWAL) : ORIGIN = CACHED_RAM13_ADDR, LENGTH = CACHED_RAM13_SIZE
-#endif
-#if defined(DEPLOY_RAM14_NAME)
- DEPLOY_RAM14_NAME (RWAL) : ORIGIN = DEPLOY_RAM14_ADDR, LENGTH = DEPLOY_RAM14_SIZE
-#endif
-#if defined(CACHED_RAM14_NAME)
- CACHED_RAM14_NAME (RWAL) : ORIGIN = CACHED_RAM14_ADDR, LENGTH = CACHED_RAM14_SIZE
-#endif
-#if defined(DEPLOY_RAM15_NAME)
- DEPLOY_RAM15_NAME (RWAL) : ORIGIN = DEPLOY_RAM15_ADDR, LENGTH = DEPLOY_RAM15_SIZE
-#endif
-#if defined(CACHED_RAM15_NAME)
- CACHED_RAM15_NAME (RWAL) : ORIGIN = CACHED_RAM15_ADDR, LENGTH = CACHED_RAM15_SIZE
-#endif
-#if defined(DEPLOY_RAM16_NAME)
- DEPLOY_RAM16_NAME (RWAL) : ORIGIN = DEPLOY_RAM16_ADDR, LENGTH = DEPLOY_RAM16_SIZE
-#endif
-#if defined(CACHED_RAM16_NAME)
- CACHED_RAM16_NAME (RWAL) : ORIGIN = CACHED_RAM16_ADDR, LENGTH = CACHED_RAM16_SIZE
-#endif
-#if defined(DEPLOY_RAM17_NAME)
- DEPLOY_RAM17_NAME (RWAL) : ORIGIN = DEPLOY_RAM17_ADDR, LENGTH = DEPLOY_RAM17_SIZE
-#endif
-#if defined(CACHED_RAM17_NAME)
- CACHED_RAM17_NAME (RWAL) : ORIGIN = CACHED_RAM17_ADDR, LENGTH = CACHED_RAM17_SIZE
-#endif
-#if defined(DEPLOY_RAM18_NAME)
- DEPLOY_RAM18_NAME (RWAL) : ORIGIN = DEPLOY_RAM18_ADDR, LENGTH = DEPLOY_RAM18_SIZE
-#endif
-#if defined(CACHED_RAM18_NAME)
- CACHED_RAM18_NAME (RWAL) : ORIGIN = CACHED_RAM18_ADDR, LENGTH = CACHED_RAM18_SIZE
-#endif
-#if defined(DEPLOY_RAM19_NAME)
- DEPLOY_RAM19_NAME (RWAL) : ORIGIN = DEPLOY_RAM19_ADDR, LENGTH = DEPLOY_RAM19_SIZE
-#endif
-#if defined(CACHED_RAM19_NAME)
- CACHED_RAM19_NAME (RWAL) : ORIGIN = CACHED_RAM19_ADDR, LENGTH = CACHED_RAM19_SIZE
-#endif
-#if defined(DEPLOY_RAM20_NAME)
- DEPLOY_RAM20_NAME (RWAL) : ORIGIN = DEPLOY_RAM20_ADDR, LENGTH = DEPLOY_RAM20_SIZE
-#endif
-#if defined(CACHED_RAM20_NAME)
- CACHED_RAM20_NAME (RWAL) : ORIGIN = CACHED_RAM20_ADDR, LENGTH = CACHED_RAM20_SIZE
-#endif
-#if defined(DEPLOY_RAM21_NAME)
- DEPLOY_RAM21_NAME (RWAL) : ORIGIN = DEPLOY_RAM21_ADDR, LENGTH = DEPLOY_RAM21_SIZE
-#endif
-#if defined(CACHED_RAM21_NAME)
- CACHED_RAM21_NAME (RWAL) : ORIGIN = CACHED_RAM21_ADDR, LENGTH = CACHED_RAM21_SIZE
-#endif
-#if defined(DEPLOY_RAM22_NAME)
- DEPLOY_RAM22_NAME (RWAL) : ORIGIN = DEPLOY_RAM22_ADDR, LENGTH = DEPLOY_RAM22_SIZE
-#endif
-#if defined(CACHED_RAM22_NAME)
- CACHED_RAM22_NAME (RWAL) : ORIGIN = CACHED_RAM22_ADDR, LENGTH = CACHED_RAM22_SIZE
-#endif
-#if defined(DEPLOY_RAM23_NAME)
- DEPLOY_RAM23_NAME (RWAL) : ORIGIN = DEPLOY_RAM23_ADDR, LENGTH = DEPLOY_RAM23_SIZE
-#endif
-#if defined(CACHED_RAM23_NAME)
- CACHED_RAM23_NAME (RWAL) : ORIGIN = CACHED_RAM23_ADDR, LENGTH = CACHED_RAM23_SIZE
-#endif
-#if defined(DEPLOY_RAM24_NAME)
- DEPLOY_RAM24_NAME (RWAL) : ORIGIN = DEPLOY_RAM24_ADDR, LENGTH = DEPLOY_RAM24_SIZE
-#endif
-#if defined(CACHED_RAM24_NAME)
- CACHED_RAM24_NAME (RWAL) : ORIGIN = CACHED_RAM24_ADDR, LENGTH = CACHED_RAM24_SIZE
-#endif
-#if defined(DEPLOY_RAM25_NAME)
- DEPLOY_RAM25_NAME (RWAL) : ORIGIN = DEPLOY_RAM25_ADDR, LENGTH = DEPLOY_RAM25_SIZE
-#endif
-#if defined(CACHED_RAM25_NAME)
- CACHED_RAM25_NAME (RWAL) : ORIGIN = CACHED_RAM25_ADDR, LENGTH = CACHED_RAM25_SIZE
-#endif
-#if defined(DEPLOY_RAM26_NAME)
- DEPLOY_RAM26_NAME (RWAL) : ORIGIN = DEPLOY_RAM26_ADDR, LENGTH = DEPLOY_RAM26_SIZE
-#endif
-#if defined(CACHED_RAM26_NAME)
- CACHED_RAM26_NAME (RWAL) : ORIGIN = CACHED_RAM26_ADDR, LENGTH = CACHED_RAM26_SIZE
-#endif
-#if defined(DEPLOY_RAM27_NAME)
- DEPLOY_RAM27_NAME (RWAL) : ORIGIN = DEPLOY_RAM27_ADDR, LENGTH = DEPLOY_RAM27_SIZE
-#endif
-#if defined(CACHED_RAM27_NAME)
- CACHED_RAM27_NAME (RWAL) : ORIGIN = CACHED_RAM27_ADDR, LENGTH = CACHED_RAM27_SIZE
-#endif
-#if defined(DEPLOY_RAM28_NAME)
- DEPLOY_RAM28_NAME (RWAL) : ORIGIN = DEPLOY_RAM28_ADDR, LENGTH = DEPLOY_RAM28_SIZE
-#endif
-#if defined(CACHED_RAM28_NAME)
- CACHED_RAM28_NAME (RWAL) : ORIGIN = CACHED_RAM28_ADDR, LENGTH = CACHED_RAM28_SIZE
-#endif
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-15-05 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-15-05
deleted file mode 100644
index af21628dbc..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-15-05
+++ /dev/null
@@ -1,255 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-//mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-//mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS en cas de besoin (actually unused)
-vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//DG 19.5. a single RAMLOCKS
-// .lock0 : { *(section_lock0)} > vci_locks
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-18-05 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-18-05
deleted file mode 100644
index cb874fee26..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-18-05
+++ /dev/null
@@ -1,333 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-//mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-//mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS en cas de besoin (actually unused)
-vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(DEPLOY_RAM10_NAME)
- DEPLOY_RAM10_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM10_NAME)
- CACHED_RAM10_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM11_NAME)
- DEPLOY_RAM11_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM11_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM12_NAME)
- DEPLOY_RAM12_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM12_NAME)
- CACHED_RAM12_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM13_NAME)
- DEPLOY_RAM13_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM13_NAME)
- CACHED_RAM13_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM14_NAME)
- DEPLOY_RAM13_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM14_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM15_NAME)
- DEPLOY_RAM15_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM15_NAME)
- CACHED_RAM15_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM16_NAME)
- DEPLOY_RAM16_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM16_NAME)
- CACHED_RAM16_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM17_NAME)
- DEPLOY_RAM17_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM17_NAME)
- CACHED_RAM17_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM18_NAME)
- DEPLOY_RAM18_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM18_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM19_NAME)
- DEPLOY_RAM19_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM19_NAME)
- CACHED_RAM19_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-#if defined(DEPLOY_RAM20_NAME)
- DEPLOY_RAM20_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM20_NAME)
- CACHED_RAM20_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM21_NAME)
- DEPLOY_RAM21_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM21_NAME)
- CACHED_RAM21_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM22_NAME)
- DEPLOY_RAM22_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM22_NAME)
- CACHED_RAM22_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM23_NAME)
- DEPLOY_RAM23_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM24_NAME)
- DEPLOY_RAM24_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM25_NAME)
- DEPLOY_RAM25_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM26_NAME)
- DEPLOY_RAM26_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM27_NAME)
- DEPLOY_RAM27_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM28_NAME)
- DEPLOY_RAM28_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM29_NAME)
- DEPLOY_RAM29_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//DG 19.5. a single RAMLOCKS
-// .lock0 : { *(section_lock0)} > vci_locks
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-19-05 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-19-05
deleted file mode 100644
index e5166f6bbd..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-19-05
+++ /dev/null
@@ -1,252 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-2-2-2017 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-2-2-2017
deleted file mode 100644
index af21628dbc..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-2-2-2017
+++ /dev/null
@@ -1,255 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-//mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-//mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS en cas de besoin (actually unused)
-vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//DG 19.5. a single RAMLOCKS
-// .lock0 : { *(section_lock0)} > vci_locks
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-20-06 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-20-06
deleted file mode 100644
index bb1be4aabe..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-20-06
+++ /dev/null
@@ -1,255 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS
-vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//DG 19.5. a single RAMLOCKS
-// .lock0 : { *(section_lock0)} > vci_locks
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-26-08 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-26-08
deleted file mode 100644
index bb1be4aabe..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-26-08
+++ /dev/null
@@ -1,255 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS
-vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//DG 19.5. a single RAMLOCKS
-// .lock0 : { *(section_lock0)} > vci_locks
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-27-06 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-27-06
deleted file mode 100644
index bb1be4aabe..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-27-06
+++ /dev/null
@@ -1,255 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS
-vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//DG 19.5. a single RAMLOCKS
-// .lock0 : { *(section_lock0)} > vci_locks
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-6-5 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-6-5
deleted file mode 100644
index e78a51e50d..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-6-5
+++ /dev/null
@@ -1,228 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-9-5 b/MPSoC/mutekh/arch/soclib/ldscript.cpp-9-5
deleted file mode 100644
index e5166f6bbd..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-9-5
+++ /dev/null
@@ -1,252 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(CACHED_RAM0_NAME)
- CACHED_RAM0_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(CACHED_RAM1_NAME)
- CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(CACHED_RAM2_NAME)
- CACHED_RAM2_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
-#endif
-#if defined(CACHED_RAM4_NAME)
- CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
-#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
-#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
-#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
-#endif
-#if defined(CACHED_RAM8_NAME)
- CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
-#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp-sav b/MPSoC/mutekh/arch/soclib/ldscript.cpp-sav
deleted file mode 100644
index e1ce44fe8c..0000000000
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp-sav
+++ /dev/null
@@ -1,222 +0,0 @@
-/* The following contains information extracted from the deployment diagram */
-
-#include <arch/soclib/deployinfo.h>
-
-/*
- We may have aliasing in rom/except/boot segments. If so, we merge
- all we can in mem_rom segment.
-
- We may also have alisasing of ram/rom (for bootloaded kernels), so
- we may merge all we can in mem_ram.
- */
-
-/* ram + rom */
-#if CONFIG_RAM_ADDR == CONFIG_ROM_ADDR
-# define mem_rom mem_ram
-# if defined(CONFIG_CPU_RESET_HANDLER)
-# error You may not have a reset handler with rom in ram
-# endif
-#endif
-
-/* The first two may only happen if reset handler is present */
-#if defined(CONFIG_CPU_RESET_HANDLER)
-
-/* boot + rom */
-# if CONFIG_CPU_RESET_ADDR == CONFIG_ROM_ADDR
-# define mem_boot mem_rom
-# endif
-
-/* exception + boot
- *
- * boot may already be rom, and we'll have cascading defines */
-# if defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) && \
- (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_CPU_RESET_ADDR)
-# define mem_except mem_boot
-# endif
-
-#endif /* end if reset handler */
-
-
-/* exception + rom */
-#if ( (CONFIG_CPU_EXCEPTION_FIXED_ADDRESS == CONFIG_ROM_ADDR) || \
- !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS) ) && \
- !defined(mem_except)
-# define mem_except mem_rom
-#endif
-
-
-/*
- Implement .data from rom (copied at boot) by putting all r/w data at
- end of mem_rom. This is used for rom-only bootloaders.
- */
-#if defined(CONFIG_DATA_FROM_ROM)
-# define __AT_MEM_ROM AT>mem_rom
-#else
-# define __AT_MEM_ROM
-#endif
-
-
-MEMORY
-{
-#if defined(CONFIG_CPU_RESET_HANDLER) && !defined(mem_boot)
- mem_boot (RXAL) : ORIGIN = CONFIG_CPU_RESET_ADDR, LENGTH = CONFIG_CPU_RESET_SIZE
-#endif
-#if !defined(mem_except)
- mem_except (RXAL) : ORIGIN = CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, LENGTH = 0x1000
-#endif
-#ifdef CONFIG_HET_BUILD
- mem_hetrom (RXAL): ORIGIN = CONFIG_HETROM_ADDR, LENGTH = CONFIG_HETROM_SIZE
-#else
-# define mem_hetrom mem_rom
-#endif
-#if !defined(mem_rom)
- mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
-#endif
- mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-mwmrd_ram (RWAL): ORIGIN = 0x20200000, LENGTH = 0x00003000
-
-//ajoute DG
-#if defined(DEPLOY_RAM0_NAME)
- DEPLOY_RAM0_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
-#endif
-#if defined(DEPLOY_RAM1_NAME)
- DEPLOY_RAM1_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
-#endif
-#if defined(DEPLOY_RAM2_NAME)
- DEPLOY_RAM2_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
-#endif
-#if defined(DEPLOY_RAM3_NAME)
- DEPLOY_RAM3_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
-#endif
-#if defined(DEPLOY_RAM4_NAME)
- DEPLOY_RAM4_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
-#endif
-#if defined(DEPLOY_RAM5_NAME)
- DEPLOY_RAM5_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
-#endif
-#if defined(DEPLOY_RAM6_NAME)
- DEPLOY_RAM6_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
-#endif
-#if defined(DEPLOY_RAM7_NAME)
- DEPLOY_RAM7_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
-#endif
-#if defined(DEPLOY_RAM8_NAME)
- DEPLOY_RAM8_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
-#endif
-#if defined(DEPLOY_RAM9_NAME)
- DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
-#endif
-//fin ajoute DG
-}
-
-SECTIONS
-{
-#if defined(CONFIG_CPU_RESET_HANDLER)
- .boot : {
- KEEP(*(.boot*))
- } > mem_boot
-#endif
-
- .text : {
- *(.init*)
- *(.text*)
- *(.glue*)
- *(.got2)
- } > mem_hetrom
-
- .rodata : {
- *(.rodata*)
- . = ALIGN(4);
- global_driver_registry = .;
- KEEP(*(.drivers))
- global_driver_registry_end = .;
- } > mem_rom
-
- .excep : {
-#if !defined(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS)
- /* On some architectures, exception vector is freely
- * relocatable up to a given alignment.
- *
- * We must set the correct pointer ASAP in the boot sequence,
- * dont forget reset vector is optional...
- */
- . = ALIGN(CONFIG_CPU_EXCEPTION_ALIGN);
-#endif
- __exception_base_ptr = .;
- KEEP(*(.excep*))
- } > mem_except
-
-
- /* TLS/CLS are templates for newly allocated contexts/cpu's
- * private data. They are always read-only.
- *
- * On a non-smp machine, cpudata is read-write, but does not fall
- * in the cpudata section (it is normal global data), so we can
- * keep on linking this as r/o.
- */
-
- /* CPU local data section */
- .cpudata 0x0 : { *(.cpudata*) } AT> mem_rom
-
- __cpu_data_start = LOADADDR(.cpudata);
- __cpu_data_end = LOADADDR(.cpudata) + SIZEOF(.cpudata);
-
- /* Task local data section */
- .contextdata 0x0 : { *(.contextdata*) } AT> mem_rom
-
- __context_data_start = LOADADDR(.contextdata);
- __context_data_end = LOADADDR(.contextdata) + SIZEOF(.contextdata);
-
- .data : {
- __data_start = ABSOLUTE(.);
- *(.sdata*)
- *(.data*)
- *(.cpuarchdata*)
- } > mem_ram __AT_MEM_ROM
-//ajoute DG
-#include <arch/soclib/deployinfo_map.h>
-//MAP_A
-//fin ajoute DG
- __data_load_start = LOADADDR(.data);
- __data_load_end = LOADADDR(.data) + SIZEOF(.data);
-
-// #if defined(CONFIG_HET_BUILD)
-// /DISCARD/ : {
-// #else
- .bss : {
- __bss_start = ABSOLUTE(.);
-// #endif
- *(.sbss*)
- *(COMMON)
- *(.common*)
- *(.scommon*)
- *(.bss*)
-// #if !defined(CONFIG_HET_BUILD)
- __bss_end = ABSOLUTE(.);
- } > mem_ram
-// #else
-// }
-
-// __bss_end = 0;
-// __bss_start = 0;
-// #endif
-
- __system_uncached_heap_start = .;
- __system_uncached_heap_end = ORIGIN(mem_ram) + LENGTH(mem_ram);
-
-#if defined(CONFIG_CPU_RESET_HANDLER)
- . = ALIGN(CONFIG_HEXO_STACK_ALIGN);
- __initial_stack = __system_uncached_heap_end;
-#endif
-
- /* GOT section */
- /DISCARD/ : { *(.eh_frame) }
-
-#if !defined(CONFIG_CPU_NIOS2)
- ASSERT(__system_uncached_heap_start == __bss_end, "Unlinked sections found, please report a bug")
-#endif
-}
-
-ENTRY(arch_init)
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/__init__.py b/MPSoC/mutekh/bin/test
similarity index 100%
rename from MPSoC/soclib/utils/lib/python/soclib_builder/__init__.py
rename to MPSoC/mutekh/bin/test
diff --git a/MPSoC/mutekh/libmwmr/mwmr.config-07-12 b/MPSoC/mutekh/libmwmr/mwmr.config-07-12
deleted file mode 100644
index 895f3e2a01..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr.config-07-12
+++ /dev/null
@@ -1,38 +0,0 @@
-
-%config CONFIG_MWMR
- desc Mwmr middleware support
- module libmwmr
- single CONFIG_MWMR_SOCLIB CONFIG_MWMR_PTHREAD
-%config end
-
-%config CONFIG_MWMR_SOCLIB
- desc Mwmr on SOCLIB, with hardware protocol compatibility
- parent CONFIG_MWMR
- depend CONFIG_MUTEK_SCHEDULER
- depend CONFIG_ARCH_SOCLIB
-%config end
-
-%config CONFIG_MWMR_PTHREAD
- desc Mwmr on Pthreads, with no hardware protocol compatibility
- parent CONFIG_MWMR
- depend CONFIG_PTHREAD
-%config end
-
-%config CONFIG_MWMR_INSTRUMENTATION
- desc Mwmr timing observation, only under SRL
- parent CONFIG_MWMR
- depend CONFIG_MWMR_SOCLIB
- depend CONFIG_SRL
-%config end
-
-%config CONFIG_MWMR_USE_RAMLOCKS
- desc Mwmr is ramlocks based, only under SRL, does not change platform s lock backend
- parent CONFIG_MWMR
- depend CONFIG_SRL
-%config end
-
-%config CONFIG_MWMR_LOCKFREE
- desc Mwmr is completely using atomic operations, only under SRL, does not change platform s lock backend
- parent CONFIG_MWMR_SOCLIB
- depend CONFIG_SRL
-%config end
diff --git a/MPSoC/mutekh/libmwmr/mwmr.config-1-8 b/MPSoC/mutekh/libmwmr/mwmr.config-1-8
deleted file mode 100644
index e7573dcd39..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr.config-1-8
+++ /dev/null
@@ -1,38 +0,0 @@
-
-%config CONFIG_MWMR
- desc Mwmr middleware support
- module libmwmr
- single CONFIG_MWMR_SOCLIB #CONFIG_MWMR_PTHREAD
-%config end
-
-%config CONFIG_MWMR_SOCLIB
- desc Mwmr on SOCLIB, with hardware protocol compatibility
- parent CONFIG_MWMR
- depend CONFIG_MUTEK_SCHEDULER
- depend CONFIG_ARCH_SOCLIB
-%config end
-
-%config CONFIG_MWMR_PTHREAD
- desc Mwmr on Pthreads, with no hardware protocol compatibility
- parent CONFIG_MWMR
- depend CONFIG_PTHREAD
-%config end
-
-#%config CONFIG_MWMR_INSTRUMENTATION
-# desc Mwmr timing observation, only under SRL
-# parent CONFIG_MWMR
-# depend CONFIG_MWMR_SOCLIB
-# depend CONFIG_SRL
-#%config end
-
-#%config CONFIG_MWMR_USE_RAMLOCKS
-# desc Mwmr is ramlocks based, only under SRL, does not change platform s lock backend
-# parent CONFIG_MWMR
-# depend CONFIG_SRL
-#%config end
-
-#%config CONFIG_MWMR_LOCKFREE
-# desc Mwmr is completely using atomic operations, only under SRL, does not change platform s lock backend
-# parent CONFIG_MWMR_SOCLIB
-# depend CONFIG_SRL
-#%config end
diff --git a/MPSoC/mutekh/libmwmr/mwmr.config-23-06 b/MPSoC/mutekh/libmwmr/mwmr.config-23-06
deleted file mode 100644
index 895f3e2a01..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr.config-23-06
+++ /dev/null
@@ -1,38 +0,0 @@
-
-%config CONFIG_MWMR
- desc Mwmr middleware support
- module libmwmr
- single CONFIG_MWMR_SOCLIB CONFIG_MWMR_PTHREAD
-%config end
-
-%config CONFIG_MWMR_SOCLIB
- desc Mwmr on SOCLIB, with hardware protocol compatibility
- parent CONFIG_MWMR
- depend CONFIG_MUTEK_SCHEDULER
- depend CONFIG_ARCH_SOCLIB
-%config end
-
-%config CONFIG_MWMR_PTHREAD
- desc Mwmr on Pthreads, with no hardware protocol compatibility
- parent CONFIG_MWMR
- depend CONFIG_PTHREAD
-%config end
-
-%config CONFIG_MWMR_INSTRUMENTATION
- desc Mwmr timing observation, only under SRL
- parent CONFIG_MWMR
- depend CONFIG_MWMR_SOCLIB
- depend CONFIG_SRL
-%config end
-
-%config CONFIG_MWMR_USE_RAMLOCKS
- desc Mwmr is ramlocks based, only under SRL, does not change platform s lock backend
- parent CONFIG_MWMR
- depend CONFIG_SRL
-%config end
-
-%config CONFIG_MWMR_LOCKFREE
- desc Mwmr is completely using atomic operations, only under SRL, does not change platform s lock backend
- parent CONFIG_MWMR_SOCLIB
- depend CONFIG_SRL
-%config end
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-01-08 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-01-08
deleted file mode 100644
index 3134edf300..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-01-08
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-# include <stdio.h>
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("use ramlocks\n");
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
- pthread_yield();
-# else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-printf("do not use ramlocks\n");
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
- printf("use pthread; lock address %x value %x \n",(atomic_int_t*)&(fifo->status->lock),fifo->status->lock);
- while (cpu_atomic_bit_testset((atomic_int_t*)&(fifo->status->lock), 0)) {
- pthread_yield();
- }
-
-# else
-printf("do not use pthread\n");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- printf("I am here");
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len; printf("while lensw ");
- while (status.usage >= fifo->gdepth) {
- //DG c'est le cas d'echec pour cause de fifo pleine
- printf("while status.usage ");
- printf("status.usage : %x ", status.usage);
- printf("fifo address : %x ", fifo);
- printf("fifo->depth: %x ", fifo->depth);
- printf("fifo->width: %x ", fifo->width);
- printf("fifo->gdepth: %x ", fifo->gdepth);
- printf("fifo->status address: %x ", fifo->status);
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
- //#elif defined(CONFIG_PTHREAD)
-#elif defined(CONFIG_PTHREAD)&&defined(CONFIG_MWMR_PTHREAD)
- printf("pthread yield");
- pthread_yield();
-#else
- printf("cpu yield");
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- //DG ici on peut ecrire
- printf("lensw : %x ", lensw);
- printf("status.usage : %x ", status.usage);
- printf("fifo->gdepth: %x ", fifo->gdepth);
-
- while ( lensw && status.usage < fifo->gdepth ) {
-printf("while lensw&& status.usage ");
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );printf("$$$ end of write ");
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-02-2017 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-02-2017
deleted file mode 100644
index 43a31fc540..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-02-2017
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
- pthread_yield();
-# else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();
- }
-# else
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-05 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-05
deleted file mode 100644
index 6c19991416..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-10-05
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-#include <stdio.h> //DG 08.12.
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
- printf("##### MWMR LOCK ####");
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("##### MWMR USE RAMLOCKS ####");
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD ####");
- pthread_yield();
-# else
-printf("##### MWMR NON CONFIG_PTHREAD ####");
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_SRL ####");
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD2 ####");
-
-while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();printf("##### MWMR pthread_yield ####");
- }
-# else
-printf("##### MWMR ELSE ####");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
- //printf("###### MWMR SOCLIB WRITE100 #############\n");
- //printf("rehash_status : %s rptr %d wptr %d usage %d/depth %d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
-printf("###### MWMR SOCLIB 101 #############\n");
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
-printf("###### MWMR SOCLIB 101b #############\n");
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-printf("###### MWMR SOCLIB 101c #############\n");
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
- printf("###### MWMR SOCLIB READ 0 #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo ); printf("###### MWMR SOCLIB READ 1 #############\n");
- rehash_status( fifo, &status );
- while ( lensw ) {printf("lensw %x \n",lensw);
- size_t len;
- while ( status.usage < fifo->width ) { //DG 15.12.
- printf("status address %x\n", &status);
- printf("status.usage %x\n", status.usage);
- printf("fifo->width %x\n", fifo->width);
-
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
- printf("###### MWMR SOCLIB READ 2 #############\n");
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
- printf("###### MWMR SOCLIB READ 2bis #############\n");
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
-printf("###### MWMR SOCLIB READ 3 #############\n");
- mwmr_lock( fifo );
-printf("###### MWMR SOCLIB READ 4 #############\n");
-
- rehash_status( fifo, &status );
-printf("###### MWMR SOCLIB READ 4a #############\n");
- } //DG 15.12.
-printf("###### MWMR SOCLIB READ 4b #############\n");
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
-printf("###### MWMR SOCLIB READ 5 #############\n");
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
-printf("###### MWMR SOCLIB READ 6 #############\n");
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- printf("###### MWMR SOCLIB READ 7 #############\n");
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-printf("###### MWMR SOCLIB WRITE #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
- //printf("###### MWMR SOCLIB WRITE2 #############\n");
-printf(" %x \n",fifo);
-//printf(" %x \n",fifo->depth); DG 08.12. c'est ici que ca plante, fifo non initialise??
-printf("###### MWMR SOCLIB WRITE2 #############\n");
-//printf(" %x \n",fifo->lock); DG 08.12. c'est ici que ca plante, on n'a pas d elock!
- mwmr_lock( fifo );
-
-printf("###### MWMR SOCLIB WRITE3 #############\n");
-printf("###### MWMR SOCLIB WRITE3b #############\n");
- rehash_status( fifo, &status );
-printf("###### MWMR SOCLIB WRITE3c #############\n");
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
-printf("###### MWMR SOCLIB WRITE4 #############\n");
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
- printf("###### MWMR SOCLIB WRITE4 #######lensw %x \n",lensw);
-printf("###### MWMR SOCLIB WRITE4 #######fifo->gdepth %x \n",fifo->gdepth);
-
- if ( status.rptr <= status.wptr ){
-printf("###### MWMR SOCLIB WRITE4a #######fifo->gdepth %x \n",fifo->gdepth);
- len = (fifo->gdepth - status.wptr);
-printf("###### MWMR SOCLIB WRITE4a #######fifo->len %x \n",len);
-}
- else{
-printf("###### MWMR SOCLIB WRITE4b #######fifo->gdepth %x \n",fifo->gdepth);
- len = fifo->gdepth - status.usage;
- }
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- printf("######lensw %x", lensw);
-printf("######len %x", len);
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-printf("###### MWMR SOCLIB WRITE5 #############\n");
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-printf("###### MWMR SOCLIB WRITE6 #############\n");
- mwmr_unlock( fifo );
-printf("###### MWMR SOCLIB WRITE7 #############\n");
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-13-06 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-13-06
deleted file mode 100644
index 8a921ec888..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-13-06
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-#include <stdio.h> //DG 19.05. for debug
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-#define CONFIG_MWMR_USE_RAMLOCKS //DG 19.05.
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
-printf("debug lock\n");
-
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
-
- printf("debug lock 0 %x \n",fifo->lock);
-
- while (*((uint32_t *)fifo->lock) != 0) {
-
-# if defined(CONFIG_PTHREAD)
-printf("debug lock 1\n");
- pthread_yield();
-# else
-printf("debug lock 2\n");
- cpu_interrupt_disable();printf("debug lock 3\n");
- sched_context_switch();printf("debug lock 4\n");
- cpu_interrupt_enable();printf("debug lock 5\n");
-# endif
- }
-printf("debug lock 6\n");
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-printf("debug lock 7\n");
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
-printf("debug lock 8\n");
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
-printf("debug lock 9\n");
- }
-# elif defined(CONFIG_PTHREAD)
-printf("debug lock 10\n");
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- printf("debug lock 11\n"); pthread_yield();
- }
-# else
-printf("debug lock 12\n");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
- printf("**debug mwmr 0\n");
- mwmr_lock( fifo );
- printf("debug mwmr 1\n");
- rehash_status( fifo, &status ); printf("debug mwmr 2\n");
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- printf("debug mwmr 3\n");
- writeback_status( fifo, &status );
- printf("debug mwmr 4\n");
- mwmr_unlock( fifo ); printf("debug mwmr 5\n");
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
- printf("debug mwmr 6\n");
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-19-05 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-19-05
deleted file mode 100644
index 43a31fc540..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-19-05
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
- pthread_yield();
-# else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();
- }
-# else
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-27-06 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-27-06
deleted file mode 100644
index 58c866fc66..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-27-06
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-#include <stdio.h>
-
-//#undef CONFIG_PTHREAD
-
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-//#define CONFIG_MWMR_USE_RAMLOCKS
-//#undef CONFIG_MWMR_USE_RAMLOCKS
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
- // printf("test %x\n", (fifo)->lock);
- //printf("testbis %x\n", &((fifo)->lock));
- //printf("testlock %x \n",*((uint32_t *)fifo->lock));
-
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("test0\n");
- while (*((uint32_t *)fifo->lock) != 0) {
-
- //# if defined(CONFIG_PTHREAD)
- // printf("test2ter\n");
- // pthread_yield();
- //# else
- printf("test2bis\n");
- // cpu_interrupt_disable();
- // sched_context_switch();
- // cpu_interrupt_enable();
-
- printf("lock status before %x\n",(atomic_int_t*)&fifo->status->lock);
- cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);//DG 27.06.
- printf("lock status after %x\n",(atomic_int_t*)&fifo->status->lock);
- //# endif
- }
-printf("test3\n");
-#else
-printf("test4a\n");
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-printf("lock status before %x\n",(atomic_int_t*)&fifo->status->lock);
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-printf("lock status after %x\n",(atomic_int_t*)&fifo->status->lock);
-# elif defined(CONFIG_PTHREAD)
- printf("test4\n");
- printf("lock status before %x\n",(atomic_int_t*)&fifo->status->lock);
- // cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();
- printf("lock status in %x\n",(atomic_int_t*)&fifo->status->lock);
- }
- printf("lock status after %x\n",(atomic_int_t*)&fifo->status->lock);
-# else
-printf("test5\n");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
- printf("call read %x\n",fifo);
-
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
- printf("call write %x\n",fifo);
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-4-7 b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-4-7
deleted file mode 100644
index bafa13dce1..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-4-7
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-# include <stdio.h>
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("use ramlocks\n");
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
- pthread_yield();
-# else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-printf("do not use ramlocks\n");
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
- printf("use pthread; lock address %x value %x \n",(atomic_int_t*)&(fifo->status->lock),fifo->status->lock);
- while (cpu_atomic_bit_testset((atomic_int_t*)&(fifo->status->lock), 0)) {
- pthread_yield();
- }
-
-# else
-printf("do not use pthread\n");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-fonctionne b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-fonctionne
deleted file mode 100644
index 1531c4b40a..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-fonctionne
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-#include <stdio.h> //DG 08.12.
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
- printf("##### MWMR LOCK ####");
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("##### MWMR USE RAMLOCKS ####");
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD ####");
- pthread_yield();
-# else
-printf("##### MWMR NON CONFIG_PTHREAD ####");
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_SRL ####");
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD2 ####");
-
-while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();printf("##### MWMR pthread_yield ####");
- }
-# else
-printf("##### MWMR ELSE ####");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
- printf("rehash_status : %s rptr %d wptr %d usage %d/depth %d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
- printf("###### MWMR SOCLIB READ 0 #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo ); printf("###### MWMR SOCLIB READ 1 #############\n");
- rehash_status( fifo, &status );
- while ( lensw ) {printf("lensw %x \n",lensw);
- size_t len;
- while ( status.usage < fifo->width ) { //DG 15.12.
- printf("status address %x\n", &status);
- printf("status.usage %x\n", status.usage);
- printf("fifo->width %x\n", fifo->width);
-
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
- printf("###### MWMR SOCLIB READ 2 #############\n");
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
- printf("###### MWMR SOCLIB READ 2bis #############\n");
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
-printf("###### MWMR SOCLIB READ 3 #############\n");
- mwmr_lock( fifo );
-printf("###### MWMR SOCLIB READ 4 #############\n");
- rehash_status( fifo, &status );
- } //DG 15.12.
-printf("###### MWMR SOCLIB READ 4a #############\n");
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
-printf("###### MWMR SOCLIB READ 5 #############\n");
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
-printf("###### MWMR SOCLIB READ 6 #############\n");
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- printf("###### MWMR SOCLIB READ 7 #############\n");
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-printf("###### MWMR SOCLIB WRITE #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
- //printf("###### MWMR SOCLIB WRITE2 #############\n");
-printf(" %x \n",fifo);
-//printf(" %x \n",fifo->depth); DG 08.12. c'est ici que ca plante, fifo non initialise??
-printf("###### MWMR SOCLIB WRITE2 #############\n");
-//printf(" %x \n",fifo->lock); DG 08.12. c'est ici que ca plante, on n'a pas d elock!
- mwmr_lock( fifo );
-
-printf("###### MWMR SOCLIB WRITE3 #############\n");
-printf("###### MWMR SOCLIB WRITE3b #############\n");
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
-printf("###### MWMR SOCLIB WRITE4 #############\n");
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-printf("###### MWMR SOCLIB WRITE5 #############\n");
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-printf("###### MWMR SOCLIB WRITE6 #############\n");
- mwmr_unlock( fifo );
-printf("###### MWMR SOCLIB WRITE7 #############\n");
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-fully-instrumented b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-fully-instrumented
deleted file mode 100644
index 6c19991416..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-fully-instrumented
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-#include <stdio.h> //DG 08.12.
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
- printf("##### MWMR LOCK ####");
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("##### MWMR USE RAMLOCKS ####");
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD ####");
- pthread_yield();
-# else
-printf("##### MWMR NON CONFIG_PTHREAD ####");
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_SRL ####");
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD2 ####");
-
-while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();printf("##### MWMR pthread_yield ####");
- }
-# else
-printf("##### MWMR ELSE ####");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
- //printf("###### MWMR SOCLIB WRITE100 #############\n");
- //printf("rehash_status : %s rptr %d wptr %d usage %d/depth %d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
-printf("###### MWMR SOCLIB 101 #############\n");
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
-printf("###### MWMR SOCLIB 101b #############\n");
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-printf("###### MWMR SOCLIB 101c #############\n");
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
- printf("###### MWMR SOCLIB READ 0 #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo ); printf("###### MWMR SOCLIB READ 1 #############\n");
- rehash_status( fifo, &status );
- while ( lensw ) {printf("lensw %x \n",lensw);
- size_t len;
- while ( status.usage < fifo->width ) { //DG 15.12.
- printf("status address %x\n", &status);
- printf("status.usage %x\n", status.usage);
- printf("fifo->width %x\n", fifo->width);
-
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
- printf("###### MWMR SOCLIB READ 2 #############\n");
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
- printf("###### MWMR SOCLIB READ 2bis #############\n");
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
-printf("###### MWMR SOCLIB READ 3 #############\n");
- mwmr_lock( fifo );
-printf("###### MWMR SOCLIB READ 4 #############\n");
-
- rehash_status( fifo, &status );
-printf("###### MWMR SOCLIB READ 4a #############\n");
- } //DG 15.12.
-printf("###### MWMR SOCLIB READ 4b #############\n");
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
-printf("###### MWMR SOCLIB READ 5 #############\n");
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
-printf("###### MWMR SOCLIB READ 6 #############\n");
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- printf("###### MWMR SOCLIB READ 7 #############\n");
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-printf("###### MWMR SOCLIB WRITE #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
- //printf("###### MWMR SOCLIB WRITE2 #############\n");
-printf(" %x \n",fifo);
-//printf(" %x \n",fifo->depth); DG 08.12. c'est ici que ca plante, fifo non initialise??
-printf("###### MWMR SOCLIB WRITE2 #############\n");
-//printf(" %x \n",fifo->lock); DG 08.12. c'est ici que ca plante, on n'a pas d elock!
- mwmr_lock( fifo );
-
-printf("###### MWMR SOCLIB WRITE3 #############\n");
-printf("###### MWMR SOCLIB WRITE3b #############\n");
- rehash_status( fifo, &status );
-printf("###### MWMR SOCLIB WRITE3c #############\n");
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
-printf("###### MWMR SOCLIB WRITE4 #############\n");
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
- printf("###### MWMR SOCLIB WRITE4 #######lensw %x \n",lensw);
-printf("###### MWMR SOCLIB WRITE4 #######fifo->gdepth %x \n",fifo->gdepth);
-
- if ( status.rptr <= status.wptr ){
-printf("###### MWMR SOCLIB WRITE4a #######fifo->gdepth %x \n",fifo->gdepth);
- len = (fifo->gdepth - status.wptr);
-printf("###### MWMR SOCLIB WRITE4a #######fifo->len %x \n",len);
-}
- else{
-printf("###### MWMR SOCLIB WRITE4b #######fifo->gdepth %x \n",fifo->gdepth);
- len = fifo->gdepth - status.usage;
- }
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- printf("######lensw %x", lensw);
-printf("######len %x", len);
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-printf("###### MWMR SOCLIB WRITE5 #############\n");
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-printf("###### MWMR SOCLIB WRITE6 #############\n");
- mwmr_unlock( fifo );
-printf("###### MWMR SOCLIB WRITE7 #############\n");
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-orig b/MPSoC/mutekh/libmwmr/mwmr_soclib.c-orig
deleted file mode 100644
index 43a31fc540..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib.c-orig
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
- pthread_yield();
-# else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();
- }
-# else
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
-// srl_log_printf(NONE,"%s %d %d %d/%d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while ( status.usage < fifo->width ) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-
- mwmr_unlock( fifo );
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/mutekh/libmwmr/mwmr_soclib_debug_15_12.c b/MPSoC/mutekh/libmwmr/mwmr_soclib_debug_15_12.c
deleted file mode 100644
index 1531c4b40a..0000000000
--- a/MPSoC/mutekh/libmwmr/mwmr_soclib_debug_15_12.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * This file is part of MutekH.
- *
- * MutekH is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * MutekH is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with MutekH; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * Copyright (c) UPMC, Lip6, SoC
- * Nicolas Pouillon <nipo@ssji.net>, 2008
- */
-
-#include <mutek/scheduler.h>
-#include <hexo/types.h>
-#include <hexo/atomic.h>
-#include <hexo/iospace.h>
-#include <hexo/endian.h>
-#include <hexo/interrupt.h>
-#include <string.h>
-#include <mwmr/mwmr.h>
-#include <stdio.h> //DG 08.12.
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-# include <srl/srl_sched_wait.h>
-# include <srl/srl_log.h>
-# ifndef SRL_VERBOSITY
-# define SRL_VERBOSITY VERB_DEBUG
-# endif
-#elif defined(CONFIG_PTHREAD)
-# include <pthread.h>
-#endif
-
-static inline size_t min(size_t a, size_t b)
-{
- if ( a < b )
- return a;
- else
- return b;
-}
-
-void
-mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
- size_t no, const struct mwmr_s* mwmr )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_WAY, endian_le32(way));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_FIFO_NO, endian_le32(no));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_STATUS_ADDR, endian_le32((uintptr_t)mwmr->status));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_DEPTH, endian_le32(mwmr->gdepth));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_BUFFER_ADDR, endian_le32((uintptr_t)mwmr->buffer));
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_WIDTH, endian_le32((uintptr_t)mwmr->width));
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_LOCK_ADDR, endian_le32((uintptr_t)mwmr->lock));
-#endif
- cpu_mem_write_32( c + sizeof(uint32_t) * MWMR_CONFIG_RUNNING, endian_le32(1));
-}
-
-void mwmr_config( void *coproc, size_t no, const uint32_t val )
-{
- uintptr_t c = (uintptr_t)coproc;
- cpu_mem_write_32( c + sizeof(uint32_t) * no, val);
-}
-
-uint32_t mwmr_status( void *coproc, size_t no )
-{
- uintptr_t c = (uintptr_t)coproc;
- return cpu_mem_read_32( c + sizeof(uint32_t) * no );
-}
-
-static inline void mwmr_lock( struct mwmr_s *fifo )
-{
- printf("##### MWMR LOCK ####");
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- printf("##### MWMR USE RAMLOCKS ####");
- while (*((uint32_t *)fifo->lock) != 0) {
-# if defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD ####");
- pthread_yield();
-# else
-printf("##### MWMR NON CONFIG_PTHREAD ####");
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-# endif
- }
-#else
-# if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_SRL ####");
- while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
-/* cpu_interrupt_disable(); */
-/* sched_context_switch(); */
-/* cpu_interrupt_enable(); */
- srl_sched_wait_eq_le(&fifo->status->lock, 0);
- }
-# elif defined(CONFIG_PTHREAD)
-printf("##### MWMR CONFIG_PTHREAD2 ####");
-
-while (cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0)) {
- pthread_yield();printf("##### MWMR pthread_yield ####");
- }
-# else
-printf("##### MWMR ELSE ####");
- cpu_atomic_bit_waitset((atomic_int_t*)&fifo->status->lock, 0);
-# endif
-#endif
-}
-
-static inline uint32_t mwmr_try_lock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- return !!cpu_mem_read_32((uintptr_t)fifo->lock);
-#else
- return cpu_atomic_bit_testset((atomic_int_t*)&fifo->status->lock, 0);
-#endif
-}
-
-static inline void mwmr_unlock( struct mwmr_s *fifo )
-{
-#ifdef CONFIG_MWMR_USE_RAMLOCKS
- cpu_mem_write_32((uintptr_t)fifo->lock, 0);
-#else
- cpu_mem_write_32((uintptr_t)&fifo->status->lock, 0);
-#endif
-}
-
-typedef struct {
- uint32_t usage, wptr, rptr, modified;
-} local_mwmr_status_t;
-
-static inline void rehash_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- cpu_dcache_invld_buf((void*)fstatus, sizeof(*fstatus));
- status->usage = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->usage ));
- status->wptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->wptr ));
- status->rptr = endian_le32(cpu_mem_read_32( (uintptr_t)&fstatus->rptr ));
- status->modified = 0;
- printf("rehash_status : %s rptr %d wptr %d usage %d/depth %d\n", fifo->name, status->rptr, status->wptr, status->usage, fifo->gdepth);
-}
-
-static inline void writeback_status( struct mwmr_s *fifo, local_mwmr_status_t *status )
-{
- struct mwmr_status_s *fstatus = fifo->status;
- if ( !status->modified )
- return;
- cpu_mem_write_32( (uintptr_t)&fstatus->usage, endian_le32(status->usage) );
- cpu_mem_write_32( (uintptr_t)&fstatus->wptr, endian_le32(status->wptr) );
- cpu_mem_write_32( (uintptr_t)&fstatus->rptr, endian_le32(status->rptr) );
-}
-
-void mwmr_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
- printf("###### MWMR SOCLIB READ 0 #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- mwmr_lock( fifo ); printf("###### MWMR SOCLIB READ 1 #############\n");
- rehash_status( fifo, &status );
- while ( lensw ) {printf("lensw %x \n",lensw);
- size_t len;
- while ( status.usage < fifo->width ) { //DG 15.12.
- printf("status address %x\n", &status);
- printf("status.usage %x\n", status.usage);
- printf("fifo->width %x\n", fifo->width);
-
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
- printf("###### MWMR SOCLIB READ 2 #############\n");
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_ge_le(&fifo->status->usage, fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
- printf("###### MWMR SOCLIB READ 2bis #############\n");
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
-printf("###### MWMR SOCLIB READ 3 #############\n");
- mwmr_lock( fifo );
-printf("###### MWMR SOCLIB READ 4 #############\n");
- rehash_status( fifo, &status );
- } //DG 15.12.
-printf("###### MWMR SOCLIB READ 4a #############\n");
- while ( lensw && status.usage >= fifo->width ) {
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
-printf("###### MWMR SOCLIB READ 5 #############\n");
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- status.modified = 1;
- }
- }
-printf("###### MWMR SOCLIB READ 6 #############\n");
- writeback_status( fifo, &status );
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += tot;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- printf("###### MWMR SOCLIB READ 7 #############\n");
- mwmr_unlock( fifo );
-}
-
-void mwmr_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- local_mwmr_status_t status;
-
-printf("###### MWMR SOCLIB WRITE #############\n");
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- size_t tot = lensw/fifo->width;
- uint32_t access_begin = cpu_cycle_count();
-#endif
- //printf("###### MWMR SOCLIB WRITE2 #############\n");
-printf(" %x \n",fifo);
-//printf(" %x \n",fifo->depth); DG 08.12. c'est ici que ca plante, fifo non initialise??
-printf("###### MWMR SOCLIB WRITE2 #############\n");
-//printf(" %x \n",fifo->lock); DG 08.12. c'est ici que ca plante, on n'a pas d elock!
- mwmr_lock( fifo );
-
-printf("###### MWMR SOCLIB WRITE3 #############\n");
-printf("###### MWMR SOCLIB WRITE3b #############\n");
- rehash_status( fifo, &status );
- while ( lensw ) {
- size_t len;
- while (status.usage >= fifo->gdepth) {
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#if defined(CONFIG_SRL) && !defined(CONFIG_PTHREAD)
- srl_sched_wait_le_le(&fifo->status->usage, fifo->gdepth-fifo->width);
-#elif defined(CONFIG_PTHREAD)
- pthread_yield();
-#else
- cpu_interrupt_disable();
- sched_context_switch();
- cpu_interrupt_enable();
-#endif
- mwmr_lock( fifo );
- rehash_status( fifo, &status );
- }
-printf("###### MWMR SOCLIB WRITE4 #############\n");
- while ( lensw && status.usage < fifo->gdepth ) {
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- status.modified = 1;
- }
- }
- writeback_status( fifo, &status );
-printf("###### MWMR SOCLIB WRITE5 #############\n");
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += tot;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
-printf("###### MWMR SOCLIB WRITE6 #############\n");
- mwmr_unlock( fifo );
-printf("###### MWMR SOCLIB WRITE7 #############\n");
-}
-
-size_t mwmr_try_read( struct mwmr_s *fifo, void *_ptr, size_t lensw )
-{
- uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage >= fifo->width ) {
- size_t len;
- void *sptr;
-
- if ( status.rptr < status.wptr )
- len = status.usage;
- else
- len = (fifo->gdepth - status.rptr);
- len = min(len, lensw);
- sptr = &((uint8_t*)fifo->buffer)[status.rptr];
- cpu_dcache_invld_buf(sptr, len);
- memcpy( ptr, sptr, len );
- status.rptr += len;
- if ( status.rptr == fifo->gdepth )
- status.rptr = 0;
- ptr += len;
- status.usage -= len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
- mwmr_unlock( fifo );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_read += done/fifo->width;
- fifo->time_read += cpu_cycle_count()-access_begin;
-#endif
- return done;
-}
-
-size_t mwmr_try_write( struct mwmr_s *fifo, const void *_ptr, size_t lensw )
-{
- const uint8_t *ptr = _ptr;
- size_t done = 0;
- local_mwmr_status_t status;
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- uint32_t access_begin = cpu_cycle_count();
-#endif
-
- if ( mwmr_try_lock( fifo ) )
- return done;
- rehash_status( fifo, &status );
- while ( lensw && status.usage < fifo->gdepth ) {
- size_t len;
- void *dptr;
-
- if ( status.rptr <= status.wptr )
- len = (fifo->gdepth - status.wptr);
- else
- len = fifo->gdepth - status.usage;
- len = min(len, lensw);
- dptr = &((uint8_t*)fifo->buffer)[status.wptr];
- memcpy( dptr, ptr, len );
- status.wptr += len;
- if ( status.wptr == fifo->gdepth )
- status.wptr = 0;
- ptr += len;
- status.usage += len;
- lensw -= len;
- done += len;
- status.modified = 1;
- }
- writeback_status( fifo, &status );
-#ifdef CONFIG_MWMR_INSTRUMENTATION
- cpu_dcache_invld_buf(fifo, sizeof(*fifo));
- fifo->n_write += done/fifo->width;
- fifo->time_write += cpu_cycle_count()-access_begin;
-#endif
- mwmr_unlock( fifo );
- return done;
-}
-
-#ifdef CONFIG_MWMR_INSTRUMENTATION
-void mwmr_dump_stats( const struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- if ( mwmr->n_read )
- srl_log_printf(NONE, "read,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_read, mwmr->n_read );
- if ( mwmr->n_write )
- srl_log_printf(NONE, "write,%s,%d,%d,%d\n",
- mwmr->name, cpu_cycle_count(),
- mwmr->time_write, mwmr->n_write );
-}
-
-void mwmr_clear_stats( struct mwmr_s *mwmr )
-{
- cpu_dcache_invld_buf(mwmr, sizeof(*mwmr));
- mwmr->time_read =
- mwmr->n_read =
- mwmr->time_write =
- mwmr->n_write = 0;
-}
-#endif
diff --git a/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/platform_desc b/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/platform_desc
deleted file mode 100644
index 7bb2879a15..0000000000
--- a/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/platform_desc
+++ /dev/null
@@ -1,44 +0,0 @@
-
-use = [
-Uses('caba:vci_locks'),
-Uses('caba:vci_ram'),
-Uses('caba:vci_fdt_rom'),
-Uses('caba:vci_heterogeneous_rom'),
-Uses('caba:vci_multi_tty'),
-Uses('caba:vci_xicu'),
-Uses('caba:vci_block_device'),
-Uses('caba:vci_ethernet'),
-Uses('caba:vci_rttimer'),
-Uses('caba:vci_fd_access'),
-Uses('caba:vci_simhelper'),
-Uses('caba:vci_vgsb'),
-Uses('caba:vci_mwmr_stats'),
-Uses('caba:vci_logger'),
-Uses('caba:vci_local_crossbar'),
-Uses('caba:fifo_virtual_copro_wrapper'),
-Uses('common:elf_file_loader'),
-Uses('common:plain_file_loader'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:arm'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32eb'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32el'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:niosII'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:lm32'),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=8),
-Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=2),
- ]
-
-todo = Platform('caba', 'top.cc',
- uses=use,
- cell_size = 4,
- plen_size = 9,
- addr_size = 32,
- rerror_size = 1,
- clen_size = 1,
- rflag_size = 1,
- srcid_size = 8,
- pktid_size = 1,
- trdid_size = 1,
- wrplen_size = 1
-)
-
diff --git a/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/systemc_64_caba:platform_desc_c24f_236058371c7066fb__top.o b/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/systemc_64_caba:platform_desc_c24f_236058371c7066fb__top.o
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diff --git a/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/top.cc b/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/top.cc
deleted file mode 100644
index af437a6aa4..0000000000
--- a/MPSoC/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/top.cc
+++ /dev/null
@@ -1,537 +0,0 @@
-//-------------------------------Header------------------------------------
-
-#include <iostream>
-#include <cstdlib>
-#include <vector>
-#include <string>
-#include <stdexcept>
-#include <cstdarg>
-
-#define CONFIG_GDB_SERVER
-#define CONFIG_SOCLIB_MEMCHECK
-
-#include "iss_memchecker.h"
-#include "gdbserver.h"
-
-#include "ppc405.h"
-#include "niosII.h"
-#include "mips32.h"
-#include "arm.h"
-#include "sparcv8.h"
-#include "lm32.h"
-
-#include "mapping_table.h"
-#include "vci_fdt_rom.h"
-#include "vci_xcache_wrapper.h"
-#include "vci_ram.h"
-#include "vci_heterogeneous_rom.h"
-#include "vci_multi_tty.h"
-#include "vci_locks.h"
-#include "vci_xicu.h"
-#include "vci_mwmr_stats.h"
-#include "vci_vgsb.h"
-#include "mwmr_controller.h"
-#include "vci_mwmr_controller.h"
-#include "fifo_virtual_copro_wrapper.h"
-#include "vci_block_device.h"
-#include "vci_simhelper.h"
-#include "vci_fd_access.h"
-#include "vci_ethernet.h"
-#include "vci_rttimer.h"
-#include "vci_logger.h"
-#include "vci_local_crossbar.h"
-
-namespace {
-std::vector<std::string> stringArray(
- const char *first, ... )
-{
- std::vector<std::string> ret;
- va_list arg;
- va_start(arg, first);
- const char *s = first;
- while(s) {
- ret.push_back(std::string(s));
- s = va_arg(arg, const char *);
- };
- va_end(arg);
- return ret;
-}
-
-std::vector<int> intArray(
- const int length, ... )
-{
- int i;
- std::vector<int> ret;
- va_list arg;
- va_start(arg, length);
-
- for (i=0; i<length; ++i) {
- ret.push_back(va_arg(arg, int));
- };
- va_end(arg);
- return ret;
-}
-}
-
-using namespace soclib;
-using common::IntTab;
-using common::Segment;
-
-static common::MappingTable maptab(32, IntTab(8), IntTab(8), 0xfff00000);
-
-typedef caba::VciParams<4,9,32,1,1,1,8,1,1,1> vci_param;// Define our VCI parameters
-
-struct CpuEntry;
-
-
-
-#if defined(CONFIG_GDB_SERVER)
-# if defined(CONFIG_SOCLIB_MEMCHECK)
-# warning Using GDB and memchecker
-# define ISS_NEST(T) common::GdbServer<common::IssMemchecker<T> >
-# else
-# warning Using GDB
-# define ISS_NEST(T) common::GdbServer<T>
-# endif
-#elif defined(CONFIG_SOCLIB_MEMCHECK)
-# warning Using Memchecker
-# define ISS_NEST(T) common::GdbServer<common::IssMemchecker<T>
-#else
-# warning Using raw processor
-# define ISS_NEST(T) T
-#endif
-
-//**********************************************************************
-// Processor entry and connection code
-//**********************************************************************
-
-#define CPU_CONNECT(n) void (n)(CpuEntry *e, sc_core::sc_clock &clk, \
-sc_core::sc_signal<bool> &rstn, caba::VciSignals<vci_param> &m)
-
-#define INIT_TOOLS(n) void (n)(const common::Loader &ldr)
-
-#define NEW_CPU(n) caba::BaseModule * (n)(CpuEntry *e)
-
-struct CpuEntry {
- caba::BaseModule *cpu;
- common::Loader *text_ldr;
- sc_core::sc_signal<bool> *irq_sig;
- size_t irq_sig_count;
- std::string type;
- std::string name;
- int id;
- CPU_CONNECT(*connect);
- INIT_TOOLS(*init_tools);
- NEW_CPU(*new_cpu);
-};
-
- template <class Iss_>
- CPU_CONNECT(cpu_connect){
- typedef ISS_NEST(Iss_) Iss;
- caba::VciXcacheWrapper<vci_param, Iss> *cpu = static_cast<caba::VciXcacheWrapper<vci_param, Iss> *>(e->cpu);
- cpu->p_clk(clk);
- cpu->p_resetn(rstn);
- e->irq_sig_count = Iss::n_irq;
- e->irq_sig = new sc_core::sc_signal<bool>[Iss::n_irq];
- for ( size_t irq = 0; irq < (size_t)Iss::n_irq; ++irq )
- cpu->p_irq[irq](e->irq_sig[irq]);
- cpu->p_vci(m);
- }
-
-template <class Iss>
-INIT_TOOLS(initialize_tools){
-#if defined(CONFIG_GDB_SERVER)
-ISS_NEST(Iss)::set_loader(ldr);
-#endif
-#if defined(CONFIG_SOCLIB_MEMCHECK)
- common::IssMemchecker<Iss>::init(maptab, ldr, "vci_multi_tty0,vci_xicu,vci_block_device,vci_fd_acccess,vci_ethernet,vci_fdt_rom,vci_rttimer");
-#endif
-}
-
-template <class Iss>
-NEW_CPU(new_cpu){
-return new caba::VciXcacheWrapper<vci_param, ISS_NEST(Iss)>(e->name.c_str(), e->id, maptab, IntTab(e->id),4,4,4,4,4,4);
-}
-
-/***************************************************************************
---------------------Processor creation code-------------------------
-***************************************************************************/
-
-template <class Iss>
- CpuEntry * newCpuEntry_(CpuEntry *e){
- e->new_cpu = new_cpu<Iss>;
- e->connect = cpu_connect<Iss>;
- e->init_tools = initialize_tools<Iss>;
- return e;
-}
-
- struct CpuEntry * newCpuEntry(const std::string &type, int id, common::Loader *ldr) {
- CpuEntry *e = new CpuEntry;
- std::ostringstream o;
- o << type << "_" << id;
-
- e->cpu = 0;
- e->text_ldr = ldr;
- e->type = type;
- e->name = o.str();
- e->id = id;
-
- switch (type[0]) {
- case 'm':
- if (type == "mips32el")
- return newCpuEntry_<common::Mips32ElIss>(e);
- else if (type == "mips32eb")
- return newCpuEntry_<common::Mips32EbIss>(e);
-
- case 'a':
- if (type == "arm")
- return newCpuEntry_<common::ArmIss>(e);
- case 'n':
- if (type == "nios2")
- return newCpuEntry_<common::Nios2fIss>(e);
-
- case 'p':
- if (type == "ppc")return newCpuEntry_<common::Ppc405Iss>(e);
-
- case 's':
- if (type == "sparc")
- return newCpuEntry_<common::Sparcv8Iss<8> >(e);
- else if (type == "sparc_2wins")
- return newCpuEntry_<common::Sparcv8Iss<2> >(e);
-
- case 'l':
- if (type == "lm32")
- return newCpuEntry_<common::LM32Iss<true> >(e);
- }
-
- throw std::runtime_error(type + ": wrong processor type");
-}
-
-//**********************************************************************
-// Args parsing and netlist
-
-//**********************************************************************
-
-int _main(int argc, char **argv)
-{
-
- // Avoid repeating these everywhere
- std::vector<CpuEntry*> cpus;
- common::Loader data_ldr;
- data_ldr.memory_default(0x5a);
-
-
-//-----------------------mapping table------------------------
-
-// ppc segments
-
-maptab.add(Segment("resetppc", 0xffffff80, 0x0080, IntTab(1), true));
-maptab.add(Segment("resetnios", 0x00802000, 0x1000, IntTab(1), true));
-maptab.add(Segment("resetzero", 0x00000000, 0x1000, IntTab(1), true));
-maptab.add(Segment("resetmips", 0xbfc00000, 0x1000, IntTab(1), true));
-
-
-// RAM segments
-
-maptab.add(Segment("text", 0x60000000, 0x00100000, IntTab(0), true));
-maptab.add(Segment("rodata", 0x80000000, 0x01000000, IntTab(1), true));
-maptab.add(Segment("data", 0x7f000000, 0x01000000, IntTab(2), false));
-
-maptab.add(Segment("simhelper", 0xd3200000, 0x00000100, IntTab(3), false));
- maptab.add(Segment("vci_xicu", 0xd2200000, 0x00001000, IntTab(4), false));
-maptab.add(Segment("vci_rttimer", 0xd6000000, 0x00000100, IntTab(5), false));
-
-maptab.add(Segment("vci_fdt_rom", 0xe0000000, 0x00001000, IntTab(6), false));
-
-maptab.add(Segment("cram0", 0x10000000, 0x80000, IntTab(2), true));
-maptab.add(Segment("uram0", 0x10280000, 0x80000, IntTab(2), false));
-maptab.add(Segment("vci_multi_tty0" , 0xd0200000, 0x00000010, IntTab(7), false));
-maptab.add(Segment("vci_fd_access", 0xd4200000, 0x00000100, IntTab(8), false));
-maptab.add(Segment("vci_ethernet", 0xd5000000, 0x00000020, IntTab(9), false));
-maptab.add(Segment("vci_block_device", 0xd1200000, 0x00000020, IntTab(10), false));
-
-maptab.add(Segment("vci_locks", 0xC0200000, 0x00000100, IntTab(11), false));
-
-
-
-//-------------------------Call Loader---------------------------------
-
-std::cerr << "caba-vgmn-mutekh_kernel_tutorial SoCLib simulator for MutekH" << std::endl;
-
-if ( (argc < 2) || ((argc % 2) == 0) ) {
-exit(0); }
- argc--;
- argv++;
-
-bool heterogeneous = (argc > 2);
-
- for (int i = 0; i < (argc - 1); i += 2){
- char *cpu_p = argv[i];
- const char *kernel_p = argv[i+1];
- const char *arch_str = strsep(&cpu_p, ":");
- int count = cpu_p ? atoi(cpu_p) : 1;
- common::Loader *text_ldr;
- if (heterogeneous) {
- text_ldr = new common::Loader(std::string(kernel_p) + ";.text");
- text_ldr->memory_default(0x5a);;
- data_ldr.load_file(std::string(kernel_p) + ";.rodata;.boot;.excep");
- if (i == 0)
- data_ldr.load_file(std::string(kernel_p) + ";.data;.channel0;.channel1;.channel2;.channel3;.channel4;.channel5;.channel6;.channel7;.channel8;.channel9;.channel10;.channel11;.channel12;.channel13;.channel14;.channel15;.channel16;.channel17;.channel18;.channel19;.channel20;.channel21;.channel22;.channel23;.channel24;.channel25;.channel26;.channel27;.channel28;.cpudata;.contextdata");
- } else {
- text_ldr = new common::Loader(std::string(kernel_p));
- text_ldr->memory_default(0x5a);
- data_ldr.load_file(std::string(kernel_p));
- }
-
- common::Loader tools_ldr(kernel_p);
- tools_ldr.memory_default(0x5a);
-
- for (int j = 0; j < count; j++) {
- int id = cpus.size();
- std::cerr << "***" << cpus.size() << std::endl;
- CpuEntry *e = newCpuEntry(arch_str, id, text_ldr);
- if (j == 0)
- e->init_tools(tools_ldr);
- e->cpu = e->new_cpu(e);
- cpus.push_back(e);
- }
- }
-
- const size_t xicu_n_irq = 5;
-
-//----------------------------Instantiation-------------------------------
-
-
-caba::VciHeterogeneousRom<vci_param> vcihetrom("vcihetrom", IntTab(0), maptab);
-caba::VciRam<vci_param> vcirom("vcirom", IntTab(1), maptab, data_ldr);
- caba::VciSimhelper<vci_param> vcisimhelper ("vcisimhelper", IntTab(3), maptab);
-caba::VciXicu<vci_param> vcixicu("vci_xicu", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());
-caba::VciRtTimer<vci_param> vcirttimer ("vcirttimer", IntTab(5), maptab, 1, true);
-
-caba::VciFdtRom<vci_param> vcifdtrom("vci_fdt_rom", IntTab(6), maptab);
-caba::VciMultiTty<vci_param> TTY0("TTY0", IntTab(7), maptab, "vci_multi_tty0", NULL);
-caba::VciLocks<vci_param> vcilocks("vcilocks", IntTab(11), maptab);
-soclib::caba::VciRam<vci_param>Memory0("Memory0", IntTab(2), maptab);
-caba::VciFdAccess<vci_param> vcifd("vcifd", maptab, IntTab(cpus.size()+1), IntTab(8));
-caba::VciEthernet<vci_param> vcieth("vcieth", maptab, IntTab(cpus.size()+2), IntTab(9), "soclib0");
-caba::VciBlockDevice<vci_param> vcibd("vcibd", maptab, IntTab(cpus.size()), IntTab(10),"block0.iso", 2048);
-soclib::caba::VciVgsb<vci_param> vgsb("Bus0" , maptab,5,12);
-
-soclib::caba::VciMwmrStats<vci_param> mwmr_stats0("mwmr_stats0",maptab, data_ldr, "mwmr0.log",stringArray("TCPIP_receiveTCP__Application_receiveTCP","TCPPacketManager_storePacket__TCPPacketManager_retrieve","TCPIP_timeoutPacket__TCPPacketManager_timeoutPacket","TCPIP_emptyListOfPackets__TCPPacketManager_empty","TCPIP_addPacket__TCPPacketManager_addPacket","TCPIP_ackPacket__TCPPacketManager_ackPacket","Application_open__TCPIP_open","Application_close__TCPIP_close","Application_abort__TCPIP_abort","Application_sendTCP__TCPIP_send_TCP","SmartCardController_fromTtoP__TCPIP_fromTtoP","SmartCardController_fromPtoT__TCPIP_fromPtoT","SmartCardController_start_TCPIP__TCPIP_start","SmartCardController_reset__InterfaceDevice_reset","SmartCardController_pTS__InterfaceDevice_pTS","SmartCardController_dataReady__InterfaceDevice_data_Ready","SmartCardController_activation__InterfaceDevice_activation","SmartCardController_fromDtoSC__InterfaceDevice_fromDtoSC","SmartCardController_answerToReset__InterfaceDevice_answerToReset","SmartCardController_pTSCConfirm__InterfaceDevice_pTSConfirm","SmartCardController_fromSCtoD__InterfaceDevice_fromSCtoD","SmartCardController_data_Ready_SC__InterfaceDevice_dataReady","SmartCardController_start_Application__Application_startApplication","TCPIP_set__mainTimer__Timer__mainTimer__TCPIP_set","TCPIP_reset__mainTimer__Timer__mainTimer__TCPIP_reset","TCPIP_expire__mainTimer__Timer__mainTimer__TCPIP_expire","TCPPacketManager_set__timerP__Timer__timerP__TCPPacketManager_set","TCPPacketManager_reset__timerP__Timer__timerP__TCPPacketManager_reset","TCPPacketManager_expire__timerP__Timer__timerP__TCPPacketManager_expire",NULL));
-
-
-
-//-------------------------------signaux------------------------------------
-
-caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];
-caba::VciSignals<vci_param> signal_vci_xicu("signal_vci_xicu");
-caba::VciSignals<vci_param> signal_vci_vcifdtrom("signal_vci_vcifdtrom");
- caba::VciSignals<vci_param> signal_vci_vcihetrom("signal_vci_vcihetrom");
- caba::VciSignals<vci_param> signal_vci_vcirom("signal_vci_vcirom");
- caba::VciSignals<vci_param> signal_vci_vcisimhelper("signal_vci_vcisimhelper");
-caba::VciSignals<vci_param> signal_vci_vcirttimer("signal_vci_vcirttimer");
-caba::VciSignals<vci_param> signal_vci_vcilocks("signal_vci_vcilocks");
-caba::VciSignals<vci_param> signal_vci_vcifdaccessi;
-caba::VciSignals<vci_param> signal_vci_vcifdaccesst;
-caba::VciSignals<vci_param> signal_vci_bdi;
-caba::VciSignals<vci_param> signal_vci_bdt;
-caba::VciSignals<vci_param> signal_vci_etherneti;
-caba::VciSignals<vci_param> signal_vci_ethernett;
-
-sc_clock signal_clk("signal_clk");
-sc_signal<bool> signal_resetn("signal_resetn");
-
- sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];
-
-soclib::caba::VciSignals<vci_param> signal_vci_vciram0("signal_vci_vciram0");
-
-soclib::caba::VciSignals<vci_param> signal_vci_tty0("signal_vci_tty0");
-
-
-
-//------------------------------Netlist---------------------------------
-
-// icu
-
- vcifdtrom.add_property("interrupt-parent", vcifdtrom.get_device_phandle("vci_xicu"));
-
- vcixicu.p_clk(signal_clk);
- vcixicu.p_resetn(signal_resetn);
-
- vcixicu.p_vci(signal_vci_xicu);
-
- vcifdtrom.begin_device_node("vci_rttimer", "soclib:vci_rttimer");
- vcifdtrom.add_property("interrupts", 4);
- vcifdtrom.add_property("frequency", 1000000);
- vcifdtrom.end_node();
-
- vcifdtrom.begin_device_node("vci_xicu", "soclib:vci_xicu");
-
- int irq_map[cpus.size() * 3];
- for ( size_t i = 0; i < cpus.size(); ++i )
- {
- irq_map[i*3 + 0] = i;
- irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);
- irq_map[i*3 + 2] = 0;
- }
-
- vcifdtrom.add_property("interrupt-map", irq_map, cpus.size() * 3);
- vcifdtrom.add_property("frequency", 1000000);
-
- vcifdtrom.add_property("param-int-pti-count", 1);
- vcifdtrom.add_property("param-int-hwi-count", xicu_n_irq);
- vcifdtrom.add_property("param-int-wti-count", cpus.size());
- vcifdtrom.add_property("param-int-irq-count", cpus.size());
- vcifdtrom.end_node();
-
- for ( size_t i = 0; i < xicu_n_irq; ++i )
- vcixicu.p_hwi[i](signal_xicu_irq[i]);
-
-///////////////// cpus
-
-vcifdtrom.begin_cpus();
-
-for ( size_t i = 0; i < cpus.size(); ++i ){
- // configure het_rom
- vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));
- // add cpu node to device tree
- vcifdtrom.begin_cpu_node(std::string("cpu:") + cpus[i]->type, i);
- vcifdtrom.add_property("freq", 1000000);
- vcifdtrom.end_node();
-
-// connect cpu
- cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);
-vgsb.p_to_initiator[i](signal_vci_m[i]);
-vcixicu.p_irq[i](cpus[i]->irq_sig[0]);
- }
- vcifdtrom.end_node();
-
- vcihetrom.p_clk(signal_clk);
- vcifdtrom.p_clk(signal_clk);
- vcirom.p_clk(signal_clk);
- vcisimhelper.p_clk(signal_clk);
- vcirttimer.p_clk(signal_clk);
- vcihetrom.p_resetn(signal_resetn);
- vcifdtrom.p_resetn(signal_resetn);
- vcirom.p_resetn(signal_resetn);
- vcisimhelper.p_resetn(signal_resetn);
- vcirttimer.p_resetn(signal_resetn);
- vcihetrom.p_vci(signal_vci_vcihetrom);
- vcifdtrom.p_vci(signal_vci_vcifdtrom);
- vcirom.p_vci(signal_vci_vcirom);
- vcisimhelper.p_vci(signal_vci_vcisimhelper);
- vcirttimer.p_vci(signal_vci_vcirttimer);
- vcirttimer.p_irq[0](signal_xicu_irq[4]);
-
- vgsb.p_clk(signal_clk);
- vgsb.p_resetn(signal_resetn);
- vgsb.p_to_target[0](signal_vci_vcihetrom);
- vgsb.p_to_target[1](signal_vci_vcirom);
- vgsb.p_to_target[3](signal_vci_vcisimhelper);
-
- vgsb.p_to_target[4](signal_vci_xicu);
- vgsb.p_to_target[5](signal_vci_vcirttimer);
-
- vgsb.p_to_target[6](signal_vci_vcifdtrom);
-
- vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);
- vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);
- vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);
-
-// RAM netlist
-
-Memory0.p_clk(signal_clk);
-Memory0.p_resetn(signal_resetn);
-Memory0.p_vci(signal_vci_vciram0);
-
-vgsb.p_to_target[2](signal_vci_vciram0);
-
-vgsb.p_to_target[8](signal_vci_vcifdaccesst);
-vgsb.p_to_target[9](signal_vci_ethernett);
-vgsb.p_to_target[10](signal_vci_bdt);
-vcifdtrom.add_property("interrupts", 0);
-
-vcifdtrom.end_node();;
-
-// TTY netlist
-
-TTY0.p_clk(signal_clk);
-TTY0.p_resetn(signal_resetn);
-TTY0.p_vci(signal_vci_tty0);
-
-vcifdtrom.begin_device_node("vci_multi_tty0","soclib:vci_multi_tty0");
-
-vgsb.p_to_target[7](signal_vci_tty0);
-
-TTY0.p_irq[0](signal_xicu_irq[0]);
-
-{
-
- vcifdtrom.begin_node("aliases");
- vcifdtrom.add_property("timer", vcifdtrom.get_device_name("vci_rttimer") + "[0]");
- vcifdtrom.add_property("console", vcifdtrom.get_device_name("vci_multi_tty0") + "[0]");
- vcifdtrom.end_node();
-}
-
-vcieth.p_clk(signal_clk);
-vcieth.p_resetn(signal_resetn);
-vcieth.p_irq(signal_xicu_irq[3]);
-vcieth.p_vci_target(signal_vci_ethernett);
-vcieth.p_vci_initiator(signal_vci_etherneti);
-vcifdtrom.begin_device_node("vci_ethernet", "soclib:vci_ethernet");
-vcifdtrom.add_property("interrupts", 3);
-vcifdtrom.end_node();
-vcibd.p_clk(signal_clk);
-vcibd.p_resetn(signal_resetn);
-vcibd.p_irq(signal_xicu_irq[1]);
-vcibd.p_vci_target(signal_vci_bdt);
-vcibd.p_vci_initiator(signal_vci_bdi);
-vcifdtrom.begin_device_node("vci_block_device", "soclib:vci_block_device");
-vcifdtrom.add_property("interrupts", 1);
-vcifdtrom.end_node();
-vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));
-vcifd.p_clk(signal_clk);
-vcifd.p_resetn(signal_resetn);
-vcifd.p_irq(signal_xicu_irq[2]);
-vcifd.p_vci_target(signal_vci_vcifdaccesst);
-vcifd.p_vci_initiator(signal_vci_vcifdaccessi);
-vcifdtrom.begin_device_node("vci_fd_access", "soclib:vci_fd_access");
-vcifdtrom.add_property("interrupts", 2);
-vcifdtrom.end_node();
-
-mwmr_stats0.p_clk(signal_clk);
-mwmr_stats0.p_resetn(signal_resetn);
-mwmr_stats0.p_vci(signal_vci_vciram0);
-
- sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));
- signal_resetn = false;
- sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));
- signal_resetn = true;
- sc_core::sc_start();
-
- return EXIT_SUCCESS;
-}
-
-
-
-
-/***************************************************************************
-----------------------------simulation-------------------------
-***************************************************************************/
-
-int sc_main (int argc, char *argv[])
-{
- try {
- return _main(argc, argv);
- }
-
- catch (std::exception &e) {
- std::cout << e.what() << std::endl;
- throw;
- } catch (...) {
-std::cout << "Unknown exception occured" << std::endl;
-throw;
-}
-
- return 1;
-}
\ No newline at end of file
diff --git a/MPSoC/soclib/utils/lib/python/sd_parser/__init__.pyc b/MPSoC/soclib/utils/lib/python/sd_parser/__init__.pyc
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diff --git a/MPSoC/soclib/utils/lib/python/sd_parser/component_builder.pyc b/MPSoC/soclib/utils/lib/python/sd_parser/component_builder.pyc
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/__init__.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/__init__.pyc
deleted file mode 100644
index 3c5bd76e437c198c1bceb37d61777cb0a420cc69..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/action.py b/MPSoC/soclib/utils/lib/python/soclib_builder/action.py
deleted file mode 100644
index e669eaf915..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/action.py
+++ /dev/null
@@ -1,291 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-
-import os
-import os.path
-import time
-import sys
-import select
-import tempfile
-import operator
-try:
- from functools import reduce
-except:
- pass
-
-from soclib_cc.config import config
-import command
-
-__author__ = 'Nicolas Pouillon, <nipo@ssji.net>'
-__copyright__ = 'UPMC, Lip6, SoC, 2007-2010'
-__license__ = 'GPL-v2'
-__id__ = "$Id: action.py 1750 2010-05-26 09:49:35Z nipo $"
-__version__ = "$Revision: 1750 $"
-
-__all__ = ['Action', 'ActionFailed', 'NotFound', 'Noop']
-
-class NotFound(Exception):
- pass
-
-class ActionFailed(Exception):
- def __init__(self, rval, action):
- Exception.__init__(self, "%s failed: %s"%(action, rval))
- self.rval = rval
- self.action = action
-
-def get_times(files, default, cmp_func, ignore_absent):
- most_time = default
- for f in files:
- if f.exists():
- most_time = cmp_func((f.last_mod, most_time))
- else:
- if ignore_absent:
- continue
- else:
- raise NotFound, f
- return most_time
-
-def merge_hash(objs):
- return hash(reduce(
- lambda x,y:(x + (y<<1)),
- map(hash, objs),
- 0))
-
-get_newest = lambda files, ignore_absent: get_times(files, 0, max, ignore_absent)
-get_oldest = lambda files, ignore_absent: get_times(files, time.time(), min, ignore_absent)
-
-def check_exist(files):
- return reduce(operator.and_, map(lambda x:x.exists(), files), True)
-
-class Action:
- priority = 0
- info_code = ' '
-
- WORKING = 'Work'
- TODO = 'Todo'
- DONE = 'Done'
- FAILED = 'Failed'
- BLOCKED = 'Blocked'
-
- def __init__(self, dests, sources, **options):
- from bblock import bblockize, BBlock, AnonymousBBlock
- if not dests:
- self.dests = [AnonymousBBlock(self)]
- else:
- self.dests = bblockize(dests, self)
- self.sources = bblockize(sources)
- self.options = options
-
- self.__hash = merge_hash(self.dests+self.sources)
-
- self.__state = self.TODO
- self.__depends = []
- self.__commands = []
-
- map(lambda x:x.addUser(self), self.sources)
-
- def prepare(self):
- import fileops
- for outdir in self.dests:
- d = os.path.dirname(str(self.dests[0]))
- if d:
- self.add_depends(*fileops.CreateDir(d).dests)
-
- self.__state = [self.TODO, self.DONE][self.is_valid()]
-
- self.prepare = lambda :None
-
- def is_valid(self):
- try:
- newest_dep = 0
- oldest_dest = time.time()
- for d in self.__depends + self.sources:
- if d.is_dir():
- continue
- if not d.exists():
- return False
- newest_dep = max((newest_dep, d.mtime()))
- for d in self.dests:
- if not d.exists():
- return False
- oldest_dest = min((oldest_dest, d.mtime()))
-
- return oldest_dest >= newest_dep
- except NotFound:
- return False
-
- # Called by children to add things
-
- def add_depends(self, *deps):
- map(lambda x:x.addUser(self), deps)
-
- self.__depends += list(deps)
-
- def run_command(self, cmd, cwd = None):
- if isinstance(cmd, (str, unicode)):
- raise ValueError("cmd must be a list of string")
-
- cmd = command.Command(cmd,
- cwd = cwd,
- on_done = self.__set_done)
- self.__commands.append(cmd)
-
- def create_file(self, f_bblock, contents):
- cmd = command.CreateFile(str(f_bblock), contents,
- on_done = self.__set_done)
- self.__commands.append(cmd)
-
- # Called by children to process synchronously
-
- def process(self):
- self.prepare()
-
- if config.debug:
- print 'Synchronously processing', self,
- if self.__state == self.DONE:
- if config.debug:
- print 'already done'
- return
-
- for d in list(self.__depends) + list(self.sources):
- if d.generator.__state != self.DONE:
- d.generator.process()
-
- if config.debug:
- print 'launching...', self.__commands
- self.todo_launch(True)
-
- # Private subprocess handling
-
- def stdout_reformat(self, msg):
- '''
- Reformat stdout, to make error messages of specific tools
- compatible with what is parsed by usual compilation tools.
- '''
- return msg
-
- def stderr_reformat(self, msg):
- '''
- Reformat stderr, to make error messages of specific tools
- compatible with what is parsed by usual compilation tools.
- '''
- return msg
-
- def __set_done(self, cmd, returncode, out, err):
-
- if out:
- out = self.stdout_reformat(out)
- sys.stdout.write('\n')
- sys.stdout.write(out)
-
- if err:
- err = self.stderr_reformat(err)
- sys.stderr.write('\n')
- sys.stderr.write(err)
-
- if returncode:
- self.__state = self.FAILED
- if returncode == -2: # sigint
- raise KeyboardInterrupt()
- raise ActionFailed(returncode, cmd.command)
-
- for d in self.dests:
- d.touch()
-
- self.__next()
-
- def __next(self):
- if len(self.__commands) == self.__cpt:
- self.__state = self.DONE
- return
- cmd = self.__commands[self.__cpt]
- self.__cpt += 1
-
- cmd.run(self.__sync)
-
- # Todo API
-
- def todo_launch(self, synchronous = False):
- self.__cpt = 0
- self.__state = self.WORKING
- self.__sync = synchronous
- self.__next()
-
- def todo_state(self):
- return self.__state
-
- def todo_can_be_processed(self):
- if not check_exist(self.sources):
- self.__state = self.BLOCKED
- return False
- for d in list(self.__depends) + list(self.sources):
- if d.generator.__state != self.DONE:
- self.__state = self.BLOCKED
- return False
- self.__state = self.TODO
- return True
-
- def why_blocked(self):
- print self, 'blocked because'
- if not check_exist(self.sources):
- print "not all sources"
- for d in list(self.__depends) + list(self.sources):
- if d.generator.__state != self.DONE:
- print d.generator, "not ready:", d.generator.__state
-
- def todo_get_depends(self):
- return list(self.__depends) + list(self.sources)
-
- def todo_clean(self):
- for i in self.dests:
- i.delete()
-
- def source_changed(self):
- self.todo_can_be_processed()
-
- # Helpers
-
- def __hash__(self):
- return self.__hash
-
- def __eq__(self, other):
- return self.__class__ is other.__class__ and \
- set(self.sources) == set(other.sources) and \
- set(self.dests) == set(other.dests)
-
- def __str__(self):
- import bblock
- l = lambda x:map(repr, x)
- return "<%s: %s -> %s + %s>"%(
- self.__class__.__name__,
- l(self.sources),
- l(self.dests),
- l(self.__depends),
- )
-
-
-class Noop(Action):
-
- def __init__(self):
- Action.__init__(self, [], [])
-
- def is_valid(self):
- return True
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/action.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/action.pyc
deleted file mode 100644
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GIT binary patch
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/bblock.py b/MPSoC/soclib/utils/lib/python/soclib_builder/bblock.py
deleted file mode 100644
index 51053207ce..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/bblock.py
+++ /dev/null
@@ -1,208 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-#
-# Copyright (c) UPMC, Lip6, SoC
-# Nicolas Pouillon <nipo@ssji.net>, 2007
-#
-# Maintainers: group:toolmakers
-
-import os, os.path
-import time
-
-from soclib_cc.config import config
-
-__id__ = "$Id: bblock.py 1750 2010-05-26 09:49:35Z nipo $"
-__version__ = "$Revision: 1750 $"
-
-_global_bblock_registry = {}
-
-class BBlock:
- def __init__(self, filename, generator = None):
- self.is_blob = False
- assert filename
- if generator is None:
- from action import Noop
- generator = Noop()
- self.__filename = filename
- assert filename not in _global_bblock_registry
- _global_bblock_registry[filename] = self
-
- self.generator = generator
- self.__i_need = None
- self.__needed_by = None
- self.__prepared = False
- self.__users = set()
-
- self.__rehash()
-
- @property
- def users(self):
- return self.__users
-
- def addUser(self, gen):
-# print 'addUser', repr(self), str(gen)[:40] + '...'
- self.__users.add(gen)
-
- def touch(self):
- mt = self.__mtime
- e = self.__exists
- self.__rehash()
- if mt != self.__mtime or e != self.__exists:
- for u in self.__users:
- u.source_changed()
-
- def is_dir(self):
- return os.path.isdir(self.__filename)
-
- def setIsBlob(self, val = True):
- self.is_blob = val
-
- def __rehash(self):
- if os.path.exists(self.__filename):
- self.__exists = True
- self.__mtime = os.stat(self.__filename).st_mtime
- else:
- self.__exists = False
- self.__mtime = time.time() + 4096
-
- def mtime(self):
- return self.__mtime
-
- def delete(self):
- if os.path.isfile(self.__filename):
- try:
- os.unlink(self.__filename)
- except OSError:
- pass
- self.__rehash()
-
- def generate(self):
- self.generator.process()
-
- def exists(self):
- return self.__exists
-
- def __str__(self):
- return self.__filename
-
- def __repr__(self):
- return '{%s}' % os.path.basename(self.__filename)
-
- def __hash__(self):
- return hash(self.__filename)
-
- def __eq__(self, other):
- return self.__filename == other.__filename
-
- def __walk_i_need(self):
- if self.__i_need is not None:
- return self.__i_need
-
- self.__i_need = set()
- for d in self.generator.todo_get_depends():
- if d in self.__i_need:
- continue
- self.__i_need.add(d)
- self.__i_need |= d.__walk_i_need()
- return self.__i_need
-
- def __walk_needed_by(self):
- if self.__needed_by is not None:
- return self.__needed_by
-
- self.__needed_by = set()
- for u in self.__users:
- for d in u.dests:
- if d is self.__needed_by:
- continue
- self.__needed_by.add(d)
- self.__needed_by |= d.__walk_needed_by()
- return self.__needed_by
-
- def prepare(self):
- if self.__prepared:
- return
-
- self.__walk_needed_by()
- self.__walk_i_need()
-
- self.__prepared = True
-
- def needs(self, other):
- return (
- (other in self.__i_need or self in other.__needed_by) and not
- (self in other.__i_need or other in self.__needed_by)
- )
-
-class AnonymousBBlock(BBlock):
- def __init__(self, builder):
- self.__done = False
- BBlock.__init__(self, '__anon_'+hex(id(builder)), builder)
-
- def touch(self):
- self.__done = True
-
- def exists(self):
- return self.__done
-
- def delete(self):
- self.__done = False
-
- def prepare(self):
- BBlock.prepare(self)
- self.__done = False
-
- def __repr__(self):
- return '{anon %03d}' % (hash(str(self)) % 1000)
-
-def bblockize1(f, gen = None):
- if config.debug:
- print 'BBlockizing', f,
- if isinstance(f, BBlock):
- if config.debug:
- print 'already is'
- return f
- if f in _global_bblock_registry:
- r = _global_bblock_registry[f]
- if config.debug:
- print 'in global reg', r
- from action import Noop
- if gen is not None:
- if isinstance(r.generator, Noop):
- r.generator = gen
- elif r.generator.__class__ is not gen.__class__:
- raise ValueError('Generator in reg: %s, passed: %s'%(r.generator.__class__, gen.__class__))
- return r
- if config.debug:
- print 'needs BBlock'
- return BBlock(f, gen)
-
-def bblockize(files, gen = None):
- return map(lambda x:bblockize1(x, gen), files)
-
-def filenames(bblocks):
- ret = []
- for b in bblocks:
- assert isinstance(b, BBlock)
- if isinstance(b, AnonymousBBlock):
- continue
- ret.append(str(b))
- return ret
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/bblock.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/bblock.pyc
deleted file mode 100644
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GIT binary patch
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/command.py b/MPSoC/soclib/utils/lib/python/soclib_builder/command.py
deleted file mode 100644
index db631161c8..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/command.py
+++ /dev/null
@@ -1,190 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-
-import os
-import tempfile
-
-from soclib_cc.config import config
-
-__author__ = 'Nicolas Pouillon, <nipo@ssji.net>'
-__copyright__ = 'UPMC, Lip6, SoC, 2007-2010'
-__license__ = 'GPL-v2'
-__id__ = "$Id: command.py 1787 2010-06-07 21:50:25Z nipo $"
-__version__ = "$Revision: 1787 $"
-
-__all__ = ['Command']
-
-class Command:
-
- __jobs = {}
-
- def __init__(self, cmd, cwd = None, on_done = None):
- self.__cmd = cmd
- self.__cwd = cwd
- self.__on_done = on_done
- self.__done = False
- self.__stdout = ''
- self.__stderr = ''
-
- @property
- def stdout(self):
- return self.__stdout
-
- @property
- def stderr(self):
- return self.__stderr
-
- @property
- def command(self):
- return ' '.join(map('"%s"'.__mod__, self.__cmd))
-
- def run(self, synchronous = False):
- import subprocess
- #print "---- run", cmd
-
- if config.verbose:
- print 'Running', ["async", "sync"][synchronous], self.command
-
- self.__out = tempfile.TemporaryFile("w+b", bufsize=128)
- self.__err = tempfile.TemporaryFile("w+b", bufsize=128)
-
- try:
- self.__handle = subprocess.Popen(
- self.__cmd,
- shell = False,
- cwd = self.__cwd,
- bufsize = 128*1024,
- close_fds = True,
- stdin = None,
- stdout = self.__out,
- stderr = self.__err,
- )
- except OSError, e:
- from action import ActionFailed
- raise ActionFailed(-1, self.command)
-
- if synchronous:
- self.__handle.wait()
- self.__out.seek(0)
- self.__err.seek(0)
- self.__stdout = self.__out.read()
- self.__stderr = self.__err.read()
- ret = self.__handle.returncode
- del self.__handle
- del self.__out
- del self.__err
- return ret
-
- self.__class__.__jobs[self.__handle.pid] = self
-
- @classmethod
- def pending_action_count(cls):
- return len(cls.__jobs)
-
- @classmethod
- def wait(cls):
- try:
- (pid, st) = os.wait()
- killed = st & 0x80
- sig = st & 0x7f
- ret = st >> 8
- cls.__jobs[pid].__handle.returncode = killed and -sig or ret
- except Exception, e:
- pass
- for job in cls.__jobs.values()[:]:
- p = job.__handle.poll()
-# print "---- poll", job, p
- if job.__handle.returncode is not None:
- job.__set_done()
-
- def __set_done(self):
- try:
- self.__handle.communicate()
- except:
- pass
- self.__out.seek(0)
- self.__err.seek(0)
- self.__stdout = self.__out.read()
- self.__stderr = self.__err.read()
- del self.__out
- del self.__err
-
- #print '--'
- del self.__class__.__jobs[self.__handle.pid]
-
- rc = self.__handle.returncode
- del self.__handle
-
- if rc == 0:
- self.__done = True
-
- if self.__on_done:
- self.__on_done(self, rc, self.__stdout, self.__stderr)
-
- def is_background(self):
- try:
- return self.__handle.poll() is None
- except:
- return False
-
-class CreateFile:
- def __init__(self, filename, contents, on_done = None):
- self.__filename = filename
- self.__contents = contents
- self.__on_done = on_done
-
- def run(self, synchronous = False):
- if config.verbose:
- print 'Creating file', self.__filename
- if os.path.exists(self.__filename):
- fd = open(self.__filename, 'r+')
- old = fd.read()
- fd.seek(0)
- if old != self.__contents:
- fd.truncate()
- fd.write(self.__contents)
- else:
- fd = open(self.__filename, 'w')
- fd.write(self.__contents)
- fd.close()
-
- if self.__on_done:
- self.__on_done(self, 0, '', '')
-
- def is_background(self):
- return False
-
-class CreateDir:
- def __init__(self, filename, on_done = None):
- self.__filename = filename
- self.__on_done = on_done
-
- def run(self, synchronous = False):
- if config.verbose:
- print 'Creating directory', self.__filename
- if not os.path.exists(self.__filename):
- os.makedirs(self.__filename)
-
- if self.__on_done:
- self.__on_done(self, 0, '', '')
-
- def is_background(self):
- return False
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/command.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/command.pyc
deleted file mode 100644
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/depends.py b/MPSoC/soclib/utils/lib/python/soclib_builder/depends.py
deleted file mode 100644
index 44f5d51e5a..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/depends.py
+++ /dev/null
@@ -1,77 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-#
-# Copyright (c) UPMC, Lip6, SoC
-# Nicolas Pouillon <nipo@ssji.net>, 2007
-#
-# Maintainers: group:toolmakers
-
-import os, os.path, time
-import pickle
-
-from soclib_cc.config import config
-
-import bblock
-
-__id__ = "$Id: depends.py 2016 2011-01-21 10:45:27Z nipo $"
-__version__ = "$Revision: 2016 $"
-
-__all__ = ['load', 'dump']
-
-class MustRehash(Exception):
- pass
-
-class DepPickler(pickle.Pickler):
- def __init__(self, filename):
- fd = open(filename, 'w')
- pickle.Pickler.__init__(self, fd, pickle.HIGHEST_PROTOCOL)
- def persistent_id(self, obj):
- if isinstance(obj, bblock.BBlock):
- return 'BBlock:'+str(obj)
-
-def dump(name, deps):
- p = DepPickler(config.reposFile(name))
- p.dump(deps)
-
-class DepUnpickler(pickle.Unpickler):
- def __init__(self, filename):
- try:
- fd = open(filename, 'r')
-# print 'loading back depends %s'%filename
- except IOError:
-# print '%s not loadable'%filename
- raise MustRehash()
- pickle.Unpickler.__init__(self, fd)
- self.last_mod = os.stat(filename).st_mtime
- def persistent_load(self, ident):
- mode,ide = ident.split(':',1)
- if mode == 'BBlock':
- r = bblock.bblockize1(ide)
- if r.exists() and r.mtime() > self.last_mod:
- raise MustRehash()
- return r
-
-def load(name):
- p = DepUnpickler(config.reposFile(name))
- try:
- return p.load()
- except:
- raise MustRehash
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/depends.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/depends.pyc
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/fileops.py b/MPSoC/soclib/utils/lib/python/soclib_builder/fileops.py
deleted file mode 100644
index d959738c29..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/fileops.py
+++ /dev/null
@@ -1,46 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-#
-# Copyright (c) UPMC, Lip6, SoC
-# Nicolas Pouillon <nipo@ssji.net>, 2007
-#
-# Maintainers: group:toolmakers
-
-import os
-import os.path
-import action
-
-__id__ = "$Id: fileops.py 1750 2010-05-26 09:49:35Z nipo $"
-__version__ = "$Revision: 1750 $"
-
-class CreateDir(action.Action):
- info_code = 'D'
-
- def __init__(self, directory):
- action.Action.__init__(self, [directory], [])
-
- def is_valid(self):
- return os.path.isdir(str(self.dests[0]))
-
- def prepare(self):
- for b in self.dests:
- self.run_command(['mkdir', '-p', str(b)])
- action.Action.prepare(self)
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/fileops.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/fileops.pyc
deleted file mode 100644
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.py b/MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.py
deleted file mode 100644
index 3b5def51dd..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.py
+++ /dev/null
@@ -1,60 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-#
-# Copyright (c) UPMC, Lip6, SoC
-# Nicolas Pouillon <nipo@ssji.net>, 2007
-#
-# Maintainers: group:toolmakers
-
-__all__ = ["MfRule"]
-
-__id__ = "$Id: mfparser.py 1750 2010-05-26 09:49:35Z nipo $"
-__version__ = "$Revision: 1750 $"
-
-def bsfilter(spacer, l):
- r = []
- next_follows = False
- for i in l:
- nf = next_follows
- if i.endswith('\\'):
- next_follows = True
- i = i[:-1]+spacer
- else:
- next_follows = False
- if nf:
- r[-1] += i
- else:
- r.append(i)
- return r
-
-class MfRule:
- def __init__(self, text):
- lines = filter(lambda x:not x.startswith('#'),
- bsfilter("", text.split('\n')))
- try:
- dest, prereq = lines[0].split(":",1)
- except ValueError:
- print lines[0]
- raise
- self.rules = lines[1:]
- self.dest = bsfilter(" ", dest.strip().split())
- self.prerequisites = bsfilter(" ", filter(None, map(
- lambda x:x.strip(), prereq.split())))
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/mfparser.pyc
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/textfile.py b/MPSoC/soclib/utils/lib/python/soclib_builder/textfile.py
deleted file mode 100644
index a2ad7d3431..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/textfile.py
+++ /dev/null
@@ -1,55 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-#
-# Copyright (c) UPMC, Lip6, SoC
-# Nicolas Pouillon <nipo@ssji.net>, 2007
-#
-# Maintainers: group:toolmakers
-
-import os, os.path
-
-from soclib_cc.config import config
-
-from fileops import CreateDir
-from action import Action
-
-__id__ = "$Id: textfile.py 1750 2010-05-26 09:49:35Z nipo $"
-__version__ = "$Revision: 1750 $"
-
-class Textfile(Action):
- info_code = 'S'
- priority = 50
-
- def __init__(self, output, contents):
- Action.__init__(self, [output], [], contents = contents)
-
- def is_valid(self):
- f = str(self.dests[0])
- if os.path.exists(f):
- return open(f, 'r').read() == self.options['contents']
- return False
-
- def prepare(self):
- self.create_file(self.dests[0], self.options['contents'])
- Action.prepare(self)
-
-class CxxSource(Textfile):
- pass
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/textfile.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/textfile.pyc
deleted file mode 100644
index d7eb13b550a5f431c8082a4b7b30401c9419e752..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/todo.py b/MPSoC/soclib/utils/lib/python/soclib_builder/todo.py
deleted file mode 100644
index 9989230b69..0000000000
--- a/MPSoC/soclib/utils/lib/python/soclib_builder/todo.py
+++ /dev/null
@@ -1,319 +0,0 @@
-
-# SOCLIB_GPL_HEADER_BEGIN
-#
-# This file is part of SoCLib, GNU GPLv2.
-#
-# SoCLib is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# SoCLib is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-# General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with SoCLib; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
-# 02110-1301, USA.
-#
-# SOCLIB_GPL_HEADER_END
-
-__author__ = 'Nicolas Pouillon, <nipo@ssji.net>'
-__copyright__ = 'UPMC, Lip6, SoC, 2007-2010'
-__license__ = 'GPL-v2'
-__id__ = "$Id: todo.py 1864 2010-08-31 14:45:01Z nipo $"
-__version__ = "$Revision: 1864 $"
-
-import sys
-import os, os.path
-
-from soclib_cc.config import config
-from bblock import bblockize, BBlock, filenames
-from action import Noop, ActionFailed, Action
-import command
-from soclib_utils.terminal import terminal_width
-
-__all__ = ['Todo']
-
-class ToDo:
- def __init__(self, *dests):
- self.has_blob = False
- self.dests = []
- self.add(*dests)
- self.prepared = False
- d = config.reposFile('')
- if not os.path.isdir(d):
- os.makedirs(d)
- self.max_actions = config.toolchain.max_processes
- self.__term_width = terminal_width()
- self.__todo = []
-
- def add(self, *dests):
- self.dests += bblockize(dests)
- for d in self.dests:
- self.has_blob |= d.is_blob
-
- def _getall_bbs(self, dests):
- dest_bb_list = set(dests)
- viewed_bb_list = set()
- todo_generator_list = set()
-
- while dest_bb_list:
- bb = dest_bb_list.pop()
- viewed_bb_list.add(bb)
-
- gen = bb.generator
- gen.prepare()
- dest_bb_list |= set(gen.todo_get_depends())
- todo_generator_list.add(gen)
-# print gen
-
- dest_bb_list -= viewed_bb_list
-
-
- def cr(x):
- return not isinstance(x, Noop)
- todo_generator_list = filter(cr, todo_generator_list)
- return todo_generator_list, viewed_bb_list
-
- def prepare(self):
- if self.prepared:
- return
-
- try:
- todo, bblocks = self._getall_bbs(self.dests)
- except ActionFailed, e:
- return self.handle_failed_action(e)
-
- for b in bblocks:
- b.generator.prepare()
-
- for b in bblocks:
- b.prepare()
-
- sorted_bblocks = []
- for b in bblocks:
- done = False
- for i, bb in reversed(list(enumerate(sorted_bblocks))):
- if b.needs(bb):
- sorted_bblocks.insert(i+1, b)
- done = True
- break
- if not done:
- sorted_bblocks.insert(0, b)
- bblocks = sorted_bblocks
-
- self.__todo = []
- viewed = set()
- for b in bblocks:
- g = b.generator
- if isinstance(g, Noop) or g in viewed:
- continue
- self.__todo.append(g)
- viewed.add(g)
-
- if set(self.__todo) < set(todo):
- print 'Lost generators in battle:'
- for i in set(todo) - set(self.__todo):
- for d in i.dests:
- print d in self.dests, d.generator.__class__, d
- raise RuntimeError()
-
-# self.__todo.reverse()
- self.prepared = True
-
-# for i, g in enumerate(self.todo):
-# print i, filenames(g.dests), filenames(g.sources)
-
- def clean(self):
- self.prepare()
- for i in self.__todo:
- i.todo_clean()
-
- def handle_failed_action(self, e):
- print "soclib-cc: *** Action failed with return value `%s'. Stop."%e.rval
- if self.has_blob:
- print '***********************************************'
- print '***********************************************'
- print '**** WARNING, YOU USED BINARY-ONLY MODULES ****'
- print '***********************************************'
- print '***********************************************'
- print 'If you compilation failed because of linkage, this is most'
- print 'likely a mismatch between expected libraries from a binary'
- print 'only module and your system libraries (libstdc++, SystemC, ...)'
- print
- print "\x1b[91mPlease don't report any error about binary modules"
- print "to SoCLib-CC maintainers, they'll ignore your requests.\x1b[m"
- print
- if config.verbose:
- print "soclib-cc: Failed action: `%s'"%e.action
- else:
- import shlex
- act = []
- was = None
- cmdlist = e.action
- if not isinstance(cmdlist, (list, tuple)):
- cmdlist = shlex.split(cmdlist)
- for a in cmdlist:
- s = None
- if a.startswith('-I'):
- s = '-I'
- if was != s and s:
- act.append(s+'...')
- elif not s:
- act.append(a)
- was = s
- print "soclib-cc: Failed action: `%s'" % ' '.join(act)
- print "soclib-cc: Command line shortened, rerun with -v for complete command line"
- if command.Command.pending_action_count():
- print "soclib-cc: Waiting for unfinished jobs"
- self.__wait_done()
- raise
-
- def wait(self):
- command.Command.wait()
-
- def __wait_done(self):
- while command.Command.pending_action_count():
- self.progressBar()
- command.Command.wait()
-
- def process(self):
- import sys
- self.prepare()
-
- if config.debug:
- print 'Would do:'
- print "="*80
- print "="*80
- for i, g in enumerate(self.__todo):
- print i, g.is_valid(), str(g)
- print "="*80
- print "="*80
-
-# self.infoBar()
- self.progressBar()
-
- while self.__build_as_much_as_possible() == False:
- self.progressBar()
- self.progressBar()
- if config.progress_bar:
- print
-
- def __build_as_much_as_possible(self):
- wont = filter(lambda x:x.todo_state() in [Action.FAILED, Action.WORKING],
- self.__todo)
- left = filter(lambda x:x.todo_state() in [Action.TODO, Action.BLOCKED],
- self.__todo)
- if not left:
- return True
- possible = filter(lambda x:x.todo_can_be_processed(),
- left)
- if left and not possible and not wont:
- print 'Left:'
- for i in left:
- i.why_blocked()
- raise RuntimeError()
-
- try:
- self.__run(possible)
- except ActionFailed, e:
- return self.handle_failed_action(e)
- except OSError, e:
- if hasattr(e, 'child_traceback'):
- print e.child_traceback
- raise
- return False
-
- def __run(self, left):
- # pop() takes from the end...
- left.reverse()
-
-# print 'run'
-
- while left:
- todo = left.pop()
- if todo.todo_state() != Action.TODO:
- continue
-
- while command.Command.pending_action_count() >= self.max_actions:
- self.wait()
-
- if not todo.todo_can_be_processed():
- continue
-
- todo.todo_launch()
- self.progressBar()
- self.__wait_done()
-
- @staticmethod
- def __progress_bar_code(state):
- return {
- Action.TODO: ' ',
- Action.BLOCKED: '.',
- Action.DONE: '=',
- Action.WORKING: 'W',
- Action.FAILED: '!',
- }[state]
-
- def progressBar(self):
- if not config.progress_bar or not self.prepared:
- return
- if self.__term_width < len(self.__todo) + 12:
- self.__short_progress()
- else:
- self.__long_progress()
-
- def __long_progress(self):
- pb = ""
- left = 0
- for pi in self.__todo:
- s = pi.todo_state()
- if s == Action.TODO:
- left += 1
- pb += self.__progress_bar_code(s)
- sys.stdout.write('\r['+pb+']')
- sys.stdout.write(' %d left ' % left)
- sys.stdout.flush()
-
- def __short_progress(self):
- states = {
- Action.TODO : 'Todo',
- Action.BLOCKED : 'Blocked',
- Action.DONE : 'Done',
- Action.WORKING : 'Working',
- Action.FAILED : 'Failed',
- }
- counts = dict([(k, 0) for k in states.keys()])
- for i in self.__todo:
- counts[i.todo_state()] += 1
- pc = 100. * counts[Action.DONE] / len(self.__todo)
- sys.stdout.write('\r % 3d%% done' % int(pc))
- for k in sorted(states.keys()):
- sys.stdout.write(', %3d %s' % (counts[k], states[k]))
- sys.stdout.write(' \r')
- sys.stdout.flush()
-
- def infoBar(self):
- if not config.progress_bar:
- return
- pb = ""
- for pi in self.__todo:
- pb += pi.info_code
- sys.stdout.write('['+pb+']\n')
- sys.stdout.flush()
-
- def format(self, formatter_class_name, output):
- self.prepare()
-
- nodes = formatter_class_name.split('.')
- module = '.'.join(nodes[:-1])
- tmp = __import__(module, globals(), locals(), [nodes[-1]])
- formatter = getattr(tmp, nodes[-1])
-
- f = formatter(output)
- for a in self.__todo:
- f.format_action(a)
-
-
diff --git a/MPSoC/soclib/utils/lib/python/soclib_builder/todo.pyc b/MPSoC/soclib/utils/lib/python/soclib_builder/todo.pyc
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GIT binary patch
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diff --git a/MPSoC/soclib/utils/lib/python/soclib_utils/terminal.pyc b/MPSoC/soclib/utils/lib/python/soclib_utils/terminal.pyc
deleted file mode 100644
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GIT binary patch
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HcmV?d00001
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diff --git a/modeling/LIP6/monoprocessor.xml b/modeling/LIP6/monoprocessor.xml
index f9d7a3a941..cc9cca4dee 100644
--- a/modeling/LIP6/monoprocessor.xml
+++ b/modeling/LIP6/monoprocessor.xml
@@ -7,7 +7,7 @@
<MainCode value="void __user_init() {"/>
<MainCode value="}"/>
<Optimized value="true" />
-<Validated value="Block0;" />
+<Validated value="" />
<Ignored value="" />
<COMPONENT type="5000" id="25" >
@@ -63,6 +63,7 @@
<cdparam x="458" y="139" />
<sizeparam width="10" height="15" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="1400" minY="10" maxY="900" />
<infoparam name="List of all parameters of an Avatar SMD transition" value="" />
<TGConnectingPoint num="0" id="26" />
@@ -70,12 +71,12 @@
<TGConnectingPoint num="2" id="28" />
<TGConnectingPoint num="3" id="29" />
<extraparam>
-<guard value="[ ]" />
-<afterMin value="" />
-<afterMax value="" />
-<computeMin value="" />
-<computeMax value="" />
-<probability value="" />
+<guard value="[ ]" enabled="true"/>
+<afterMin value="" enabled="true"/>
+<afterMax value="" enabled="true"/>
+<computeMin value="" enabled="true"/>
+<computeMax value="" enabled="true"/>
+<probability value="" enabled="true"/>
</extraparam>
</SUBCOMPONENT>
@@ -92,6 +93,7 @@
<cdparam x="407" y="110" />
<sizeparam width="10" height="15" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="1400" minY="10" maxY="900" />
<infoparam name="List of all parameters of an Avatar SMD transition" value="" />
<TGConnectingPoint num="0" id="33" />
@@ -99,12 +101,12 @@
<TGConnectingPoint num="2" id="35" />
<TGConnectingPoint num="3" id="36" />
<extraparam>
-<guard value="[ ]" />
-<afterMin value="" />
-<afterMax value="" />
-<computeMin value="" />
-<computeMax value="" />
-<probability value="" />
+<guard value="[ ]" enabled="true"/>
+<afterMin value="" enabled="true"/>
+<afterMax value="" enabled="true"/>
+<computeMin value="" enabled="true"/>
+<computeMax value="" enabled="true"/>
+<probability value="" enabled="true"/>
</extraparam>
</SUBCOMPONENT>
@@ -121,6 +123,7 @@
<cdparam x="410" y="65" />
<sizeparam width="100" height="50" minWidth="40" minHeight="30" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="1400" minY="10" maxY="900" />
<infoparam name="state0" value="state0" />
<TGConnectingPoint num="0" id="42" />
@@ -554,7 +557,7 @@
<Attribute period="6.0" time="ns" processCode="void processing() {
in.read();
}
- " listStruct="" nameTemplate="" typeTemplate="int" listTypedef="" />
+ " listStruct="" nameTemplate="" typeTemplate="int" listTypedef="" />
</extraparam>
</SUBCOMPONENT>
<SUBCOMPONENT type="1604" id="264" >
@@ -599,7 +602,7 @@
out_de.write( (int) x);
tdf_out.write(x);
}
- " listStruct="" nameTemplate="" typeTemplate="int" listTypedef="" />
+ " listStruct="" nameTemplate="" typeTemplate="int" listTypedef="" />
</extraparam>
</SUBCOMPONENT>
<SUBCOMPONENT type="1606" id="283" >
diff --git a/modeling/testforkandjoin.xml b/modeling/testforkandjoin.xml
index f79ec47ac5..f205175918 100644
--- a/modeling/testforkandjoin.xml
+++ b/modeling/testforkandjoin.xml
@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="ISO-8859-1"?>
+<?xml version="1.0" encoding="UTF-8"?>
<TURTLEGMODELING version="1.0beta">
@@ -9,7 +9,7 @@
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="Connector between ports" />
<P1 x="418" y="288" id="5" />
-<P2 x="521" y="399" id="20" />
+<P2 x="508" y="412" id="20" />
<AutomaticDrawing data="true" />
</CONNECTOR>
<CONNECTOR type="126" id="2" >
@@ -17,14 +17,14 @@
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="Connector between ports" />
<P1 x="412" y="279" id="7" />
-<P2 x="525" y="159" id="31" />
+<P2 x="512" y="172" id="31" />
<AutomaticDrawing data="true" />
</CONNECTOR>
<CONNECTOR type="126" id="3" >
<cdparam x="292" y="261" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="Connector between ports" />
-<P1 x="279" y="248" id="42" />
+<P1 x="292" y="261" id="42" />
<P2 x="396" y="288" id="4" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -176,12 +176,13 @@
<cdparam x="377" y="113" />
<sizeparam width="74" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="read channel" value="chfork2(5) " />
<TGConnectingPoint num="0" id="55" />
<TGConnectingPoint num="1" id="56" />
<extraparam>
-<Data channelName="chfork2" nbOfSamples="5" secPattern="" isAttacker="No" />
+<Data channelName="chfork2" nbOfSamples="5" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -198,7 +199,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="58" />
+<P1 x="407" y="65" id="58" />
<P2 x="414" y="108" id="55" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -227,12 +228,13 @@
<cdparam x="382" y="110" />
<sizeparam width="74" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="read channel" value="chfork1(5) " />
<TGConnectingPoint num="0" id="64" />
<TGConnectingPoint num="1" id="65" />
<extraparam>
-<Data channelName="chfork1" nbOfSamples="5" secPattern="" isAttacker="No" />
+<Data channelName="chfork1" nbOfSamples="5" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -249,7 +251,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="67" />
+<P1 x="407" y="65" id="67" />
<P2 x="419" y="105" id="64" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -278,12 +280,13 @@
<cdparam x="382" y="112" />
<sizeparam width="62" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="write channel" value="chfork(5)" />
<TGConnectingPoint num="0" id="73" />
<TGConnectingPoint num="1" id="74" />
<extraparam>
-<Data channelName="chfork" nbOfSamples="5" secPattern="" isAttacker="No" />
+<Data channelName="chfork" nbOfSamples="5" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -300,7 +303,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="76" />
+<P1 x="407" y="65" id="76" />
<P2 x="413" y="107" id="73" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -504,9 +507,9 @@
<SUBCOMPONENT type="1101" id="188" >
<father id="213" num="0" />
<cdparam x="105" y="292" />
-<sizeparam width="100" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="102" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="104" minY="0" maxY="60" />
+<cdrectangleparam minX="0" maxX="102" minY="0" maxY="60" />
<infoparam name="TGComponent" value="FVFork::src" />
<TGConnectingPoint num="0" id="180" />
<TGConnectingPoint num="1" id="181" />
@@ -559,9 +562,9 @@
<SUBCOMPONENT type="1101" id="222" >
<father id="247" num="0" />
<cdparam x="1349" y="701" />
-<sizeparam width="116" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="119" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="134" minY="0" maxY="160" />
+<cdrectangleparam minX="0" maxX="131" minY="0" maxY="160" />
<infoparam name="TGComponent" value="FVFork::Dest2" />
<TGConnectingPoint num="0" id="214" />
<TGConnectingPoint num="1" id="215" />
@@ -614,9 +617,9 @@
<SUBCOMPONENT type="1101" id="256" >
<father id="281" num="0" />
<cdparam x="1165" y="190" />
-<sizeparam width="116" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="119" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="121" minY="0" maxY="66" />
+<cdrectangleparam minX="0" maxX="118" minY="0" maxY="66" />
<infoparam name="TGComponent" value="FVFork::Dest1" />
<TGConnectingPoint num="0" id="248" />
<TGConnectingPoint num="1" id="249" />
@@ -741,9 +744,9 @@
<SUBCOMPONENT type="1103" id="340" >
<father id="365" num="0" />
<cdparam x="854" y="834" />
-<sizeparam width="174" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="178" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="209" minY="0" maxY="162" />
+<cdrectangleparam minX="0" maxX="205" minY="0" maxY="162" />
<infoparam name="TGComponent" value="FVFork::chfork__chfork2" />
<TGConnectingPoint num="0" id="332" />
<TGConnectingPoint num="1" id="333" />
@@ -796,9 +799,9 @@
<SUBCOMPONENT type="1103" id="374" >
<father id="399" num="0" />
<cdparam x="668" y="132" />
-<sizeparam width="174" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="178" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="172" minY="0" maxY="120" />
+<cdrectangleparam minX="0" maxX="168" minY="0" maxY="120" />
<infoparam name="TGComponent" value="FVFork::chfork__chfork1" />
<TGConnectingPoint num="0" id="366" />
<TGConnectingPoint num="1" id="367" />
@@ -1115,12 +1118,13 @@
<cdparam x="375" y="98" />
<sizeparam width="73" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="write channel" value="chjoin1(5)" />
<TGConnectingPoint num="0" id="464" />
<TGConnectingPoint num="1" id="465" />
<extraparam>
-<Data channelName="chjoin1" nbOfSamples="5" secPattern="" isAttacker="No" />
+<Data channelName="chjoin1" nbOfSamples="5" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -1137,7 +1141,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="467" />
+<P1 x="407" y="65" id="467" />
<P2 x="411" y="93" id="464" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -1166,12 +1170,13 @@
<cdparam x="385" y="106" />
<sizeparam width="77" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="read channel" value="chjoin(10) " />
<TGConnectingPoint num="0" id="473" />
<TGConnectingPoint num="1" id="474" />
<extraparam>
-<Data channelName="chjoin" nbOfSamples="10" secPattern="" isAttacker="No" />
+<Data channelName="chjoin" nbOfSamples="10" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -1188,7 +1193,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="476" />
+<P1 x="407" y="65" id="476" />
<P2 x="423" y="101" id="473" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -1217,12 +1222,13 @@
<cdparam x="377" y="108" />
<sizeparam width="73" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="write channel" value="chjoin2(5)" />
<TGConnectingPoint num="0" id="482" />
<TGConnectingPoint num="1" id="483" />
<extraparam>
-<Data channelName="chjoin2" nbOfSamples="5" secPattern="" isAttacker="No" />
+<Data channelName="chjoin2" nbOfSamples="5" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -1239,7 +1245,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="485" />
+<P1 x="407" y="65" id="485" />
<P2 x="413" y="103" id="482" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -1334,11 +1340,11 @@
</COMPONENT>
<SUBCOMPONENT type="1103" id="522" >
<father id="556" num="0" />
-<cdparam x="146" y="537" />
+<cdparam x="170" y="586" />
<sizeparam width="166" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="0" maxX="101" minY="0" maxY="175" />
-<infoparam name="TGComponent" value="FVJoin::chjoin2__chjoin" />
+<infoparam name="TGComponent" value="FVJoin::chjoin1__chjoin" />
<TGConnectingPoint num="0" id="514" />
<TGConnectingPoint num="1" id="515" />
<TGConnectingPoint num="2" id="516" />
@@ -1348,16 +1354,16 @@
<TGConnectingPoint num="6" id="520" />
<TGConnectingPoint num="7" id="521" />
<extraparam>
-<info value="FVJoin::chjoin2__chjoin" communicationName="chjoin2__chjoin" referenceCommunicationName="FVJoin" priority="0" typeName="channel" />
+<info value="FVJoin::chjoin1__chjoin" communicationName="chjoin1__chjoin" referenceCommunicationName="FVJoin" priority="0" typeName="channel" />
</extraparam>
</SUBCOMPONENT>
<SUBCOMPONENT type="1103" id="531" >
<father id="556" num="1" />
-<cdparam x="170" y="586" />
+<cdparam x="146" y="537" />
<sizeparam width="166" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="0" maxX="101" minY="0" maxY="175" />
-<infoparam name="TGComponent" value="FVJoin::chjoin1__chjoin" />
+<infoparam name="TGComponent" value="FVJoin::chjoin2__chjoin" />
<TGConnectingPoint num="0" id="523" />
<TGConnectingPoint num="1" id="524" />
<TGConnectingPoint num="2" id="525" />
@@ -1367,7 +1373,7 @@
<TGConnectingPoint num="6" id="529" />
<TGConnectingPoint num="7" id="530" />
<extraparam>
-<info value="FVJoin::chjoin1__chjoin" communicationName="chjoin1__chjoin" referenceCommunicationName="FVJoin" priority="0" typeName="channel" />
+<info value="FVJoin::chjoin2__chjoin" communicationName="chjoin2__chjoin" referenceCommunicationName="FVJoin" priority="0" typeName="channel" />
</extraparam>
</SUBCOMPONENT>
@@ -1481,9 +1487,9 @@
<SUBCOMPONENT type="1101" id="615" >
<father id="640" num="0" />
<cdparam x="183" y="295" />
-<sizeparam width="103" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="105" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="101" minY="0" maxY="60" />
+<cdrectangleparam minX="0" maxX="99" minY="0" maxY="60" />
<infoparam name="TGComponent" value="FVJoin::dest" />
<TGConnectingPoint num="0" id="607" />
<TGConnectingPoint num="1" id="608" />
@@ -1979,12 +1985,13 @@
<cdparam x="380" y="117" />
<sizeparam width="69" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="read channel" value="comm(3) " />
<TGConnectingPoint num="0" id="844" />
<TGConnectingPoint num="1" id="845" />
<extraparam>
-<Data channelName="comm" nbOfSamples="3" secPattern="" isAttacker="No" />
+<Data channelName="comm" nbOfSamples="3" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -2001,7 +2008,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="847" />
+<P1 x="407" y="65" id="847" />
<P2 x="414" y="112" id="844" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -2030,12 +2037,13 @@
<cdparam x="378" y="98" />
<sizeparam width="65" height="20" minWidth="30" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
+<enabled value="true" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="write channel" value="comm(3)" />
<TGConnectingPoint num="0" id="853" />
<TGConnectingPoint num="1" id="854" />
<extraparam>
-<Data channelName="comm" nbOfSamples="3" secPattern="" isAttacker="No" />
+<Data channelName="comm" nbOfSamples="3" secPattern="" isAttacker="No" isEncForm="No" />
</extraparam>
</COMPONENT>
@@ -2052,7 +2060,7 @@
<cdparam x="407" y="70" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="null" />
-<P1 x="407" y="70" id="856" />
+<P1 x="407" y="65" id="856" />
<P2 x="410" y="93" id="853" />
<AutomaticDrawing data="true" />
</CONNECTOR>
@@ -2074,176 +2082,157 @@
<Modeling type="TML Architecture" nameTab="Architecture" >
<TMLArchiDiagramPanel name="DIPLODOCUS architecture and mapping Diagram" minX="10" maxX="2500" minY="10" maxY="1500" attributes="0" masterClockFrequency="200" >
-<COMPONENT type="1105" id="884" >
+<COMPONENT type="1105" id="893" >
<cdparam x="669" y="81" />
<sizeparam width="200" height="200" minWidth="100" minHeight="35" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="Memory0" value="name" />
-<TGConnectingPoint num="0" id="860" />
-<TGConnectingPoint num="1" id="861" />
-<TGConnectingPoint num="2" id="862" />
-<TGConnectingPoint num="3" id="863" />
-<TGConnectingPoint num="4" id="864" />
-<TGConnectingPoint num="5" id="865" />
-<TGConnectingPoint num="6" id="866" />
-<TGConnectingPoint num="7" id="867" />
-<TGConnectingPoint num="8" id="868" />
-<TGConnectingPoint num="9" id="869" />
-<TGConnectingPoint num="10" id="870" />
-<TGConnectingPoint num="11" id="871" />
-<TGConnectingPoint num="12" id="872" />
-<TGConnectingPoint num="13" id="873" />
-<TGConnectingPoint num="14" id="874" />
-<TGConnectingPoint num="15" id="875" />
-<TGConnectingPoint num="16" id="876" />
-<TGConnectingPoint num="17" id="877" />
-<TGConnectingPoint num="18" id="878" />
-<TGConnectingPoint num="19" id="879" />
-<TGConnectingPoint num="20" id="880" />
-<TGConnectingPoint num="21" id="881" />
-<TGConnectingPoint num="22" id="882" />
-<TGConnectingPoint num="23" id="883" />
+<TGConnectingPoint num="0" id="869" />
+<TGConnectingPoint num="1" id="870" />
+<TGConnectingPoint num="2" id="871" />
+<TGConnectingPoint num="3" id="872" />
+<TGConnectingPoint num="4" id="873" />
+<TGConnectingPoint num="5" id="874" />
+<TGConnectingPoint num="6" id="875" />
+<TGConnectingPoint num="7" id="876" />
+<TGConnectingPoint num="8" id="877" />
+<TGConnectingPoint num="9" id="878" />
+<TGConnectingPoint num="10" id="879" />
+<TGConnectingPoint num="11" id="880" />
+<TGConnectingPoint num="12" id="881" />
+<TGConnectingPoint num="13" id="882" />
+<TGConnectingPoint num="14" id="883" />
+<TGConnectingPoint num="15" id="884" />
+<TGConnectingPoint num="16" id="885" />
+<TGConnectingPoint num="17" id="886" />
+<TGConnectingPoint num="18" id="887" />
+<TGConnectingPoint num="19" id="888" />
+<TGConnectingPoint num="20" id="889" />
+<TGConnectingPoint num="21" id="890" />
+<TGConnectingPoint num="22" id="891" />
+<TGConnectingPoint num="23" id="892" />
<extraparam>
<info stereotype="MEMORY" nodeName="Memory0" />
<attributes byteDataSize="4" memorySize="1024" clockRatio="1" bufferType="0" />
</extraparam>
</COMPONENT>
-<SUBCOMPONENT type="1103" id="974" >
-<father id="884" num="0" />
+<SUBCOMPONENT type="1103" id="868" >
+<father id="893" num="0" />
<cdparam x="672" y="150" />
-<sizeparam width="113" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="111" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="87" minY="0" maxY="160" />
+<cdrectangleparam minX="0" maxX="89" minY="0" maxY="160" />
<infoparam name="TGComponent" value="Basic::comm" />
-<TGConnectingPoint num="0" id="975" />
-<TGConnectingPoint num="1" id="976" />
-<TGConnectingPoint num="2" id="977" />
-<TGConnectingPoint num="3" id="978" />
-<TGConnectingPoint num="4" id="979" />
-<TGConnectingPoint num="5" id="980" />
-<TGConnectingPoint num="6" id="981" />
-<TGConnectingPoint num="7" id="982" />
+<TGConnectingPoint num="0" id="860" />
+<TGConnectingPoint num="1" id="861" />
+<TGConnectingPoint num="2" id="862" />
+<TGConnectingPoint num="3" id="863" />
+<TGConnectingPoint num="4" id="864" />
+<TGConnectingPoint num="5" id="865" />
+<TGConnectingPoint num="6" id="866" />
+<TGConnectingPoint num="7" id="867" />
<extraparam>
<info value="Basic::comm" communicationName="comm" referenceCommunicationName="Basic" priority="0" typeName="channel" />
</extraparam>
</SUBCOMPONENT>
-<COMPONENT type="1102" id="918" >
+<COMPONENT type="1102" id="927" >
<cdparam x="418" y="340" />
<sizeparam width="362" height="126" minWidth="100" minHeight="50" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="Bus0" value="name" />
-<TGConnectingPoint num="0" id="894" />
-<TGConnectingPoint num="1" id="895" />
-<TGConnectingPoint num="2" id="896" />
-<TGConnectingPoint num="3" id="897" />
-<TGConnectingPoint num="4" id="898" />
-<TGConnectingPoint num="5" id="899" />
-<TGConnectingPoint num="6" id="900" />
-<TGConnectingPoint num="7" id="901" />
-<TGConnectingPoint num="8" id="902" />
-<TGConnectingPoint num="9" id="903" />
-<TGConnectingPoint num="10" id="904" />
-<TGConnectingPoint num="11" id="905" />
-<TGConnectingPoint num="12" id="906" />
-<TGConnectingPoint num="13" id="907" />
-<TGConnectingPoint num="14" id="908" />
-<TGConnectingPoint num="15" id="909" />
-<TGConnectingPoint num="16" id="910" />
-<TGConnectingPoint num="17" id="911" />
-<TGConnectingPoint num="18" id="912" />
-<TGConnectingPoint num="19" id="913" />
-<TGConnectingPoint num="20" id="914" />
-<TGConnectingPoint num="21" id="915" />
-<TGConnectingPoint num="22" id="916" />
-<TGConnectingPoint num="23" id="917" />
+<TGConnectingPoint num="0" id="903" />
+<TGConnectingPoint num="1" id="904" />
+<TGConnectingPoint num="2" id="905" />
+<TGConnectingPoint num="3" id="906" />
+<TGConnectingPoint num="4" id="907" />
+<TGConnectingPoint num="5" id="908" />
+<TGConnectingPoint num="6" id="909" />
+<TGConnectingPoint num="7" id="910" />
+<TGConnectingPoint num="8" id="911" />
+<TGConnectingPoint num="9" id="912" />
+<TGConnectingPoint num="10" id="913" />
+<TGConnectingPoint num="11" id="914" />
+<TGConnectingPoint num="12" id="915" />
+<TGConnectingPoint num="13" id="916" />
+<TGConnectingPoint num="14" id="917" />
+<TGConnectingPoint num="15" id="918" />
+<TGConnectingPoint num="16" id="919" />
+<TGConnectingPoint num="17" id="920" />
+<TGConnectingPoint num="18" id="921" />
+<TGConnectingPoint num="19" id="922" />
+<TGConnectingPoint num="20" id="923" />
+<TGConnectingPoint num="21" id="924" />
+<TGConnectingPoint num="22" id="925" />
+<TGConnectingPoint num="23" id="926" />
<extraparam>
<info stereotype="BUS-RR" nodeName="Bus0" />
<attributes byteDataSize="4" arbitrationPolicy="0" sliceTime="10000" pipelineSize="1" clockRatio="1" privacy="0" referenceAttack="null" />
</extraparam>
</COMPONENT>
-<SUBCOMPONENT type="1103" id="893" >
-<father id="918" num="0" />
+<SUBCOMPONENT type="1103" id="902" >
+<father id="927" num="0" />
<cdparam x="557" y="388" />
-<sizeparam width="113" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="111" height="40" minWidth="75" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="249" minY="0" maxY="86" />
+<cdrectangleparam minX="0" maxX="251" minY="0" maxY="86" />
<infoparam name="TGComponent" value="Basic::comm" />
-<TGConnectingPoint num="0" id="885" />
-<TGConnectingPoint num="1" id="886" />
-<TGConnectingPoint num="2" id="887" />
-<TGConnectingPoint num="3" id="888" />
-<TGConnectingPoint num="4" id="889" />
-<TGConnectingPoint num="5" id="890" />
-<TGConnectingPoint num="6" id="891" />
-<TGConnectingPoint num="7" id="892" />
+<TGConnectingPoint num="0" id="894" />
+<TGConnectingPoint num="1" id="895" />
+<TGConnectingPoint num="2" id="896" />
+<TGConnectingPoint num="3" id="897" />
+<TGConnectingPoint num="4" id="898" />
+<TGConnectingPoint num="5" id="899" />
+<TGConnectingPoint num="6" id="900" />
+<TGConnectingPoint num="7" id="901" />
<extraparam>
<info value="Basic::comm" communicationName="comm" referenceCommunicationName="Basic" priority="0" typeName="channel" />
</extraparam>
</SUBCOMPONENT>
-<COMPONENT type="1100" id="961" >
+<COMPONENT type="1100" id="970" >
<cdparam x="198" y="79" />
<sizeparam width="250" height="200" minWidth="150" minHeight="100" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
<infoparam name="CPU0" value="name" />
-<TGConnectingPoint num="0" id="937" />
-<TGConnectingPoint num="1" id="938" />
-<TGConnectingPoint num="2" id="939" />
-<TGConnectingPoint num="3" id="940" />
-<TGConnectingPoint num="4" id="941" />
-<TGConnectingPoint num="5" id="942" />
-<TGConnectingPoint num="6" id="943" />
-<TGConnectingPoint num="7" id="944" />
-<TGConnectingPoint num="8" id="945" />
-<TGConnectingPoint num="9" id="946" />
-<TGConnectingPoint num="10" id="947" />
-<TGConnectingPoint num="11" id="948" />
-<TGConnectingPoint num="12" id="949" />
-<TGConnectingPoint num="13" id="950" />
-<TGConnectingPoint num="14" id="951" />
-<TGConnectingPoint num="15" id="952" />
-<TGConnectingPoint num="16" id="953" />
-<TGConnectingPoint num="17" id="954" />
-<TGConnectingPoint num="18" id="955" />
-<TGConnectingPoint num="19" id="956" />
-<TGConnectingPoint num="20" id="957" />
-<TGConnectingPoint num="21" id="958" />
-<TGConnectingPoint num="22" id="959" />
-<TGConnectingPoint num="23" id="960" />
+<TGConnectingPoint num="0" id="946" />
+<TGConnectingPoint num="1" id="947" />
+<TGConnectingPoint num="2" id="948" />
+<TGConnectingPoint num="3" id="949" />
+<TGConnectingPoint num="4" id="950" />
+<TGConnectingPoint num="5" id="951" />
+<TGConnectingPoint num="6" id="952" />
+<TGConnectingPoint num="7" id="953" />
+<TGConnectingPoint num="8" id="954" />
+<TGConnectingPoint num="9" id="955" />
+<TGConnectingPoint num="10" id="956" />
+<TGConnectingPoint num="11" id="957" />
+<TGConnectingPoint num="12" id="958" />
+<TGConnectingPoint num="13" id="959" />
+<TGConnectingPoint num="14" id="960" />
+<TGConnectingPoint num="15" id="961" />
+<TGConnectingPoint num="16" id="962" />
+<TGConnectingPoint num="17" id="963" />
+<TGConnectingPoint num="18" id="964" />
+<TGConnectingPoint num="19" id="965" />
+<TGConnectingPoint num="20" id="966" />
+<TGConnectingPoint num="21" id="967" />
+<TGConnectingPoint num="22" id="968" />
+<TGConnectingPoint num="23" id="969" />
<extraparam>
<info stereotype="CPURR" nodeName="CPU0" />
<attributes nbOfCores="1" byteDataSize="4" schedulingPolicy="0" sliceTime="10000" goIdleTime="10" maxConsecutiveIdleCycles="10" pipelineSize="5" taskSwitchingTime="20" branchingPredictionPenalty="2" cacheMiss="5" execiTime="1" execcTime="1" clockRatio="1" MECType="0" encryption="0"/>
</extraparam>
</COMPONENT>
-<SUBCOMPONENT type="1101" id="927" >
-<father id="961" num="0" />
-<cdparam x="258" y="136" />
-<sizeparam width="113" height="54" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
-<hidden value="false" />
-<cdrectangleparam minX="0" maxX="137" minY="0" maxY="146" />
-<infoparam name="TGComponent" value="Basic::Task1" />
-<TGConnectingPoint num="0" id="919" />
-<TGConnectingPoint num="1" id="920" />
-<TGConnectingPoint num="2" id="921" />
-<TGConnectingPoint num="3" id="922" />
-<TGConnectingPoint num="4" id="923" />
-<TGConnectingPoint num="5" id="924" />
-<TGConnectingPoint num="6" id="925" />
-<TGConnectingPoint num="7" id="926" />
-<extraparam>
-<info value="Basic::Task1" taskName="Task1" referenceTaskName="Basic" priority="0" operation="Dest2" fatherComponentMECType="0" />
-</extraparam>
-</SUBCOMPONENT>
<SUBCOMPONENT type="1101" id="936" >
-<father id="961" num="1" />
+<father id="970" num="0" />
<cdparam x="267" y="218" />
-<sizeparam width="113" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<sizeparam width="110" height="40" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="137" minY="0" maxY="160" />
+<cdrectangleparam minX="0" maxX="140" minY="0" maxY="160" />
<infoparam name="TGComponent" value="Basic::Task2" />
<TGConnectingPoint num="0" id="928" />
<TGConnectingPoint num="1" id="929" />
@@ -2257,25 +2246,44 @@
<info value="Basic::Task2" taskName="Task2" referenceTaskName="Basic" priority="0" operation="Dest2" fatherComponentMECType="0" />
</extraparam>
</SUBCOMPONENT>
+<SUBCOMPONENT type="1101" id="945" >
+<father id="970" num="1" />
+<cdparam x="258" y="136" />
+<sizeparam width="110" height="54" minWidth="100" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="140" minY="0" maxY="146" />
+<infoparam name="TGComponent" value="Basic::Task1" />
+<TGConnectingPoint num="0" id="937" />
+<TGConnectingPoint num="1" id="938" />
+<TGConnectingPoint num="2" id="939" />
+<TGConnectingPoint num="3" id="940" />
+<TGConnectingPoint num="4" id="941" />
+<TGConnectingPoint num="5" id="942" />
+<TGConnectingPoint num="6" id="943" />
+<TGConnectingPoint num="7" id="944" />
+<extraparam>
+<info value="Basic::Task1" taskName="Task1" referenceTaskName="Basic" priority="0" operation="Dest2" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
-<CONNECTOR type="125" id="962" >
+<CONNECTOR type="125" id="971" >
<cdparam x="719" y="281" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="{info}" />
-<P1 x="719" y="281" id="874" />
-<P2 x="689" y="340" id="903" />
+<P1 x="719" y="281" id="883" />
+<P2 x="689" y="340" id="912" />
<AutomaticDrawing data="true" />
<extraparam>
<info priority="0" />
<spy value="false" />
</extraparam>
</CONNECTOR>
-<CONNECTOR type="125" id="963" >
+<CONNECTOR type="125" id="972" >
<cdparam x="385" y="279" />
<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<infoparam name="connector" value="{info}" />
-<P1 x="385" y="279" id="952" />
-<P2 x="418" y="340" id="894" />
+<P1 x="385" y="279" id="961" />
+<P2 x="418" y="340" id="903" />
<AutomaticDrawing data="true" />
<extraparam>
<info priority="0" />
--
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