diff --git a/simulators/c++2/src_simulator/TMLTransaction.cpp b/simulators/c++2/src_simulator/TMLTransaction.cpp
index 14a1066796506633e634d361bc1ae03654f72c8d..b77c818321c588a21cc1882648bf61d7320e3baa 100755
--- a/simulators/c++2/src_simulator/TMLTransaction.cpp
+++ b/simulators/c++2/src_simulator/TMLTransaction.cpp
@@ -46,7 +46,7 @@
 MemPoolNoDel<TMLTransaction> TMLTransaction::memPool(BLOCK_SIZE_TRANS);
 
 
-TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),
+TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),_transactCoreNumber(0),
 #ifdef PENALTIES_ENABLED
                                  _idlePenalty(0), _taskSwitchingPenalty(0), //, _branchingPenalty(0),
 #endif
diff --git a/simulators/c++2/src_simulator/TMLTransaction.h b/simulators/c++2/src_simulator/TMLTransaction.h
index bb82e10398784bfd60dcd476a9e150cbbf2e1244..5a85c1163e2b007bd01a35f5b667c7c5443b69e8 100644
--- a/simulators/c++2/src_simulator/TMLTransaction.h
+++ b/simulators/c++2/src_simulator/TMLTransaction.h
@@ -241,6 +241,8 @@ class TMLTransaction {
   inline void setStateID(ID iID) {_stateID=iID;}
   inline ID getStateID() {return _stateID;}
   inline void setTaskID(ID iID) {_taskID=iID;}
+  inline unsigned int getTransactCoreNumber() {return _transactCoreNumber;}
+  inline void setTransactCoreNumber(unsigned int num) {_transactCoreNumber=num;}
   void toXML(std::ostringstream& glob, int deviceID, std::string deviceName) const;
 
 
@@ -255,6 +257,8 @@ class TMLTransaction {
   TMLLength _virtualLength;
   ///Pointer to the command the transaction belongs to
   TMLCommand* _command;
+  ///Core number of the transaction
+  unsigned int _transactCoreNumber;
 #ifdef PENALTIES_ENABLED
   ///Idle penalty
   TMLTime _idlePenalty;
diff --git a/simulators/c++2/src_simulator/arch/CPU.h b/simulators/c++2/src_simulator/arch/CPU.h
index f1c4cd0b7679cb8c92acfaf069719ae7d7945667..ef8f099df2fbd049f0a1c9c848a3fa9c009f61b1 100755
--- a/simulators/c++2/src_simulator/arch/CPU.h
+++ b/simulators/c++2/src_simulator/arch/CPU.h
@@ -111,6 +111,7 @@ public:
 		SchedulableDevice::writeObject(os);
 		return os;
 	}
+	inline unsigned int getAmoutOfCore(){ return amountOfCore;} 
 	///Invalidate schedule of CPU
 	/*void setRescheduleFlag(){
 		_schedulingNeeded=true;
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index 3191feec1ddb5309a19a99cf64d534435ae1d7ef..917940b2d1198a7584bf25fabea30817e702f611 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -336,6 +336,8 @@ bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
       _endSchedule=getMinEndSchedule();
       initCore();
     }
+    _nextTransaction->setTransactCoreNumber(iCoreNumber);
+    std::cout <<"test transaction core number !!!! "<<_nextTransaction->getTransactCoreNumber()<<std::endl;
     std::cout << "set end schedule CPU: " << _endSchedule << "\n";
     _simulatedTime=max(_simulatedTime,_endSchedule);
     _overallTransNo++; //NEW!!!!!!!!
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index 01ab6a13a60d7dadeae9b676b89673b695921877..51c32eb1d1668d805a790026bbaf1a376ca4a38b 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -184,6 +184,7 @@ std::string SchedulableDevice::determineHTMLCellClass( 	std::map<TMLTask*, std::
 }
 
 void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
+        static unsigned int time=0;
 	myfile << "<h2><span>Scheduling for device: "<< _name << "</span></h2>" << std::endl;
 
 	if ( _transactList.size() == 0 ) {
@@ -197,6 +198,8 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
 		TMLTime aCurrTime = 0;
 
 		for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+		  myfile<<"test transaction core number!!!"<<(*i)->getTransactCoreNumber()<<std::endl;
+		  if( (*i)->getTransactCoreNumber() == time ){
 			TMLTransaction* aCurrTrans = *i;
 			unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
 
@@ -221,7 +224,9 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
 			writeHTMLColumn( myfile, aLength, cellClass, aCurrTrans->toShortString() );
 
 			aCurrTime = aCurrTrans->getEndTime();
+		  }
 		}
+		++time;
 
 		myfile << "</tr>" << std::endl << "<tr>";
 
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index 43f3fe4674ad0e2fc30ae504f6572ea7e8548f1e..be2d4f53271541d9cbc5be98eb9be66721932ba4 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -343,7 +343,8 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
 
     //for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
     for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
-      (*i)->schedule2HTML(myfile);
+      for(unsigned int j = 0; j < (*i)->getAmoutOfCore(); j++) 
+	(*i)->schedule2HTML(myfile);
     }
     //for(BusList::const_iterator j=_simComp->getBusIterator(false); j != _simComp->getBusIterator(true); ++j){
     for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){