diff --git a/src/ddtranslatorSoclib/toTopCell/Declaration.java b/src/ddtranslatorSoclib/toTopCell/Declaration.java
index 1534b23b8e37e2170aa7efccf2bf379b5401fca5..3b0e05ce84b0923f225f79512f357b3b70130b89 100755
--- a/src/ddtranslatorSoclib/toTopCell/Declaration.java
+++ b/src/ddtranslatorSoclib/toTopCell/Declaration.java
@@ -64,7 +64,7 @@ public class Declaration {
//Is the platform clustered?
int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar().size();
- nb_clusters=2;
+ //nb_clusters=2;
boolean trace_caba=true;
@@ -267,19 +267,42 @@ if(nb_clusters==0){
System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
- declaration += "soclib::caba::VciVgmn<vci_param> "+ vgmn.getVgmnName() +" (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "+ 1 +"," + 6 +
- "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+ // declaration += "soclib::caba::VciVgmn<vci_param> "+ vgmn.getVgmnName() +" (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "+ 1 +"," + 6 +
+ // "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+
+ //DG 10.08. only one central interconnect
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "+ 1 +"," + 6 +
+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+
int i=0;
- if(trace_caba){
- for(i=0;i<TopCellGenerator.avatardd.getNb_init();i++){
- declaration += "soclib::caba::VciLogger<vci_param> logger(\"logger" + i+"\",maptab);" + CR2;
- }
- int j=i;
- for(i=0;i<TopCellGenerator.avatardd.getAllRAM().size()+3;i++){
- declaration += "soclib::caba::VciLogger<vci_param> logger(\"logger" + j+"\",maptab);" + CR2;
- }
- }
+
+
+ //monitoring either by logger(1) ou stats (2)
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+
+ if (ram.getMonitored()==1){
+ int number = ram.getNo_target();
+ declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
+ i++;
+ }
+ else{
+ if (ram.getMonitored()==2){
+ int number = ram.getNo_target();
+
+ String strArray="";
+ for(AvatarChannel channel: ram.getChannels()){
+
+ String chname = generateName(channel);
+
+ strArray=strArray+"\""+chname+"\",";
+ }
+
+ declaration += "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"+i+"(\"mwmr_stats" + i+"\",maptab, data_ldr, \"mwmr"+i+".log\",stringArray("+strArray+"NULL));" + CR2;
+ i++;
+ }
+ }
+ }
// if VGMN was not last in input file, update here
vgmn.setNbOfAttachedInitiators(1);
diff --git a/src/ddtranslatorSoclib/toTopCell/Header.java b/src/ddtranslatorSoclib/toTopCell/Header.java
index abb5605c0b30fd041301ffcb41d535ee1bcfa4c5..58e40b81914c2f2d65fbd1cbd8da64f7870566aa 100755
--- a/src/ddtranslatorSoclib/toTopCell/Header.java
+++ b/src/ddtranslatorSoclib/toTopCell/Header.java
@@ -46,8 +46,9 @@ int nb_clusters=5;
+ "#include \"vci_simhelper.h\"" + CR + "#include \"vci_fd_access.h\"" + CR
+ "#include \"vci_ethernet.h\"" + CR
+ "#include \"vci_rttimer.h\"" + CR
- + "#include \"vci_logger.h\"" + CR
- + "#include \"vci_mwmr_stats.h\"" + CR2;
+ + "#include \"vci_logger.h\"" + CR
++ "#include \"vci_logger.h\"" + CR
+ + "#include \"vci_local_crossbar.h\"" + CR2;
header = header +"namespace {" + CR
+"std::vector<std::string> stringArray(" + CR
diff --git a/src/ddtranslatorSoclib/toTopCell/Loader.java b/src/ddtranslatorSoclib/toTopCell/Loader.java
index e68e7547cdc56e87cd0d0cf1b792c073f3611c83..64f151d717259666279bdcdb6d76cb54b4246ab6 100755
--- a/src/ddtranslatorSoclib/toTopCell/Loader.java
+++ b/src/ddtranslatorSoclib/toTopCell/Loader.java
@@ -20,7 +20,7 @@ public class Loader {
public static String getLoader() {
int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- nb_clusters=2;
+ //nb_clusters=2;
loader = CR2 + "//-------------------------Call Loader---------------------------------" + CR2 ;
loader = loader + "std::cerr << \"caba-vgmn-mutekh_kernel_tutorial SoCLib simulator for MutekH\" << std::endl;"
diff --git a/src/ddtranslatorSoclib/toTopCell/MappingTable.java b/src/ddtranslatorSoclib/toTopCell/MappingTable.java
index c7a2f1dae7dc85a96999a448f0d8c8d8e36a78c7..e6bd997968955c9190666532235b188762eec0cf 100755
--- a/src/ddtranslatorSoclib/toTopCell/MappingTable.java
+++ b/src/ddtranslatorSoclib/toTopCell/MappingTable.java
@@ -19,7 +19,7 @@ public class MappingTable {
public static String getMappingTable() {
int l=0;
int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- nb_clusters=2;
+ //nb_clusters=2;
if(nb_clusters == 0){
mapping = CR2 + "//-----------------------mapping table------------------------" + CR2;
diff --git a/src/ddtranslatorSoclib/toTopCell/NetList.java b/src/ddtranslatorSoclib/toTopCell/NetList.java
index 3af9505d9bf3198aa7eac55deaf839cc484dbb3d..bdf728b9271682e92a129087408dc5eef04ecc88 100755
--- a/src/ddtranslatorSoclib/toTopCell/NetList.java
+++ b/src/ddtranslatorSoclib/toTopCell/NetList.java
@@ -14,7 +14,7 @@ public class NetList {
public static String getNetlist(String icn, boolean _tracing) {
int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- nb_clusters=2;
+ //nb_clusters=2;
boolean trace_caba=true; //tracing is enabled in cycle accurate mode
tracing = _tracing;
String netlist;
@@ -142,9 +142,9 @@ public class NetList {
netlist = netlist + "vgsb.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getNo_ram()+");" + CR2;
}
}
- netlist = netlist + "vci_locks.p_clk(" + NAME_CLK + ");" + CR;
- netlist = netlist + "vci_locks.p_resetn(" + NAME_RST + ");" + CR;
- netlist = netlist + "vci_locks.p_vci(signal_vci_vcilocks);" + CR2;
+ // netlist = netlist + "vci_locks.p_clk(" + NAME_CLK + ");" + CR;
+ // netlist = netlist + "vci_locks.p_resetn(" + NAME_RST + ");" + CR;
+ // netlist = netlist + "vci_locks.p_vci(signal_vci_vcilocks);" + CR2;
//MWMR RAM
netlist = netlist +"mwmr_ram.p_clk(" + NAME_CLK + ");" + CR;
netlist = netlist +"mwmr_ram.p_resetn(" + NAME_RST + ");" + CR;
@@ -167,16 +167,18 @@ netlist = netlist + "// RAM netlist" + CR2;
netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getNo_ram()+");" + CR2;
//target number for local cluster: this is set at avatardd creation
- netlist = netlist + "local_crossbar.p_to_target["+ram.getNo_target()+"](signal_vci_vciram"+ram.getNo_ram()+");" + CR2;
+
+ //DG 10.08. haben wir getno_cluster?i ist inkorrekt
+ netlist = netlist + "crossbar"+ram.getNo_cluster()+".p_to_target["+ram.getNo_target()+"](signal_vci_vciram"+ram.getNo_ram()+");" + CR2;
}
//one locks engine per cluster is added transparently
- for(i=0;i<nb_clusters;i++){
+ /* for(i=0;i<nb_clusters;i++){
netlist = netlist + "vci_locks"+i+".p_clk(" + NAME_CLK + ");" + CR;
netlist = netlist + "vci_locks"+i+".p_resetn(" + NAME_RST + ");" + CR;
netlist = netlist + "vci_locks"+i+".p_vci(signal_vci_vcilocks);" + CR2;
netlist = netlist + "vci_locks"+i+".p_to_target["+i+"](signal_vci_locks"+i+");" + CR2;
- }
+ }*/
//one mwmr ram and one mwmrdram are added transparently
@@ -190,9 +192,9 @@ netlist = netlist + "// RAM netlist" + CR2;
*/
for(i=0;i<nb_clusters;i++){
- netlist = netlist + "local_crossbar"+i+".p_to_target["+1+"](signal_vci_mwmr_ram"+i+");" + CR2;
+ netlist = netlist + "crossbar"+i+".p_to_target["+1+"](signal_vci_mwmr_ram"+i+");" + CR2;
//netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
- netlist = netlist + "local_crossbar"+i+".p_to_target["+2+"](signal_vci_mwmrd_ram"+i+");" + CR2;
+ netlist = netlist + "crossbar"+i+".p_to_target["+2+"](signal_vci_mwmrd_ram"+i+");" + CR2;
//netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
}
}
@@ -208,7 +210,7 @@ netlist = netlist + "// RAM netlist" + CR2;
netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
+ // netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
}
}else{
//clustered case directly connected to VGSB/to VGMN
@@ -257,7 +259,7 @@ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib
else{
for(i=0;i<nb_clusters;i++){
- netlist = netlist + "local_crossbar"+i+".p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
+ netlist = netlist + "crossbar"+i+".p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
//DG 4.4. recalculate irq addresses! Hypothesis 5 devices per cluster
netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+(tty.getNo_cluster()*5)+"]);" + CR2;
}
@@ -372,7 +374,7 @@ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib
netlist += "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" + CR;
netlist += "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");" + CR;
netlist += "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcilocks ,\"signal_vci_vcilocks\");" + CR;
+ //netlist += "sc_trace(tf, signal_vci_vcilocks ,\"signal_vci_vcilocks\");" + CR;
netlist += "sc_trace(tf, signal_vci_mwmr_ram ,\"signal_vci_mwmr_ram\");" + CR;
netlist += "sc_trace(tf, signal_vci_mwmrd_ram ,\"signal_vci_mwmrd_ram\");" + CR;
netlist += "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");" + CR;
diff --git a/src/ddtranslatorSoclib/toTopCell/Signal.java b/src/ddtranslatorSoclib/toTopCell/Signal.java
index 5b1d640163e410357d40045a95a72c663c9c60b0..efdf4f04ba733a6e9182fd491f48601ca40969f1 100755
--- a/src/ddtranslatorSoclib/toTopCell/Signal.java
+++ b/src/ddtranslatorSoclib/toTopCell/Signal.java
@@ -16,7 +16,7 @@ public class Signal {
public static String getSignal() {
int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- nb_clusters=2;
+ //nb_clusters=2;
String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];"+ CR;
diff --git a/src/tmltranslator/HwCrossbar.java b/src/tmltranslator/HwCrossbar.java
new file mode 100755
index 0000000000000000000000000000000000000000..bfaf72f34744be569776e7a0a56df802625d1065
--- /dev/null
+++ b/src/tmltranslator/HwCrossbar.java
@@ -0,0 +1,73 @@
+/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+
+ludovic.apvrille AT enst.fr
+
+This software is a computer program whose purpose is to allow the
+edition of TURTLE analysis, design and deployment diagrams, to
+allow the generation of RT-LOTOS or Java code from this diagram,
+and at last to allow the analysis of formal validation traces
+obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+from INRIA Rhone-Alpes.
+
+This software is governed by the CeCILL license under French law and
+abiding by the rules of distribution of free software. You can use,
+modify and/ or redistribute the software under the terms of the CeCILL
+license as circulated by CEA, CNRS and INRIA at the following URL
+"http://www.cecill.info".
+
+As a counterpart to the access to the source code and rights to copy,
+modify and redistribute granted by the license, users are provided only
+with a limited warranty and the software's author, the holder of the
+economic rights, and the successive licensors have only limited
+liability.
+
+In this respect, the user's attention is drawn to the risks associated
+with loading, using, modifying and/or developing or reproducing the
+software by the user in light of its specific status of free software,
+that may mean that it is complicated to manipulate, and that also
+therefore means that it is reserved for developers and experienced
+professionals having in-depth computer knowledge. Users are therefore
+encouraged to load and test the software's suitability as regards their
+requirements in conditions enabling the security of their systems and/or
+data to be ensured and, more generally, to use and operate it in the
+same conditions as regards security.
+
+The fact that you are presently reading this means that you have had
+knowledge of the CeCILL license and that you accept its terms.
+
+/**
+* Class HwCrossbar
+* Creation: 05/09/2007
+* @version 1.0 05/09/2007
+* @author Ludovic APVRILLE
+* @see
+*/
+
+package tmltranslator;
+
+import java.util.*;
+
+
+public class HwCrossbar extends HwCommunicationNode {
+
+ /* public static final int BASIC_ROUND_ROBIN = 0;
+ public static final int PRIORITY_BASED = 1;
+ public static final int CAN = 2;
+ public static final int CROSSBAR = 3;
+ public static final int DEFAULT_SLICE_TIME = 10000; // in microseconds
+ public static final int BUS_PUBLIC = 0;
+ public static final int BUS_PRIVATE = 1;*/
+ public static final int DEFAULT_BYTE_DATA_SIZE = 4;
+ /* public static final int DEFAULT_PIPELINE_SIZE = 1;
+ public static final int DEFAULT_ARBITRATION = BASIC_ROUND_ROBIN;
+ */
+ public int byteDataSize = DEFAULT_BYTE_DATA_SIZE; // In bytes. Should more than 0
+ /* public int pipelineSize = DEFAULT_PIPELINE_SIZE;
+ public int arbitration = DEFAULT_ARBITRATION;
+ public int privacy = BUS_PUBLIC;
+ public int sliceTime = DEFAULT_SLICE_TIME;*/
+ public HwCrossbar(String _name) {
+ super(_name);
+ }
+
+}
diff --git a/src/tmltranslator/HwVGMN.java b/src/tmltranslator/HwVGMN.java
new file mode 100755
index 0000000000000000000000000000000000000000..77beea8a94c3521bafc268e3ea146efe991714dc
--- /dev/null
+++ b/src/tmltranslator/HwVGMN.java
@@ -0,0 +1,75 @@
+/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+
+ludovic.apvrille AT enst.fr
+
+This software is a computer program whose purpose is to allow the
+edition of TURTLE analysis, design and deployment diagrams, to
+allow the generation of RT-LOTOS or Java code from this diagram,
+and at last to allow the analysis of formal validation traces
+obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+from INRIA Rhone-Alpes.
+
+This software is governed by the CeCILL license under French law and
+abiding by the rules of distribution of free software. You can use,
+modify and/ or redistribute the software under the terms of the CeCILL
+license as circulated by CEA, CNRS and INRIA at the following URL
+"http://www.cecill.info".
+
+As a counterpart to the access to the source code and rights to copy,
+modify and redistribute granted by the license, users are provided only
+with a limited warranty and the software's author, the holder of the
+economic rights, and the successive licensors have only limited
+liability.
+
+In this respect, the user's attention is drawn to the risks associated
+with loading, using, modifying and/or developing or reproducing the
+software by the user in light of its specific status of free software,
+that may mean that it is complicated to manipulate, and that also
+therefore means that it is reserved for developers and experienced
+professionals having in-depth computer knowledge. Users are therefore
+encouraged to load and test the software's suitability as regards their
+requirements in conditions enabling the security of their systems and/or
+data to be ensured and, more generally, to use and operate it in the
+same conditions as regards security.
+
+The fact that you are presently reading this means that you have had
+knowledge of the CeCILL license and that you accept its terms.
+
+/**
+* Class HwVGMN
+* Creation: 05/09/2007
+* @version 1.0 05/09/2007
+* @author Ludovic APVRILLE adapted by Daniela Genius 10/08/2016
+* @see
+*/
+
+package tmltranslator;
+
+import java.util.*;
+
+
+public class HwVGMN extends HwCommunicationNode {
+
+ /* public static final int BASIC_ROUND_ROBIN = 0;
+ public static final int PRIORITY_BASED = 1;
+ public static final int CAN = 2;
+ public static final int CROSSBAR = 3;
+ public static final int DEFAULT_SLICE_TIME = 10000; // in microseconds
+ public static final int BUS_PUBLIC = 0;
+ public static final int BUS_PRIVATE = 1;*/
+ public static final int DEFAULT_BYTE_DATA_SIZE = 4;
+ /*
+ public static final int DEFAULT_PIPELINE_SIZE = 1;
+ public static final int DEFAULT_ARBITRATION = BASIC_ROUND_ROBIN;
+ */
+ public int byteDataSize = DEFAULT_BYTE_DATA_SIZE; // In bytes. Should more than 0
+ /* public int pipelineSize = DEFAULT_PIPELINE_SIZE;
+ public int arbitration = DEFAULT_ARBITRATION;
+ public int privacy = BUS_PUBLIC;
+ public int sliceTime = DEFAULT_SLICE_TIME;*/
+
+ public HwVGMN(String _name) {
+ super(_name);
+ }
+
+}
diff --git a/src/ui/TGComponentManager.java b/src/ui/TGComponentManager.java
index 13c9a5654022a63663e30869ceba56ee73f4c89b..4b0f3fd08e9962a403f5d7d1a9b090540074dfe4 100755
--- a/src/ui/TGComponentManager.java
+++ b/src/ui/TGComponentManager.java
@@ -638,17 +638,11 @@ public class TGComponentManager {
case ADD_BUSNODE:
tgc = new ADDBusNode(x, y, tdp.getMinX(), tdp.getMaxX(), tdp.getMinY(), tdp.getMaxY(), false, null, tdp);
break;
- case ADD_VGMNNODE:
- {
- TraceManager.addDev("****vgmn");
- tgc = new ADDVgmnNode(x, y, tdp.getMinX(), tdp.getMaxX(), tdp.getMinY(), tdp.getMaxY(), false, null, tdp);
- }
- break;
- case ADD_CROSSBARNODE:
- {
- TraceManager.addDev("****crossbar");
- tgc = new ADDCrossbarNode(x, y, tdp.getMinX(), tdp.getMaxX(), tdp.getMinY(), tdp.getMaxY(), false, null, tdp);
- }
+ case ADD_VGMNNODE:
+ tgc = new ADDVgmnNode(x, y, tdp.getMinX(), tdp.getMaxX(), tdp.getMinY(), tdp.getMaxY(), false, null, tdp);
+ break;
+ case ADD_CROSSBARNODE:
+ tgc = new ADDCrossbarNode(x, y, tdp.getMinX(), tdp.getMaxX(), tdp.getMinY(), tdp.getMaxY(), false, null, tdp);
break;
case ADD_TTYNODE:
tgc = new ADDTTYNode(x, y, tdp.getMinX(), tdp.getMaxX(), tdp.getMinY(), tdp.getMaxY(), false, null, tdp);