From 0d6b30acd41e9bb8f523a10d530e7a91b8d99014 Mon Sep 17 00:00:00 2001
From: niusiyuan <siyuan.niu@telecom-paristech.fr>
Date: Fri, 5 Jul 2019 17:40:32 +0200
Subject: [PATCH] bug not sovled
---
simulators/c++2/src_simulator/app/TMLCommand.cpp | 1 +
simulators/c++2/src_simulator/arch/FPGA.cpp | 1 +
.../c++2/src_simulator/arch/OrderScheduler.cpp | 5 ++++-
simulators/c++2/src_simulator/arch/RRScheduler.cpp | 1 +
simulators/c++2/src_simulator/sim/Simulator.cpp | 13 +++++++++----
5 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/simulators/c++2/src_simulator/app/TMLCommand.cpp b/simulators/c++2/src_simulator/app/TMLCommand.cpp
index bba1d2bf52..7f18b64972 100755
--- a/simulators/c++2/src_simulator/app/TMLCommand.cpp
+++ b/simulators/c++2/src_simulator/app/TMLCommand.cpp
@@ -138,6 +138,7 @@ TMLCommand* TMLCommand::prepare(bool iInit){
if (_progress==0){
#ifdef LISTENERS_ENABLED
NOTIFY_CMD_ENTERED(this);
+ std::cout<<"command is------"<<this->toString()<<std::endl;
#else
#ifdef EXPLO_ENABLED
if (dynamic_cast<IndeterminismSource*>(this)!=0) NOTIFY_CMD_ENTERED(this);
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index 6e27bcfad3..8927966487 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -294,6 +294,7 @@ void FPGA::schedule(){
}
}
+ //if(_nextTransaction!=0) std::cout<<"nextTransaction is~~~~ "<< _nextTransaction->toShortString()<<std::endl;
if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength();
std::cout << "fpga:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
diff --git a/simulators/c++2/src_simulator/arch/OrderScheduler.cpp b/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
index 363386ba5c..b0e11cfce8 100644
--- a/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
@@ -54,7 +54,8 @@ TMLTime OrderScheduler::schedule(TMLTime iEndSchedule){
WorkloadSource *aSourcePast=0, *aSourceFuture=0; //NEW
for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
aTempTrans=(*i)->getNextTransaction(iEndSchedule);
- if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0){
+ if(aTempTrans) std::cout<<"show temp trans"<<aTempTrans->toShortString()<<std::endl;
+ if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0 && aTempTrans->getCommand()->getTask()->getFPGA()){
aRunnableTime=aTempTrans->getRunnableTime();
if (aRunnableTime<=iEndSchedule){
//Past
@@ -81,6 +82,8 @@ TMLTime OrderScheduler::schedule(TMLTime iEndSchedule){
_nextTransaction=aMarkerPast;
_lastSource=aSourcePast; //NEW
}
+ if(_nextTransaction) std::cout<<"order next trans is "<<_nextTransaction->toShortString()<<std::endl;
+ else std::cout<<"order next trans is 0"<<std::endl;
std::cout<<"end order scheduler"<<std::endl;
return 0;
}
diff --git a/simulators/c++2/src_simulator/arch/RRScheduler.cpp b/simulators/c++2/src_simulator/arch/RRScheduler.cpp
index e6a025c019..f1ffdf1bda 100644
--- a/simulators/c++2/src_simulator/arch/RRScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/RRScheduler.cpp
@@ -71,6 +71,7 @@ TMLTime RRScheduler::schedule(TMLTime iEndSchedule){
if (!aSameTaskFound){
//std::cout << _name << ": Second if\n";
for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
+
//std::cout << "Loop\n";
//if (*i!=aScheduledSource)
(*i)->schedule(iEndSchedule);
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index f0221357ad..0706315b7e 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -180,16 +180,16 @@ ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned
}
}
for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
- // for(TaskList::const_iterator j = _simComp->getTaskList().begin(); j != _simComp->getTaskList().end(); j++){
aTrans = (*i)->getTransactions1By1(true);
if (aTrans!=0) aQueue.push(aTrans);
- // }
}
//std::ostringstream aOutp;
while (!aQueue.empty()){
CPU* aCPU;
+ FPGA* aFPGA;
aTopElement = aQueue.top();
aCPU = aTopElement->getCommand()->getTask()->getCPU();
+ aFPGA = aTopElement->getCommand()->getTask()->getFPGA();
aEndState = aTopElement->getStateID();
if (aEndState==0){
aEndState=TMLTransaction::getID();
@@ -209,6 +209,9 @@ ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned
std::cout << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
}
}
+ else if(aFPGA){
+ iAUTFile << "(" << aStartState << "," << "\"i(" << aFPGA->toString() << "_core_" << aTopElement->toShortString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr() << "_Endtime<" << aTopElement->getEndTime() << ">";
+ }
if (aTopElement->getChannel()!=0){
iAUTFile << "__" << aTopElement->getChannel()->toShortString();
std::cout << "__" << aTopElement->getChannel()->toShortString();
@@ -219,6 +222,8 @@ ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned
aQueue.pop();
if(aCPU)
aTrans = aCPU->getTransactions1By1(false);
+ else if(aFPGA)
+ aTrans = aFPGA->getTransactions1By1(false);
if (aTrans!=0) aQueue.push(aTrans);
}
std::cout << "exit graph output\n";
@@ -813,14 +818,14 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
TMLTask* depTask;
SchedulableDevice* deviceLET;
CPU* depCPU;
- FPGA *depFPGA;
+ FPGA* depFPGA;
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: first schedule" << std::endl;
#endif
_simComp->setStopFlag(false,"");
for(TaskList::const_iterator i=_simComp->getTaskList().begin(); i!=_simComp->getTaskList().end();i++){
if ((*i)->getCurrCommand()!=0) (*i)->getCurrCommand()->prepare(true);
- std::cout<<"in prepare"<<std::endl;
+ std::cout<<"in prepare"<< (*i)->toString() << std::endl;
}
#ifdef EBRDD_ENABLED
for(EBRDDList::const_iterator i=_simComp->getEBRDDIterator(false); i!=_simComp->getEBRDDIterator(true);i++){
--
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