diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp b/MPSoC/mutekh/arch/soclib/ldscript.cpp
index 3f826cd44b03f75be2731519fe773338e7addd6b..2ad92939a27e3a9a72714dcd9c1388eaec5dfe9d 100644
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp
+++ b/MPSoC/mutekh/arch/soclib/ldscript.cpp
@@ -73,10 +73,14 @@ MEMORY
     mem_rom (RXAL): ORIGIN = CONFIG_ROM_ADDR, LENGTH = CONFIG_ROM_SIZE
 #endif
     mem_ram (RWAL): ORIGIN = CONFIG_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE
-//ajoute DG provisiore
-//mwmr_ram (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
-//mwmrd_ram (RWAL): ORIGIN = 0xB0200000, LENGTH = 0x00003000
-//19.05. une seule RAMLOCKS en cas de besoin (actually unused)
+//DG 7.9.
+#if defined(MWMR_RAM0_NAME)
+mwmr_ram0 (RWAL): ORIGIN = 0xA0200000, LENGTH = 0x00001000
+#endif
+#if defined(MWMR_RAM1_NAME)
+mwmr_ram1 (RWAL): ORIGIN = 0xA1200000, LENGTH = 0x00001000
+#endif
+
 vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
 
 //ajout CD
diff --git a/src/main/java/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java b/src/main/java/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java
index 965c8c8daaad94a26b3d3132f6c3acda437e1ca6..e7bb5a2b617af1a93b29c5112d1ac8ac57f43169 100755
--- a/src/main/java/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java
+++ b/src/main/java/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java
@@ -1033,6 +1033,26 @@ public class TasksAndMainGenerator {
         mainFile.appendToMainCode("/* Activating randomness */" + CR);
         mainFile.appendToMainCode("initRandom();" + CR);
 
+	/* DG 7.9.2017 additions for use of hardware MWMR controller */
+
+
+	/*void mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
+	  size_t no, const struct mwmr_s* mwmr );*/
+
+	/*uint32_t *fifo_data_in    = (uint32_t*)(base(MWMRd)+0x000); //0x20200000;*/
+	/* uint32_t *lock_in     = (uint32_t*)(base(LOCKS)+0x00);*§
+	/* mwmr_t *p_mwmr_in    = (mwmr_t*)(base(MWMRd)+0x1000);*/
+
+
+/*mwmr_initialize_pointer(p_mwmr_in,    WIDTH, DEPTH, fifo_data_in,    lock_in   );*/
+
+/* mwmr_hw_init(base(MWMR), MWMR_TO_COPROC, 0 , p_mwmr_in);*/
+
+/*for all coproc 
+  uint32_t *fifo =  (uint32_t*) + i*4096;*/
+
+/* end ajoute 7.9. */
+
 	mainFile.appendToMainCode("/* Initializing the main mutex */" + CR);
 	mainFile.appendToMainCode("if (pthread_mutex_init(&__mainMutex, NULL) < 0) { exit(-1);}" + CR + CR);
 
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java b/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java
index 9c55b3fd3a937c958939dbcf5e24f759cb9c4102..42871f9d6a8582d7a46fcef32e4053161948329e 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java
@@ -174,6 +174,16 @@ public class Deployinfo {
 
 	    i++;
 	}
+	//Calculate Adresses of MWMR segments, one for each hardware accellerator
+	i=0;
+
+	for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+	    deployinfo = deployinfo + "#define MWMR_RAM" + i  + "_NAME mwmr_ram" + i + CR; 
+	    deployinfo = deployinfo + "#define MWMR_RAM" + i  + "_ADDR 0xA02" + Integer.toHexString(i*4096) + CR; 
+	    deployinfo = deployinfo + "#define MWMR_RAM" + i  + "_SIZE 0x1000"+ CR;
+	    i++;
+	}
+
 	return deployinfo;	
     }
     
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
index 0d1bcac49188659832e14b5327955ce58e264ba3..871c0b60449c6d65f119965bbd5a17b24dc5eba5 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
@@ -173,18 +173,15 @@ public class MappingTable {
       /* The accelerators themselves are specifies on DIPLODOCUS level */
 
       int hwa_count=0;
-      int MWMRd_SIZE=4096;
-      int MWMR_SIZE=1024;
-      //   int MWMR_BASE=359242137;
-      // int MWMRd_BASE=360919859; 
-      // int MWMR_BASE=3592421376; //0xd62
-      //int MWMRd_BASE=3609198592; //0xd72
-
-       /*  for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {   
-	  mapping += "maptab.add(Segment(\"mwmr"+hwa_count+"\", 0x"+Integer.toHexString(MWMR_BASE+i*1024)+", 0x"+  Integer.toHexString(MWMR_SIZE)+", IntTab("+(l+5+hwa_count)+"), false));" + CR; 	 
+      int MWMR_SIZE=4096;
+      // int MWMR_BASE=0xA0200000;
+      i=0;
+        for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {   
+	    mapping += "maptab.add(Segment(\"mwmr_ram"+hwa_count+"\", 0xA0"+  Integer.toHexString(2097152+MWMR_SIZE*i)+",  0x00001000, IntTab("+(l+5+hwa_count)+"), false));" + CR; 	 
      hwa_count++;
       } 
- hwa_count=0;
+ hwa_count=0; 
+ /*
    for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {
 	  mapping += "maptab.add(Segment(\"mwmr_ram"+hwa_count+"\", 0x"+(Integer.toHexString(MWMRd_BASE+i*4096))+", 0x"+Integer.toHexString(MWMRd_SIZE)+", IntTab("+(l+5+hwa_count)+"), false));" + CR2; 
 	  hwa_count++;   	     
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java b/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
index de2c5fc94e83981c5c259d8637e557a01e34eaad..29a8d45b409a58c974a47189176d2fd7da18d249 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
@@ -90,7 +90,6 @@ public class Platforminfo {
 	for(i=0;i<nb_hwa;i++){
 	    platforminfo+="Uses('caba:my_hwa"+i+"'),"+CR; 
 		}
-	//+"Uses('caba:MyHWA1'),"+CR 
         platforminfo+="Uses('common:elf_file_loader'),"+CR
 	+"Uses('common:plain_file_loader'),"+CR
         +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),"+CR