diff --git a/simulators/c++2/src_simulator/arch/Bus.cpp b/simulators/c++2/src_simulator/arch/Bus.cpp
index bf77be113fb884c08bc293e089f5fd291659aa0b..cdce8b4a006599a30ec56fc091e56212e5c1c5f8 100644
--- a/simulators/c++2/src_simulator/arch/Bus.cpp
+++ b/simulators/c++2/src_simulator/arch/Bus.cpp
@@ -117,7 +117,7 @@ void Bus::calcStartTimeLength(TMLTime iTimeSlice) const{
   TMLTime tmp2  = static_cast<TMLTime>(_nextTransaction->getPenalties());
   TMLTime tmp3 = static_cast<TMLTime>(_nextTransaction->getStartTime());
   //std::cout << "BUS   ------------- tmp1:" << tmp1 << " tmp2:" << tmp2 << " tmp3:" << tmp3 << "\n";
-  if (tmp1 < tmp2) { tmp1 = tmp2;}
+//  if (tmp1 < tmp2) { tmp1 = tmp2;}
   
   
   //_nextTransaction->setStartTime(max(tmp1+tmp2, tmp3));
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index 5a8b58e349299e1ecad1d78fe130ba1493a739cb..760d20e84e23632c9b1a826f3dbb554650443fd4 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -153,7 +153,9 @@ void FPGA::calcStartTimeLength(){
   if (_masterNextTransaction==0){
 #endif  
     _nextTransaction->setLength(max(_nextTransaction->getVirtualLength(),(TMLTime)1));
+#ifdef BUS_ENABLED
   }
+#endif
 }
 
 
@@ -259,12 +261,14 @@ std::cout<<"fpga addTransaction"<<std::endl;
             unsigned int _tempStartTime = _nextTransaction->getStartTime();
             _nextTransaction->setStartTime(_tempStartTime + _reconfigNumber * _reconfigTime);
             _maxEndTime=max(_maxEndTime,_nextTransaction->getEndTime());
+            _transactListReconfig.push_back(_nextTransaction);
         }
         _nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
     } else if(_tempReconfigNumber>0) {
         if(!_nextTransaction->getCommand()->getTask()->getIsFirstTranExecuted()) {
             _nextTransaction->setStartTime(_maxEndTime + _tempReconfigNumber * _reconfigTime);
             _nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
+            _transactListReconfig.push_back(_nextTransaction);
         }
     }
     else{
@@ -395,6 +399,7 @@ void FPGA::reset(){
   SchedulableDevice::reset();
   _scheduler->reset();
   _transactList.clear();
+  if (!_transactListReconfig.empty()) _transactListReconfig.clear();
   _nextTransaction=0;
   _lastTransaction=0;
   _masterNextTransaction=0;
@@ -660,9 +665,17 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
         std::cout<<"in!!"<<_htmlCurrTask->toString()<<std::endl;
         #endif
         TMLTransaction* aCurrTrans = *i;
+        bool reconfigCheck = false;
+        if (!_transactListReconfig.empty()) {
+            std::vector<TMLTransaction*>::iterator it = std::find (_transactListReconfig.begin(), _transactListReconfig.end(), aCurrTrans);
+                if (it != _transactListReconfig.end()) {
+                    reconfigCheck = true;
+                }
+        }
+
         unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
         bool isBlankTooBig = false;
-        std::ostringstream tempString;
+        std::ostringstream tempString, tempReconfigIdle;
         int tempBlanks;
         if(_htmlCurrTask->getEndLastTransaction() >= MIN_RESIZE_THRESHOLD && aBlanks > MIN_RESIZE_TRANS) {
             int newBlanks = 0;
@@ -679,6 +692,11 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
             isBlankTooBig = true;
             changeCssClass = true;
         }
+        if (reconfigCheck) {
+            tempReconfigIdle << "dynamic reconfiguraiton";
+        } else {
+            tempReconfigIdle << "normal";
+        }
         if ( aBlanks >= 0 && (!(aCurrTrans->getCommand()->getActiveDelay()) && aCurrTrans->getCommand()->isDelayTransaction()) ){
             listScale.push_back(aBlanks+1);
             tempString << tempBlanks+1;
@@ -686,21 +704,20 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
                 listScaleTime.push_back(aCurrTrans->getStartTime()+1);
             }
             if (isBlankTooBig){
-                myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
+                myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
             } else {
-                myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time\" class=\"not\"></td>";
+                myfile << "<td colspan=\""<< aBlanks+1 <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\"></td>";
             }
-        }
-        else if ( aBlanks > 0 ){
+        } else if ( aBlanks > 0 ){
             listScale.push_back(aBlanks);
             tempString << tempBlanks;
             if(aCurrTrans->getStartTime() > listScaleTime.back()){
                 listScaleTime.push_back(aCurrTrans->getStartTime());
             }
             if (isBlankTooBig){
-                myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
+                myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\">" << "<- idle " + tempString.str() + " ->" << "</td>";
             } else {
-                myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time\" class=\"not\"></td>";
+                myfile << "<td colspan=\""<< aBlanks <<"\" title=\"idle time " + tempReconfigIdle.str() + "\" class=\"not\"></td>";
             }
         }
 
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index 602f84305d2827a5f8a891f59a8a53699a64fb17..ccfde361a3dac5dd17190b5f683b87c76bf4a6a7 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -199,6 +199,7 @@ protected:
 	unsigned int _reconfigNumber;
 	unsigned int maxScale;
 	TMLTime _maxEndTime;
+	TransactionList _transactListReconfig; // contains the first trans of each tasks when fpga scheduling is enable
 	unsigned int nextCellClassIndex;
  	std::map<TMLTask*, std::string> taskCellClasses;	
 	///State variable for the VCD output
diff --git a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
index 09ec16872d71e9b901fe15f8f188a61a26f33ff7..fc80dd3dea97fb22ffc7651604ab0b58ce357322 100644
--- a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
@@ -172,6 +172,8 @@ void SingleCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
   //std::cout << "starttime=" <<  _nextTransaction->getStartTime() << "\n";
   if ((_nextTransaction->getStartTime()-_endSchedule) >=_timeBeforeIdle){
     _nextTransaction->setIdlePenalty(_changeIdleModeTime);
+  } else {
+    _nextTransaction->setIdlePenalty(0);
   }
 #endif
 }