diff --git a/simulators/c++2/src_simulator/arch/CPU.h b/simulators/c++2/src_simulator/arch/CPU.h
index 5680e735b8033b45706ea81733c2d9f0b1783564..5e4448648d6d7aab6a5aa208de573fde8b70f515 100755
--- a/simulators/c++2/src_simulator/arch/CPU.h
+++ b/simulators/c++2/src_simulator/arch/CPU.h
@@ -72,7 +72,7 @@ public:
 	\param iScheduler Pointer to the scheduler object
 	*/
 	CPU(ID iID, std::string iName, WorkloadSource* iScheduler, unsigned int iAmountOfCore): SchedulableDevice(iID, iName, iScheduler), _lastTransaction(0),
-        amountOfCore(iAmountOfCore)/*,_schedulingNeeded(false)*/{
+        amountOfCore(iAmountOfCore), _coreNumberGraph(0)/*,_schedulingNeeded(false)*/{
 	}
 	///Destructor
 	virtual ~CPU(){
@@ -123,7 +123,8 @@ public:
 	void HW2HTML(std::ofstream& myfile) const;
 	void schedule2HTML(std::ofstream& myfile) const;
 	void schedule2XML(std::ostringstream& glob,std::ofstream& myfile) const;
-	
+	inline void setCoreNumberGraph(unsigned int n){ _coreNumberGraph=n;}
+	inline unsigned int getCoreNumberGraph(){ return _coreNumberGraph;}
 protected:
 	///List of all tasks running on the CPU
 	TaskList _taskList;
@@ -133,6 +134,7 @@ protected:
 	BusMasterList _busMasterList;
 	///Amount of cores
 	unsigned int amountOfCore; 
+	unsigned int _coreNumberGraph;
 	///Dirty flag of the current scheduling decision
 	//bool _schedulingNeeded;
 	
diff --git a/simulators/c++2/src_simulator/definitions.h b/simulators/c++2/src_simulator/definitions.h
index 34d1deb37a4eb87f82eb8ddd09910a3358a4a6f0..2a9880339c6299c394c225cfd85b4c342cc65393 100644
--- a/simulators/c++2/src_simulator/definitions.h
+++ b/simulators/c++2/src_simulator/definitions.h
@@ -86,8 +86,8 @@ using std::max;
 #undef DEBUG_BUS
 #undef DEBUG_SERIALIZE
 
-#define DEBUG_FPGA
-#define DEBUG_SIMULATE
+#undef DEBUG_FPGA
+#undef DEBUG_SIMULATE
 //enables mapping of DIPLODOCUS channels onto buses
 #define BUS_ENABLED
 //cost of a send/wait command
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index 4428c5d4b7457fa7a596dc52b86b1c3a72c04383..f0221357ade8dd36b7e5728af2120b5b5c2d61e5 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -168,28 +168,28 @@ TMLTransaction* Simulator::getTransLowestEndTimeFPGA(SchedulableDevice*& oResult
 
 ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned int& oTransCounter) const{
   std::cout<<"schedule graph aut!"<<std::endl;
-  CPUList::iterator i;
+  // CPUList::iterator i;
   //std::cout << "entry graph output\n";
   GraphTransactionQueue aQueue;
   TMLTransaction* aTrans, *aTopElement;
   ID aStartState=iStartState, aEndState=0;
   for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
-    for(unsigned int j = 0; j < (*i)->getAmoutOfCore(); j++) {
       aTrans = (*i)->getTransactions1By1(true);
-      if (aTrans!=0) aQueue.push(aTrans);
-    }
+      if (aTrans!=0) {
+	aQueue.push(aTrans);
+      }
   }
   for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
-      aTrans = (*i)->getTransactions1By1(true);
-      if (aTrans!=0) aQueue.push(aTrans);
+    //  for(TaskList::const_iterator j = _simComp->getTaskList().begin(); j != _simComp->getTaskList().end(); j++){
+       aTrans = (*i)->getTransactions1By1(true);
+       if (aTrans!=0) aQueue.push(aTrans);
+       //  }
   }
   //std::ostringstream aOutp;
   while (!aQueue.empty()){
     CPU* aCPU;
-    FPGA* aFPGA;
     aTopElement = aQueue.top();
     aCPU = aTopElement->getCommand()->getTask()->getCPU();
-    aFPGA = aTopElement->getCommand()->getTask()->getFPGA();
     aEndState = aTopElement->getStateID();
     if (aEndState==0){
       aEndState=TMLTransaction::getID();
@@ -198,16 +198,17 @@ ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned
     //13 -> 17 [label = "i(CPU0__test1__TMLTask_1__wro__test1__ch<4 ,4>)"];
     oTransCounter++;
     //(20,"i(CPU0__test1__TMLTask_1__wr__test1__ch<4 ,4>)", 24)
-    //std::cout << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
+    //std::cout << "(" << aStartState<< "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
     if(aCPU){
-      if(aCPU->getAmoutOfCore()>1)
-	iAUTFile << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "_core_" << aCPU->getCycleTime() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
-      else 
-	iAUTFile << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
+      if(aCPU->getAmoutOfCore()>1){
+	iAUTFile << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "_core_" << aTopElement->getTransactCoreNumber() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr() << "_Endtime<" << aTopElement->getEndTime() << ">";
+	std::cout << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "_core_" << aTopElement->getTransactCoreNumber() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
+      }
+      else {
+	iAUTFile << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr() << "_Endtime<" << aTopElement->getEndTime() << ">";
+	std::cout << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
+      }
     }
-    else if(aFPGA)
-      iAUTFile << "(" << aStartState << "," << "\"i(" << aFPGA->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
-    // std::cout << "(" << aStartState << "," << "\"i(" << aCPU->toString() << "__" << aTopElement->getCommand()->getTask()->toString() << "__" << aTopElement->getCommand()->getCommandStr();
     if (aTopElement->getChannel()!=0){
       iAUTFile << "__" << aTopElement->getChannel()->toShortString();
       std::cout << "__" << aTopElement->getChannel()->toShortString();
@@ -218,8 +219,6 @@ ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned
     aQueue.pop();
     if(aCPU)
       aTrans = aCPU->getTransactions1By1(false);
-    else if(aFPGA)
-      aTrans = aFPGA->getTransactions1By1(false);
     if (aTrans!=0) aQueue.push(aTrans);
   }
   std::cout << "exit graph output\n";