diff --git a/simulators/c++2/src_simulator/TMLTransaction.cpp b/simulators/c++2/src_simulator/TMLTransaction.cpp
index 14a1066796506633e634d361bc1ae03654f72c8d..9bce0cc66a6c6e2ea22f95d0182495af1a3eee96 100755
--- a/simulators/c++2/src_simulator/TMLTransaction.cpp
+++ b/simulators/c++2/src_simulator/TMLTransaction.cpp
@@ -46,7 +46,11 @@
MemPoolNoDel<TMLTransaction> TMLTransaction::memPool(BLOCK_SIZE_TRANS);
+<<<<<<< HEAD
TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),
+=======
+TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),_transactCoreNumber(0),_transVcdOutputState(END_IDLE_TRANS),
+>>>>>>> simulation_niu
#ifdef PENALTIES_ENABLED
_idlePenalty(0), _taskSwitchingPenalty(0), //, _branchingPenalty(0),
#endif
diff --git a/simulators/c++2/src_simulator/TMLTransaction.h b/simulators/c++2/src_simulator/TMLTransaction.h
index bb82e10398784bfd60dcd476a9e150cbbf2e1244..e47ddce7082703b819f8cf7f93d014fa53815d98 100644
--- a/simulators/c++2/src_simulator/TMLTransaction.h
+++ b/simulators/c++2/src_simulator/TMLTransaction.h
@@ -48,6 +48,13 @@
//class TMLCommand;
class TMLChannel;
+enum vcdTransVisState
+ {
+ END_IDLE_TRANS,
+ END_PENALTY_TRANS,
+ END_TASK_TRANS
+};
+
class TMLTransaction {
public:
///Constructor
@@ -241,6 +248,13 @@ class TMLTransaction {
inline void setStateID(ID iID) {_stateID=iID;}
inline ID getStateID() {return _stateID;}
inline void setTaskID(ID iID) {_taskID=iID;}
+<<<<<<< HEAD
+=======
+ inline unsigned int getTransactCoreNumber() {return _transactCoreNumber;}
+ inline void setTransactCoreNumber(unsigned int num) {_transactCoreNumber=num;}
+ inline void setTransVcdOutPutState(vcdTransVisState n) {_transVcdOutputState=n;}
+ inline vcdTransVisState getTransVcdOutPutState() { return _transVcdOutputState;}
+>>>>>>> simulation_niu
void toXML(std::ostringstream& glob, int deviceID, std::string deviceName) const;
@@ -255,6 +269,13 @@ class TMLTransaction {
TMLLength _virtualLength;
///Pointer to the command the transaction belongs to
TMLCommand* _command;
+<<<<<<< HEAD
+=======
+ ///Core number of the transaction
+ unsigned int _transactCoreNumber;
+ ///State variable for the cpu VCD output
+ vcdTransVisState _transVcdOutputState;
+>>>>>>> simulation_niu
#ifdef PENALTIES_ENABLED
///Idle penalty
TMLTime _idlePenalty;
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index caa144b3352a36326145129efccbe4e68ebfe5a2..370a0df429ba06c0746cc4eddbd1a22ae160f677 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -469,8 +469,9 @@ void MultiCoreCPU::latencies2XML(std::ostringstream& glob, unsigned int id1, uns
-//TMLTime MultiCoreCPU::getNextSignalChange(bool iInit, std::string& oSigChange, bool& oNoMoreTrans){
+
void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
+<<<<<<< HEAD
//new (oSigData) SignalChangeData(RUNNING, aCurrTrans->getStartTimeOperation(), this);
//std::ostringstream outp;
//oNoMoreTrans=false;
@@ -533,6 +534,87 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//oSigChange=outp.str();
//return aCurrTrans->getStartTime();
break;
+=======
+ static bool _end=false;
+ std::cout<<"getNextSignalChangemulticore!!!---------"<<std::endl;
+ for( TransactionList::iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ std::cout<<"transaction core number is "<< (*i)->getTransactCoreNumber()<<std::endl;
+ std::cout<<"cycle time is "<< this->_cycleTime<<std::endl;
+ if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
+ _posTrasactListVCD= i;
+ std::cout<<"bingo!!"<<(*i)->toShortString()<<std::endl;
+ if (iInit){
+ //_posTrasactListVCD= i;
+ _previousTransEndTime=0;
+ (*i)->setTransVcdOutPutState(END_IDLE_TRANS);
+ std::cout<<"init"<<std::endl;
+ if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()!=0){
+ //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
+ //oSigChange=outp.str();
+ new (oSigData) SignalChangeData(END_IDLE_TRANS, 0, this);
+ //return 0
+ return;
+ }
+ }
+ if (_end==true || _posTrasactListVCD == _transactList.end()){
+ //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
+ //oSigChange=outp.str();
+ //oNoMoreTrans=true;
+ //return _previousTransEndTime;
+ std::cout<<"end transact"<<std::endl;
+ new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
+ this->_cycleTime++;
+ _end=false;
+ }else{
+ //_posTrasactListVCD = i;
+ TMLTransaction* aCurrTrans=*_posTrasactListVCD;
+ switch (aCurrTrans->getTransVcdOutPutState()){
+ case END_TASK_TRANS:
+ std::cout<<"END_TASK_CPU"<<std::endl;
+ do{
+ _previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
+ _posTrasactListVCD++;
+ }while (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTimeOperation()==_previousTransEndTime);
+ if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
+ //outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_PENALTY_TRANS);
+ new (oSigData) SignalChangeData(END_PENALTY_TRANS, _previousTransEndTime, this);
+ }else{
+ //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_IDLE_TRANS);
+ //if (_posTrasactListVCD == _transactList.end()) oNoMoreTrans=true;
+ new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
+ _end=true;
+ }
+ //oSigChange=outp.str();
+ //return _previousTransEndTime;
+ // this->_cycleTime++;
+ break;
+ case END_PENALTY_TRANS:
+ std::cout<<"END_PENALTY_CPU"<<std::endl;
+ //outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
+ //oSigChange=outp.str();
+ aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
+ //return aCurrTrans->getStartTimeOperation();
+ new (oSigData) SignalChangeData(END_TASK_TRANS, aCurrTrans->getStartTimeOperation(), this);
+ break;
+ case END_IDLE_TRANS:
+ std::cout<<"END_IDLE_CPU"<<std::endl;
+ if (aCurrTrans->getPenalties()==0){
+ //outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
+ new (oSigData) SignalChangeData(END_TASK_TRANS, aCurrTrans->getStartTime(), this);
+ }else{
+ //outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_PENALTY_TRANS);
+ new (oSigData) SignalChangeData(END_PENALTY_TRANS, aCurrTrans->getStartTime(), this);
+ }
+ //oSigChange=outp.str();
+ //return aCurrTrans->getStartTime();
+ break;
+ }
+ }
+>>>>>>> simulation_niu
}
}
//return 0;
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
index 4e9f7b938f041335b37a82b0731df3c202e9d9be..766bce178eb476ccb9add58a956c64dd86e91f3b 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
@@ -170,7 +170,7 @@ protected:
TMLTime _changeIdleModeTime;
#endif
///State variable for the VCD output
- vcdCPUVisState _vcdOutputState;
+ //vcdCPUVisState _vcdOutputState;
};
#endif
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index 43f3fe4674ad0e2fc30ae504f6572ea7e8548f1e..087b6a0a7921b259f4a601d32c118aaf6b9effab 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -381,7 +381,8 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
if (myfile.is_open()){
//std::cout << "File is open" << std::endl;
SignalChangeQueue aQueue;
- std::string aSigString;
+ SignalChangeQueue aQueueCpu;
+ //std::string aSigString;
//bool aNoMoreTrans;
//TraceableDevice* actDevice;
TMLTime aCurrTime=-1;
@@ -390,7 +391,12 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
myfile << "$date\n" << asctime(aTimeinfo) << "$end\n\n$version\nDaniel's TML simulator\n$end\n\n";
myfile << "$timescale\n5 ns\n$end\n\n$scope module Simulation $end\n";
//std::cout << "Before 1st loop" << std::endl;
+<<<<<<< HEAD
//for (TraceableDeviceList::const_iterator i=_simComp->getVCDIterator(false); i!= _simComp->getVCDIterator(true); ++i){
+=======
+
+ std::cout<<"vcd name of cpu is finished !!!!!"<<std::endl;
+>>>>>>> simulation_niu
for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
//TraceableDevice* a=*i;
// a->streamBenchmarks(std::cout);
@@ -398,6 +404,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
//std::cout << "in 1st loop " << a << std::endl;
//std::cout << "device: " << (*i)->toString() << std::endl;
//myfile << "$var integer 3 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
+<<<<<<< HEAD
myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
//std::cout << "get next signal change" << std::endl;
//aTime = (*i)->getNextSignalChange(true, aSigString, aNoMoreTrans);
@@ -406,12 +413,84 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
aQueue.push(aTopElement);
//std::cout << "push" << std::endl;
//aQueue.push(new SignalChangeData(aSigString, aTime, (aNoMoreTrans)?0:(*i)));
+=======
+ if ((*i)->toShortString().substr(0,3) == "cpu"){
+ for(unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore(); j++) {
+ myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
+ aTopElement = new SignalChangeData();
+ (*i)->getNextSignalChange(true, aTopElement);
+ aQueueCpu.push(aTopElement);
+ }
+ }
+ else{
+ myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
+ aTopElement = new SignalChangeData();
+ (*i)->getNextSignalChange(true, aTopElement);
+ aQueue.push(aTopElement);
+ }
+>>>>>>> simulation_niu
}
myfile << "$var integer 32 clk Clock $end\n";
myfile << "$upscope $end\n$enddefinitions $end\n\n";
+ while (!aQueueCpu.empty()){
+ std::cout<<"this is cpu queue"<<std::endl;
+ while (aNextClockEvent < aTopElement->_time){
+ myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
+ aNextClockEvent+=CLOCK_INC;
+ }
+ if (aCurrTime!=aTopElement->_time){
+ aCurrTime=aTopElement->_time;
+ myfile << "#" << aCurrTime << "\n";
+ }
+ if (aNextClockEvent == aTopElement->_time){
+ myfile << "b" << vcdTimeConvert(aNextClockEvent) << " clk\n";
+ aNextClockEvent+=CLOCK_INC;
+ }
+ //myfile << aTopElement->_sigChange << "\n";
+ myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
+ aQueueCpu.pop();
+ TMLTime aTime = aTopElement->_time;
+ aTopElement->_device->getNextSignalChange(false, aTopElement);
+ std::cout<<"aTime is "<<aTime<<std::endl;
+ std::cout<<"aTopElement time is "<<aTopElement->_time<<std::endl;
+ if (aTopElement->_time == aTime){
+ delete aTopElement;
+ //std::cout<<"delete"<<std::endl;
+ }
+ else{
+ aQueueCpu.push(aTopElement);
+ //std::cout<<"no delete"<<std::endl;
+ }
+
+ }
+ // (dynamic_cast<CPU*>(*i))->setCycleTime( (dynamic_cast<CPU*>(*i))->getCycleTime()+1);
+ // aNextClockEvent=0;
+ // aCurrTime=-1;
+
+
+
+
+ //if sucess, make it as a fonction !!!! change
+ /* for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
+ if ((*i)->toShortString().substr(0,3) == "cpu"){
+ for(unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore(); j++) {
+ (dynamic_cast<CPU*>(*i))->setCycleTime(0);
+ }
+ }
+ }*/
+
+ // myfile << "$var integer 32 clk Clock $end\n";
+ // myfile << "$upscope $end\n$enddefinitions $end\n\n";
//std::cout << "Before 2nd loop" << std::endl;
+ aNextClockEvent=0;
+ aCurrTime=-1;
while (!aQueue.empty()){
aTopElement=aQueue.top();
+<<<<<<< HEAD
+=======
+ std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<<std::endl;
+
+>>>>>>> simulation_niu
while (aNextClockEvent < aTopElement->_time){
myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
aNextClockEvent+=CLOCK_INC;
@@ -428,11 +507,29 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
aQueue.pop();
TMLTime aTime = aTopElement->_time;
+<<<<<<< HEAD
aTopElement->_device->getNextSignalChange(false, aTopElement);
if (aTopElement->_time == aTime)
delete aTopElement;
else
aQueue.push(aTopElement);
+=======
+ std::cout<<"aTime is "<<aTime<<std::endl;
+ //std::cout<<"lets get next signal : )"<<std::endl;
+ //if (aTopElement->_device->toShortString().substr(0,3) == "cpu")
+ // std::cout<<"!!!!!"<<(dynamic_cast<CPU*>(aTopElement->_device))->getCycleTime()<<std::endl;
+
+ aTopElement->_device->getNextSignalChange(false, aTopElement);
+ if (aTopElement->_time == aTime){
+ delete aTopElement;
+ std::cout<<"delete"<<std::endl;
+ }
+ else{
+ aQueue.push(aTopElement);
+ std::cout<<"no delete"<<std::endl;
+ }
+
+>>>>>>> simulation_niu
//actDevice=aTopElement->_device;
//if (actDevice!=0) aTime = actDevice->getNextSignalChange(false, aSigString, aNoMoreTrans);
//delete aTopElement;
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java b/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
index b91a3940a8eabc23fa826b53a34c8c9a42a72a2a..022057015603faa7a7122437ef804ba1e4053a2d 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
@@ -280,8 +280,13 @@ public class TML2MappingSystemC implements IDiploSimulatorCodeGenerator {
//noOfCores=2;
for (int cores = 0; cores < noOfCores; cores++) {
String nodeName = node.getName();
+<<<<<<< HEAD
if ((node instanceof HwCPU) || (node instanceof HwA))
nodeName += cores;
+=======
+ if (node instanceof HwCPU)
+ nodeName += ((HwCPU)node).nbOfCores;
+>>>>>>> simulation_niu
declaration += "BusMaster* " + nodeName + "_" + link.bus.getName() + "_Master = new BusMaster(\"" + nodeName + "_" + link.bus.getName() + "_Master\", " + link.getPriority() + ", " + link.bus.pipelineSize + ", array(" + link.bus.pipelineSize;
for (int i = 0; i < link.bus.pipelineSize; i++)
declaration += ", (SchedulableCommDevice*)" + link.bus.getName() + "_" + i;