From 20edfdac9da11f1b22305238045b6ce70af75efe Mon Sep 17 00:00:00 2001
From: jerray <jawher.jerray@eurecom.fr>
Date: Tue, 25 Jul 2023 15:20:00 +0200
Subject: [PATCH] add new tests for parallel transfers
---
.../DiplodocusSimulatorTest.java | 222 +++++++++---------
.../testParallel-R-R-Transfers.tarchi | 148 ++++++++++++
.../simulator/testParallel-R-R-Transfers.tmap | 32 +++
.../simulator/testParallel-R-R-Transfers.tml | 41 ++++
.../testParallel-W-R-Transfers.tarchi | 140 +++++++++++
.../simulator/testParallel-W-R-Transfers.tmap | 34 +++
.../simulator/testParallel-W-R-Transfers.tml | 41 ++++
...rchi => testParallel-W-W-Transfers.tarchi} | 0
...s.tmap => testParallel-W-W-Transfers.tmap} | 4 +-
...ers.tml => testParallel-W-W-Transfers.tml} | 0
10 files changed, 550 insertions(+), 112 deletions(-)
create mode 100644 ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tarchi
create mode 100644 ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tmap
create mode 100644 ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tml
create mode 100644 ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tarchi
create mode 100644 ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tmap
create mode 100644 ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tml
rename ttool/src/test/resources/tmltranslator/simulator/{testParallelTransfers.tarchi => testParallel-W-W-Transfers.tarchi} (100%)
rename ttool/src/test/resources/tmltranslator/simulator/{testParallelTransfers.tmap => testParallel-W-W-Transfers.tmap} (90%)
rename ttool/src/test/resources/tmltranslator/simulator/{testParallelTransfers.tml => testParallel-W-W-Transfers.tml} (100%)
diff --git a/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java b/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
index 0bd95ec2e9..a50719ba50 100644
--- a/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
+++ b/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
@@ -45,8 +45,8 @@ public class DiplodocusSimulatorTest extends AbstractTest {
// model with paths allowing parallel transfers
private static final String SIM_KEYWORD_TIME_BEG = "Simulated time:";
private static final String SIM_KEYWORD_TIME_END = "time";
- final String MODEL_PARALLEL_TRANSFERS = "testParallelTransfers";
- final String SIMUL_END_TIME = "3";
+ final String[] MODELS_PARALLEL_TRANSFERS = {"testParallel-W-W-Transfers", "testParallel-R-R-Transfers", "testParallel-W-R-Transfers"};
+ final String[] SIMULS_END_TIME = {"3", "3", "3"};
private String SIM_DIR;
@BeforeClass
@@ -604,136 +604,138 @@ public class DiplodocusSimulatorTest extends AbstractTest {
@Test
public void testPathsWithParallelTransfers() throws Exception {
- String s = MODEL_PARALLEL_TRANSFERS;
- SIM_DIR = DIR_GEN + s + "/";
- System.out.println("executing: checking syntax " + s);
+ for (int i = 0; i < MODELS_PARALLEL_TRANSFERS.length; i++) {
+ String s = MODELS_PARALLEL_TRANSFERS[i];
+ SIM_DIR = DIR_GEN + s + "/";
+ System.out.println("executing: checking syntax " + s);
- // Load the TML
- System.out.println("executing: loading " + s);
- TMLMappingTextSpecification tmts = new TMLMappingTextSpecification(s);
- File f = new File(RESOURCES_DIR + s + ".tmap");
- System.out.println("executing: new file loaded " + s);
- String spec = null;
- try {
- spec = FileUtils.loadFileData(f);
- } catch (Exception e) {
- System.out.println("Exception executing: loading " + s);
- assertTrue(false);
- }
- System.out.println("executing: testing spec " + s);
- assertTrue(spec != null);
- System.out.println("executing: testing parsed " + s);
- boolean parsed = tmts.makeTMLMapping(spec, RESOURCES_DIR);
- assertTrue(parsed);
- System.out.println("executing: checking syntax " + s);
+ // Load the TML
+ System.out.println("executing: loading " + s);
+ TMLMappingTextSpecification tmts = new TMLMappingTextSpecification(s);
+ File f = new File(RESOURCES_DIR + s + ".tmap");
+ System.out.println("executing: new file loaded " + s);
+ String spec = null;
+ try {
+ spec = FileUtils.loadFileData(f);
+ } catch (Exception e) {
+ System.out.println("Exception executing: loading " + s);
+ assertTrue(false);
+ }
+ System.out.println("executing: testing spec " + s);
+ assertTrue(spec != null);
+ System.out.println("executing: testing parsed " + s);
+ boolean parsed = tmts.makeTMLMapping(spec, RESOURCES_DIR);
+ assertTrue(parsed);
+ System.out.println("executing: checking syntax " + s);
- // Checking syntax
- TMLMapping tmap = tmts.getTMLMapping();
- TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
- syntax.checkSyntax();
- assertTrue(syntax.hasErrors() == 0);
+ // Checking syntax
+ TMLMapping tmap = tmts.getTMLMapping();
+ TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
+ syntax.checkSyntax();
+ assertTrue(syntax.hasErrors() == 0);
- // Generate C code
- System.out.println("executing: sim code gen for " + s);
- final IDiploSimulatorCodeGenerator tml2systc;
- List<EBRDD> al = new ArrayList<EBRDD>();
- List<TEPE> alTepe = new ArrayList<TEPE>();
- tml2systc = DiploSimulatorFactory.INSTANCE.createCodeGenerator(tmap, al, alTepe);
- tml2systc.setModelName(s);
- String error = tml2systc.generateSystemC(false, true);
- assertTrue(error == null);
- File directory = new File(SIM_DIR);
- if (! directory.exists()){
- directory.mkdirs();
- }
+ // Generate C code
+ System.out.println("executing: sim code gen for " + s);
+ final IDiploSimulatorCodeGenerator tml2systc;
+ List<EBRDD> al = new ArrayList<EBRDD>();
+ List<TEPE> alTepe = new ArrayList<TEPE>();
+ tml2systc = DiploSimulatorFactory.INSTANCE.createCodeGenerator(tmap, al, alTepe);
+ tml2systc.setModelName(s);
+ String error = tml2systc.generateSystemC(false, true);
+ assertTrue(error == null);
+ File directory = new File(SIM_DIR);
+ if (! directory.exists()){
+ directory.mkdirs();
+ }
- // Putting sim files
- System.out.println("SIM executing: sim lib code copying for " + s);
- ConfigurationTTool.SystemCCodeDirectory = getBaseResourcesDir() + "../../../../simulators/c++2/";
- boolean simFiles = SpecConfigTTool.checkAndCreateSystemCDir(SIM_DIR);
- System.out.println("SIM executing: sim lib code copying done with result " + simFiles);
- assertTrue(simFiles);
- System.out.println("SIM Saving file in: " + SIM_DIR);
- tml2systc.saveFile(SIM_DIR, "appmodel");
+ // Putting sim files
+ System.out.println("SIM executing: sim lib code copying for " + s);
+ ConfigurationTTool.SystemCCodeDirectory = getBaseResourcesDir() + "../../../../simulators/c++2/";
+ boolean simFiles = SpecConfigTTool.checkAndCreateSystemCDir(SIM_DIR);
+ System.out.println("SIM executing: sim lib code copying done with result " + simFiles);
+ assertTrue(simFiles);
+ System.out.println("SIM Saving file in: " + SIM_DIR);
+ tml2systc.saveFile(SIM_DIR, "appmodel");
- // Compile it
- System.out.println("executing: compile");
- Process proc;
- BufferedReader proc_in;
- String str;
- boolean mustRecompileAll;
- Penalties penalty = new Penalties(SIM_DIR + File.separator + "src_simulator");
- int changed = penalty.handlePenalties(false);
- if (changed == 1) {
- mustRecompileAll = true;
- } else {
- mustRecompileAll = false;
- }
+ // Compile it
+ System.out.println("executing: compile");
+ Process proc;
+ BufferedReader proc_in;
+ String str;
+ boolean mustRecompileAll;
+ Penalties penalty = new Penalties(SIM_DIR + File.separator + "src_simulator");
+ int changed = penalty.handlePenalties(false);
+ if (changed == 1) {
+ mustRecompileAll = true;
+ } else {
+ mustRecompileAll = false;
+ }
- if (mustRecompileAll) {
- System.out.println("executing: " + "make -C " + SIM_DIR + " clean");
+ if (mustRecompileAll) {
+ System.out.println("executing: " + "make -C " + SIM_DIR + " clean");
+ try {
+ proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + " clean");
+ proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
+ while ((str = proc_in.readLine()) != null) {
+ System.out.println("executing: " + str);
+ }
+ } catch (Exception e) {
+ // probably make is not installed
+ System.out.println("FAILED: executing: " + "make -C " + SIM_DIR + " clean");
+ return;
+ }
+ }
+
+ System.out.println("executing: " + "make -C " + SIM_DIR);
try {
- proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + " clean");
+ proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + "");
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
+ monitorError(proc);
while ((str = proc_in.readLine()) != null) {
System.out.println("executing: " + str);
}
} catch (Exception e) {
- // probably make is not installed
- System.out.println("FAILED: executing: " + "make -C " + SIM_DIR + " clean");
+ // Probably make is not installed
+ System.out.println("FAILED: executing: " + "make -C " + SIM_DIR);
return;
}
- }
-
- System.out.println("executing: " + "make -C " + SIM_DIR);
- try {
- proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + "");
- proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
- monitorError(proc);
- while ((str = proc_in.readLine()) != null) {
- System.out.println("executing: " + str);
- }
- } catch (Exception e) {
- // Probably make is not installed
- System.out.println("FAILED: executing: " + "make -C " + SIM_DIR);
- return;
- }
- System.out.println("SUCCESS: executing: " + "make -C " + SIM_DIR);
+ System.out.println("SUCCESS: executing: " + "make -C " + SIM_DIR);
- // Run the simulator
- String graphPath = SIM_DIR + "testgraph_" + s;
- try {
+ // Run the simulator
+ String graphPath = SIM_DIR + "testgraph_" + s;
+ try {
- String[] params = new String[3];
+ String[] params = new String[3];
- params[0] = "./" + SIM_DIR + "run.x";
- params[1] = "-cmd";
- params[2] = "1 0; 1 7 100 100 " + graphPath;
- proc = Runtime.getRuntime().exec(params);
- //proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
- proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
+ params[0] = "./" + SIM_DIR + "run.x";
+ params[1] = "-cmd";
+ params[2] = "1 0; 1 7 100 100 " + graphPath;
+ proc = Runtime.getRuntime().exec(params);
+ //proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
+ proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
- monitorError(proc);
+ monitorError(proc);
- boolean simulationTime = false;
- while ((str = proc_in.readLine()) != null) {
- System.out.println("executing: " + str);
- if (str.startsWith(SIM_KEYWORD_TIME_BEG)) {
- String str1 = str.substring(SIM_KEYWORD_TIME_BEG.length());
- int index = str1.indexOf(SIM_KEYWORD_TIME_END);
- System.out.println("executing: str1=" + str1);
- if (index != -1) {
- String str2 = str1.substring(0, index).trim();
- System.out.println("executing: str2=" + str2);
- simulationTime = str2.compareTo(SIMUL_END_TIME) == 0;
+ boolean simulationTime = false;
+ while ((str = proc_in.readLine()) != null) {
+ System.out.println("executing: " + str);
+ if (str.startsWith(SIM_KEYWORD_TIME_BEG)) {
+ String str1 = str.substring(SIM_KEYWORD_TIME_BEG.length());
+ int index = str1.indexOf(SIM_KEYWORD_TIME_END);
+ System.out.println("executing: str1=" + str1);
+ if (index != -1) {
+ String str2 = str1.substring(0, index).trim();
+ System.out.println("executing: str2=" + str2);
+ simulationTime = str2.compareTo(SIMULS_END_TIME[i]) == 0;
+ }
}
}
+ assertTrue(simulationTime);
+ } catch (Exception e) {
+ // Probably make is not installed
+ System.out.println("FAILED: executing simulation");
+ return;
}
- assertTrue(simulationTime);
- } catch (Exception e) {
- // Probably make is not installed
- System.out.println("FAILED: executing simulation");
- return;
}
}
}
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tarchi b/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tarchi
new file mode 100644
index 0000000000..47c676b4ba
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tarchi
@@ -0,0 +1,148 @@
+// Master clock frequency - in MHz
+MASTERCLOCKFREQUENCY 200
+
+NODE MEMORY MemoryOrigin2
+SET MemoryOrigin2 byteDataSize 4
+SET MemoryOrigin2 clockDivider 1
+
+NODE CPU CPUDestination2
+SET CPUDestination2 nbOfCores 1
+SET CPUDestination2 byteDataSize 4
+SET CPUDestination2 pipelineSize 5
+SET CPUDestination2 goIdleTime 10
+SET CPUDestination2 maxConsecutiveIdleCycles 10
+SET CPUDestination2 taskSwitchingTime 20
+SET CPUDestination2 branchingPredictionPenalty 2
+SET CPUDestination2 cacheMiss 5
+SET CPUDestination2 schedulingPolicy 0
+SET CPUDestination2 sliceTime 10000
+SET CPUDestination2 execiTime 1
+SET CPUDestination2 execcTime 1
+SET CPUDestination2 clockDivider 1
+
+NODE BRIDGE Bridge1
+SET Bridge1 bufferByteSize 4
+SET Bridge1 clockDivider 1
+
+NODE BUS Bus1
+SET Bus1 byteDataSize 4
+SET Bus1 pipelineSize 1
+SET Bus1 arbitration 0
+SET Bus1 sliceTime 10000
+SET Bus1 burstSize 100
+SET Bus1 privacy private
+SET Bus1 clockDivider 1
+
+NODE MEMORY MemoryOrigin1
+SET MemoryOrigin1 byteDataSize 4
+SET MemoryOrigin1 clockDivider 1
+
+NODE CPU CPUDestination1
+SET CPUDestination1 nbOfCores 1
+SET CPUDestination1 byteDataSize 4
+SET CPUDestination1 pipelineSize 5
+SET CPUDestination1 goIdleTime 10
+SET CPUDestination1 maxConsecutiveIdleCycles 10
+SET CPUDestination1 taskSwitchingTime 20
+SET CPUDestination1 branchingPredictionPenalty 2
+SET CPUDestination1 cacheMiss 5
+SET CPUDestination1 schedulingPolicy 0
+SET CPUDestination1 sliceTime 10000
+SET CPUDestination1 execiTime 1
+SET CPUDestination1 execcTime 1
+SET CPUDestination1 clockDivider 1
+
+NODE CPU CPUOrigin
+SET CPUOrigin nbOfCores 1
+SET CPUOrigin byteDataSize 4
+SET CPUOrigin pipelineSize 5
+SET CPUOrigin goIdleTime 10
+SET CPUOrigin maxConsecutiveIdleCycles 10
+SET CPUOrigin taskSwitchingTime 20
+SET CPUOrigin branchingPredictionPenalty 2
+SET CPUOrigin cacheMiss 5
+SET CPUOrigin schedulingPolicy 0
+SET CPUOrigin sliceTime 10000
+SET CPUOrigin execiTime 1
+SET CPUOrigin execcTime 1
+SET CPUOrigin clockDivider 1
+
+NODE BUS Bus4
+SET Bus4 byteDataSize 4
+SET Bus4 pipelineSize 1
+SET Bus4 arbitration 0
+SET Bus4 sliceTime 10000
+SET Bus4 burstSize 100
+SET Bus4 privacy public
+SET Bus4 clockDivider 1
+
+NODE BUS Bus2
+SET Bus2 byteDataSize 4
+SET Bus2 pipelineSize 1
+SET Bus2 arbitration 0
+SET Bus2 sliceTime 10000
+SET Bus2 burstSize 100
+SET Bus2 privacy public
+SET Bus2 clockDivider 1
+
+NODE BRIDGE Bridge3
+SET Bridge3 bufferByteSize 4
+SET Bridge3 clockDivider 1
+
+NODE BRIDGE Bridge2
+SET Bridge2 bufferByteSize 4
+SET Bridge2 clockDivider 1
+
+NODE BUS Bus3
+SET Bus3 byteDataSize 4
+SET Bus3 pipelineSize 1
+SET Bus3 arbitration 0
+SET Bus3 sliceTime 10000
+SET Bus3 burstSize 100
+SET Bus3 privacy public
+SET Bus3 clockDivider 1
+
+NODE LINK link_MemoryOrigin2_to_Bus3
+SET link_MemoryOrigin2_to_Bus3 node MemoryOrigin2
+SET link_MemoryOrigin2_to_Bus3 bus Bus3
+SET link_MemoryOrigin2_to_Bus3 priority 0
+NODE LINK link_CPUDestination2_to_Bus4
+SET link_CPUDestination2_to_Bus4 node CPUDestination2
+SET link_CPUDestination2_to_Bus4 bus Bus4
+SET link_CPUDestination2_to_Bus4 priority 0
+NODE LINK link_CPUDestination1_to_Bus1
+SET link_CPUDestination1_to_Bus1 node CPUDestination1
+SET link_CPUDestination1_to_Bus1 bus Bus1
+SET link_CPUDestination1_to_Bus1 priority 0
+NODE LINK link_Bridge1_to_Bus1
+SET link_Bridge1_to_Bus1 node Bridge1
+SET link_Bridge1_to_Bus1 bus Bus1
+SET link_Bridge1_to_Bus1 priority 0
+NODE LINK link_Bridge1_to_Bus2
+SET link_Bridge1_to_Bus2 node Bridge1
+SET link_Bridge1_to_Bus2 bus Bus2
+SET link_Bridge1_to_Bus2 priority 0
+NODE LINK link_Bridge3_to_Bus4
+SET link_Bridge3_to_Bus4 node Bridge3
+SET link_Bridge3_to_Bus4 bus Bus4
+SET link_Bridge3_to_Bus4 priority 0
+NODE LINK link_CPUOrigin_to_Bus1
+SET link_CPUOrigin_to_Bus1 node CPUOrigin
+SET link_CPUOrigin_to_Bus1 bus Bus1
+SET link_CPUOrigin_to_Bus1 priority 0
+NODE LINK link_Bridge2_to_Bus2
+SET link_Bridge2_to_Bus2 node Bridge2
+SET link_Bridge2_to_Bus2 bus Bus2
+SET link_Bridge2_to_Bus2 priority 0
+NODE LINK link_MemoryOrigin1_to_Bus2
+SET link_MemoryOrigin1_to_Bus2 node MemoryOrigin1
+SET link_MemoryOrigin1_to_Bus2 bus Bus2
+SET link_MemoryOrigin1_to_Bus2 priority 0
+NODE LINK link_Bridge3_to_Bus3
+SET link_Bridge3_to_Bus3 node Bridge3
+SET link_Bridge3_to_Bus3 bus Bus3
+SET link_Bridge3_to_Bus3 priority 0
+NODE LINK link_Bridge2_to_Bus3
+SET link_Bridge2_to_Bus3 node Bridge2
+SET link_Bridge2_to_Bus3 bus Bus3
+SET link_Bridge2_to_Bus3 priority 0
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tmap b/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tmap
new file mode 100644
index 0000000000..214ac12949
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tmap
@@ -0,0 +1,32 @@
+TMLSPEC
+ #include "testParallel-R-R-Transfers.tml"
+ENDTMLSPEC
+
+TMLARCHI
+ #include "testParallel-R-R-Transfers.tarchi"
+ENDTMLARCHI
+
+TMLMAPPING
+ MAP CPUDestination2 Application__Destination2
+ SET Application__Destination2 priority 0
+ MAP CPUDestination1 Application__Destination1
+ SET Application__Destination1 priority 0
+ MAP CPUOrigin Application__Origin
+ SET Application__Origin priority 0
+ MAP MemoryOrigin2 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus1 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus2 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus3 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus4 Application__comm2
+ SET Application__comm2 priority 0
+ MAP MemoryOrigin1 Application__comm1
+ SET Application__comm1 priority 0
+ MAP Bus1 Application__comm1
+ SET Application__comm1 priority 0
+ MAP Bus2 Application__comm1
+ SET Application__comm1 priority 0
+ENDTMLMAPPING
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tml b/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tml
new file mode 100644
index 0000000000..a2d37e4e84
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-R-R-Transfers.tml
@@ -0,0 +1,41 @@
+// TML Application - FORMAT 0.2
+// Application: /home/jawher/Jawher/Huawei-MDE/models/testParalR-R.xml
+// Generated: Tue Jul 25 12:48:24 CEST 2023
+
+// PRAGMAS
+
+// Channels
+CHANNEL Application__comm1 BRBW 4 8 OUT Application__Origin IN Application__Destination1
+VCCHANNEL Application__comm1 0
+CHANNEL Application__comm2 BRBW 4 8 OUT Application__Origin IN Application__Destination2
+VCCHANNEL Application__comm2 0
+
+// Events
+
+// Requests
+
+TASK Application__Destination1
+ TASKOP
+ //Local variables
+
+ //Behavior
+ READ Application__comm1 1
+ENDTASK
+
+TASK Application__Destination2
+ TASKOP
+ //Local variables
+
+ //Behavior
+ READ Application__comm2 1
+ENDTASK
+
+TASK Application__Origin
+ TASKOP
+ //Local variables
+
+ //Behavior
+ WRITE Application__comm1 1
+ WRITE Application__comm2 1
+ENDTASK
+
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tarchi b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tarchi
new file mode 100644
index 0000000000..ebef4dff42
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tarchi
@@ -0,0 +1,140 @@
+// Master clock frequency - in MHz
+MASTERCLOCKFREQUENCY 200
+
+NODE MEMORY MemoryOrigin2
+SET MemoryOrigin2 byteDataSize 4
+SET MemoryOrigin2 clockDivider 1
+
+NODE CPU CPUOrigin2
+SET CPUOrigin2 nbOfCores 1
+SET CPUOrigin2 byteDataSize 4
+SET CPUOrigin2 pipelineSize 5
+SET CPUOrigin2 goIdleTime 10
+SET CPUOrigin2 maxConsecutiveIdleCycles 10
+SET CPUOrigin2 taskSwitchingTime 20
+SET CPUOrigin2 branchingPredictionPenalty 2
+SET CPUOrigin2 cacheMiss 5
+SET CPUOrigin2 schedulingPolicy 0
+SET CPUOrigin2 sliceTime 10000
+SET CPUOrigin2 execiTime 1
+SET CPUOrigin2 execcTime 1
+SET CPUOrigin2 clockDivider 1
+
+NODE BRIDGE Bridge1
+SET Bridge1 bufferByteSize 4
+SET Bridge1 clockDivider 1
+
+NODE BUS Bus1
+SET Bus1 byteDataSize 4
+SET Bus1 pipelineSize 1
+SET Bus1 arbitration 0
+SET Bus1 sliceTime 10000
+SET Bus1 burstSize 100
+SET Bus1 privacy private
+SET Bus1 clockDivider 1
+
+NODE MEMORY MemoryOrigin1
+SET MemoryOrigin1 byteDataSize 4
+SET MemoryOrigin1 clockDivider 1
+
+NODE CPU CPUDestination
+SET CPUDestination nbOfCores 1
+SET CPUDestination byteDataSize 4
+SET CPUDestination pipelineSize 5
+SET CPUDestination goIdleTime 10
+SET CPUDestination maxConsecutiveIdleCycles 10
+SET CPUDestination taskSwitchingTime 20
+SET CPUDestination branchingPredictionPenalty 2
+SET CPUDestination cacheMiss 5
+SET CPUDestination schedulingPolicy 0
+SET CPUDestination sliceTime 10000
+SET CPUDestination execiTime 1
+SET CPUDestination execcTime 1
+SET CPUDestination clockDivider 1
+
+NODE CPU CPUOrigin1
+SET CPUOrigin1 nbOfCores 1
+SET CPUOrigin1 byteDataSize 4
+SET CPUOrigin1 pipelineSize 5
+SET CPUOrigin1 goIdleTime 10
+SET CPUOrigin1 maxConsecutiveIdleCycles 10
+SET CPUOrigin1 taskSwitchingTime 20
+SET CPUOrigin1 branchingPredictionPenalty 2
+SET CPUOrigin1 cacheMiss 5
+SET CPUOrigin1 schedulingPolicy 0
+SET CPUOrigin1 sliceTime 10000
+SET CPUOrigin1 execiTime 1
+SET CPUOrigin1 execcTime 1
+SET CPUOrigin1 clockDivider 1
+
+NODE BUS Bus4
+SET Bus4 byteDataSize 4
+SET Bus4 pipelineSize 1
+SET Bus4 arbitration 0
+SET Bus4 sliceTime 10000
+SET Bus4 burstSize 100
+SET Bus4 privacy public
+SET Bus4 clockDivider 1
+
+NODE BUS Bus2
+SET Bus2 byteDataSize 4
+SET Bus2 pipelineSize 1
+SET Bus2 arbitration 0
+SET Bus2 sliceTime 10000
+SET Bus2 burstSize 100
+SET Bus2 privacy public
+SET Bus2 clockDivider 1
+
+NODE BRIDGE Bridge2
+SET Bridge2 bufferByteSize 4
+SET Bridge2 clockDivider 1
+
+NODE BUS Bus3
+SET Bus3 byteDataSize 4
+SET Bus3 pipelineSize 1
+SET Bus3 arbitration 0
+SET Bus3 sliceTime 10000
+SET Bus3 burstSize 100
+SET Bus3 privacy public
+SET Bus3 clockDivider 1
+
+NODE LINK link_MemoryOrigin2_to_Bus4
+SET link_MemoryOrigin2_to_Bus4 node MemoryOrigin2
+SET link_MemoryOrigin2_to_Bus4 bus Bus4
+SET link_MemoryOrigin2_to_Bus4 priority 0
+NODE LINK link_CPUOrigin2_to_Bus1
+SET link_CPUOrigin2_to_Bus1 node CPUOrigin2
+SET link_CPUOrigin2_to_Bus1 bus Bus1
+SET link_CPUOrigin2_to_Bus1 priority 0
+NODE LINK link_CPUDestination_to_Bus3
+SET link_CPUDestination_to_Bus3 node CPUDestination
+SET link_CPUDestination_to_Bus3 bus Bus3
+SET link_CPUDestination_to_Bus3 priority 0
+NODE LINK link_Bridge1_to_Bus1
+SET link_Bridge1_to_Bus1 node Bridge1
+SET link_Bridge1_to_Bus1 bus Bus1
+SET link_Bridge1_to_Bus1 priority 0
+NODE LINK link_Bridge1_to_Bus2
+SET link_Bridge1_to_Bus2 node Bridge1
+SET link_Bridge1_to_Bus2 bus Bus2
+SET link_Bridge1_to_Bus2 priority 0
+NODE LINK link_Bridge1_to_Bus4
+SET link_Bridge1_to_Bus4 node Bridge1
+SET link_Bridge1_to_Bus4 bus Bus4
+SET link_Bridge1_to_Bus4 priority 0
+NODE LINK link_CPUOrigin1_to_Bus1
+SET link_CPUOrigin1_to_Bus1 node CPUOrigin1
+SET link_CPUOrigin1_to_Bus1 bus Bus1
+SET link_CPUOrigin1_to_Bus1 priority 0
+NODE LINK link_Bridge2_to_Bus4
+SET link_Bridge2_to_Bus4 node Bridge2
+SET link_Bridge2_to_Bus4 bus Bus4
+SET link_Bridge2_to_Bus4 priority 0
+NODE LINK link_MemoryOrigin1_to_Bus2
+SET link_MemoryOrigin1_to_Bus2 node MemoryOrigin1
+SET link_MemoryOrigin1_to_Bus2 bus Bus2
+SET link_MemoryOrigin1_to_Bus2 priority 0
+NODE LINK link_Bridge2_to_Bus3
+SET link_Bridge2_to_Bus3 node Bridge2
+SET link_Bridge2_to_Bus3 bus Bus3
+SET link_Bridge2_to_Bus3 priority 0
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tmap b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tmap
new file mode 100644
index 0000000000..44ab41da6c
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tmap
@@ -0,0 +1,34 @@
+TMLSPEC
+ #include "testParallel-W-R-Transfers.tml"
+ENDTMLSPEC
+
+TMLARCHI
+ #include "testParallel-W-R-Transfers.tarchi"
+ENDTMLARCHI
+
+TMLMAPPING
+ MAP CPUOrigin2 Application__Origin2
+ SET Application__Origin2 priority 0
+ MAP CPUDestination Application__Destination
+ SET Application__Destination priority 0
+ MAP CPUOrigin1 Application__Origin1
+ SET Application__Origin1 priority 0
+ MAP MemoryOrigin2 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus3 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus4 Application__comm2
+ SET Application__comm2 priority 0
+ MAP Bus1 Application__comm2
+ SET Application__comm2 priority 0
+ MAP MemoryOrigin1 Application__comm1
+ SET Application__comm1 priority 0
+ MAP Bus1 Application__comm1
+ SET Application__comm1 priority 0
+ MAP Bus2 Application__comm1
+ SET Application__comm1 priority 0
+ MAP Bus3 Application__comm1
+ SET Application__comm1 priority 0
+ MAP Bus4 Application__comm1
+ SET Application__comm1 priority 0
+ENDTMLMAPPING
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tml b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tml
new file mode 100644
index 0000000000..b9944c59e7
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-R-Transfers.tml
@@ -0,0 +1,41 @@
+// TML Application - FORMAT 0.2
+// Application: /home/jawher/Jawher/Huawei-MDE/models/testParalW-R.xml
+// Generated: Tue Jul 25 12:50:42 CEST 2023
+
+// PRAGMAS
+
+// Channels
+CHANNEL Application__comm1 BRBW 4 8 OUT Application__Origin1 IN Application__Destination
+VCCHANNEL Application__comm1 0
+CHANNEL Application__comm2 BRBW 4 8 OUT Application__Origin2 IN Application__Destination
+VCCHANNEL Application__comm2 0
+
+// Events
+
+// Requests
+
+TASK Application__Destination
+ TASKOP
+ //Local variables
+
+ //Behavior
+ READ Application__comm2 1
+ READ Application__comm1 1
+ENDTASK
+
+TASK Application__Origin1
+ TASKOP
+ //Local variables
+
+ //Behavior
+ WRITE Application__comm1 1
+ENDTASK
+
+TASK Application__Origin2
+ TASKOP
+ //Local variables
+
+ //Behavior
+ WRITE Application__comm2 1
+ENDTASK
+
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tarchi b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tarchi
similarity index 100%
rename from ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tarchi
rename to ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tarchi
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tmap b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tmap
similarity index 90%
rename from ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tmap
rename to ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tmap
index b1cf6c24b2..7da83451a4 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tmap
+++ b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tmap
@@ -1,9 +1,9 @@
TMLSPEC
- #include "testParallelTransfers.tml"
+ #include "testParallel-W-W-Transfers.tml"
ENDTMLSPEC
TMLARCHI
- #include "testParallelTransfers.tarchi"
+ #include "testParallel-W-W-Transfers.tarchi"
ENDTMLARCHI
TMLMAPPING
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tml b/ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tml
similarity index 100%
rename from ttool/src/test/resources/tmltranslator/simulator/testParallelTransfers.tml
rename to ttool/src/test/resources/tmltranslator/simulator/testParallel-W-W-Transfers.tml
--
GitLab