diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp index fb846bc63225cc20d63e6366c0a9ae3a05c9cd0c..64d050acf5bf37cd5ec25920d61edcda25d900fa 100644 --- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp +++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp @@ -344,17 +344,42 @@ std::cout<<"addTransaction"<<_name<<std::endl; // unsigned int iCoreNumber=getCoreNumber(); static unsigned int time=0; // std::cout<<"multicore number "<<coreNumber<<" end schedule "<<_endSchedule<<std::endl; - multiCore[coreNumber]=_endSchedule; +// multiCore[coreNumber]=_endSchedule; // std::cout<<"cycle time is "<<_cycleTime<<std::endl; if (time < amountOfCore -1){ - _endSchedule=0; - _nextTransaction->setTransactCoreNumber(coreNumber); - ++coreNumber; +// _endSchedule=0; + // check if lasttrans = idle Delay and current trans has the same task=> not change core, after that update the multicore mapping + if ((_nextTransaction != NULL && _lastTransaction != NULL && !(_lastTransaction->getCommand()->getActiveDelay()) && _lastTransaction->getCommand()->isDelayTransaction())) { + if (_nextTransaction->getCommand()->getTask() == _lastTransaction->getCommand()->getTask()) { + _nextTransaction->setTransactCoreNumber(_lastTransaction->getTransactCoreNumber()); + multiCore[_lastTransaction->getTransactCoreNumber()] = _endSchedule; + } else { + _nextTransaction->setTransactCoreNumber(coreNumber); + multiCore[coreNumber] = _endSchedule; + } + } else if (_nextTransaction != NULL) { + _nextTransaction->setTransactCoreNumber(coreNumber); + multiCore[coreNumber] = _endSchedule; + } + + ++coreNumber; - }else { - _nextTransaction->setTransactCoreNumber(coreNumber); - _endSchedule=getMinEndSchedule(); - + } else { + // check if lasttrans = idle Delay and current trans has the same task=> not change core, after that update the multicore mapping + if ((_nextTransaction != NULL && _lastTransaction != NULL && !(_lastTransaction->getCommand()->getActiveDelay()) && _lastTransaction->getCommand()->isDelayTransaction())) { + if (_nextTransaction->getCommand()->getTask() == _lastTransaction->getCommand()->getTask()) { + _nextTransaction->setTransactCoreNumber(_lastTransaction->getTransactCoreNumber()); + multiCore[_lastTransaction->getTransactCoreNumber()] = _endSchedule; + } else { + _nextTransaction->setTransactCoreNumber(coreNumber); + multiCore[coreNumber] = _endSchedule; + } + } else if (_nextTransaction != NULL) { + _nextTransaction->setTransactCoreNumber(coreNumber); + multiCore[coreNumber] = _endSchedule; + } + + _endSchedule = getMinEndSchedule(); } time++; if(!(_nextTransaction->getCommand()->getTask()->getIsDaemon()==true && _nextTransaction->getCommand()->getTask()->getNextTransaction(0)==0)) diff --git a/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java b/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java index db7762f0f93cd2a17b6d441b4c563b9fac185dab..1aa3e682291b024f408a0cb35cc0da4c777109a0 100644 --- a/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java +++ b/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java @@ -40,8 +40,8 @@ public class DiplodocusDelayTest extends AbstractUITest { //model for Delay task with penalties final int [] NB_Of_DELAY_STATES_PENALTIES = {42, 42, 42, 42, 32, 32}; final int [] NB_Of_DELAY_TRANSTIONS_PENALTIES = {41, 41, 41, 41, 31, 31}; - final int [] MIN_DELAY_CYCLES_PENALTIES = {2590, 2590, 2670, 2670, 2010, 2340}; - final int [] MAX_DELAY_CYCLES_PENALTIES = {2590, 2590, 2670, 2670, 2010, 2340}; + final int [] MIN_DELAY_CYCLES_PENALTIES = {2590, 2590, 2660, 2660, 2010, 2340}; + final int [] MAX_DELAY_CYCLES_PENALTIES = {2590, 2590, 2660, 2660, 2010, 2340}; // test for read and write active delay parameter final String [] MODELS_DELAY_READ_WRITE = {"delayRW"}; final static String EXPECTED_FILE1 = getBaseResourcesDir() + "tmltranslator/expected/expected_specdelay_readwrite.tml"; diff --git a/ttool/src/test/java/tmltranslator/HTMLParseTest.java b/ttool/src/test/java/tmltranslator/HTMLParseTest.java index 256f3233bb8f98fc5e152bd2bb442b2e4e2cd11b..f540f3003ad8c6072fd39d8666c4135f947e677d 100644 --- a/ttool/src/test/java/tmltranslator/HTMLParseTest.java +++ b/ttool/src/test/java/tmltranslator/HTMLParseTest.java @@ -33,7 +33,7 @@ public class HTMLParseTest extends AbstractUITest { final String [] MODELS_PARSE_HTML = {"parseFPGA_HTML", "parseCPU1_HTML","parseCPU2_HTML"}; final String [] PARSE_FPGA = {"<- idle 471 ->","", "", "", ""}; final String [] PARSE_SINGLE_CORE = {"<- idle 366 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->"}; - final String [] PARSE_MULTI_CORE = { "", "", "<- idle 374 ->", "<- idle 401 ->", "<- idle 401 ->"}; + final String [] PARSE_MULTI_CORE = { "", "", "<- idle 376 ->", "<- idle 807 ->", "<- idle 807 ->"}; final static String EXPECTED_FILE_GET_ALL_TRANS = getBaseResourcesDir() + "tmltranslator/expected/expected_get_all_transactions.txt"; private String SIM_DIR; @BeforeClass diff --git a/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java b/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java new file mode 100644 index 0000000000000000000000000000000000000000..593e9ce61c6d0288faa9473aa7f50abf70f6de5f --- /dev/null +++ b/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java @@ -0,0 +1,202 @@ +package tmltranslator; + +import common.ConfigurationTTool; +import common.SpecConfigTTool; +import graph.AUTGraph; +import myutil.FileUtils; +import org.junit.Before; +import org.junit.BeforeClass; +import org.junit.Test; +import req.ebrdd.EBRDD; +import tepe.TEPE; +import tmltranslator.tomappingsystemc2.DiploSimulatorFactory; +import tmltranslator.tomappingsystemc2.IDiploSimulatorCodeGenerator; +import tmltranslator.tomappingsystemc2.Penalties; +import ui.AbstractUITest; +import ui.TDiagramPanel; +import ui.TMLArchiPanel; +import ui.tmldd.TMLArchiDiagramPanel; + +import java.io.BufferedReader; +import java.io.File; +import java.io.InputStreamReader; +import java.util.ArrayList; +import java.util.List; + +import static org.junit.Assert.assertTrue; + +public class MulticoreCrossCpuSchedulingTest extends AbstractUITest { + final String DIR_GEN = "test_diplo_simulator/"; + final String [] MODELS_CPU_CROSS = {"crossCpuScheduling"}; + private String SIM_DIR; + final int [] NB_OF_CS_STATES = {29}; + final int [] NB_OF_CS_TRANSTIONS = {28}; + final int [] MIN_CS_CYCLES = {42}; + final int [] MAX_CS_CYCLES = {42}; + static String CPP_DIR = "../../../../simulators/c++2/"; + static String mappingName = "Architecture"; + private TMLArchiDiagramPanel currTdp; + + @BeforeClass + public static void setUpBeforeClass() throws Exception { + RESOURCES_DIR = getBaseResourcesDir() + "/tmltranslator/simulator/"; + } + + public MulticoreCrossCpuSchedulingTest() { + super(); + } + + @Before + public void setUp() throws Exception { + SIM_DIR = getBaseResourcesDir() + CPP_DIR; + } + + @Test(timeout = 600000) + public void testMulticoreNotHangingWhenSaveTrace() throws Exception { + for (int i = 0; i < MODELS_CPU_CROSS.length; i++) { + String s = MODELS_CPU_CROSS[i]; + SIM_DIR = DIR_GEN + s + "/"; + System.out.println("executing: checking syntax " + s); + // select architecture tab + mainGUI.openProjectFromFile(new File(RESOURCES_DIR + s + ".xml")); + TMLArchiPanel _tab = findArchiPanel(mappingName); + for (TDiagramPanel tdp : _tab.getPanels()) { + if (tdp instanceof TMLArchiDiagramPanel) { + mainGUI.selectTab(tdp); + currTdp = (TMLArchiDiagramPanel) tdp; + break; + } + } + + mainGUI.checkModelingSyntax(true); + TMLMapping tmap = mainGUI.gtm.getTMLMapping(); + TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap); + syntax.checkSyntax(); + assertTrue(syntax.hasErrors() == 0); + // Generate SystemC code + System.out.println("executing: sim code gen for " + s); + final IDiploSimulatorCodeGenerator tml2systc; + List<EBRDD> al = new ArrayList<EBRDD>(); + List<TEPE> alTepe = new ArrayList<TEPE>(); + tml2systc = DiploSimulatorFactory.INSTANCE.createCodeGenerator(tmap, al, alTepe); + tml2systc.setModelName(s); + String error = tml2systc.generateSystemC(false, true); + assertTrue(error == null); + + File directory = new File(SIM_DIR); + if (!directory.exists()) { + directory.mkdirs(); + } + + // Putting sim files + System.out.println("SIM executing: sim lib code copying for " + s); + ConfigurationTTool.SystemCCodeDirectory = getBaseResourcesDir() + CPP_DIR; + boolean simFiles = SpecConfigTTool.checkAndCreateSystemCDir(SIM_DIR); + + System.out.println("SIM executing: sim lib code copying done with result " + simFiles); + assertTrue(simFiles); + + System.out.println("SIM Saving file in: " + SIM_DIR); + tml2systc.saveFile(SIM_DIR, "appmodel"); + + // Compile it + System.out.println("executing: compile"); + Process proc; + BufferedReader proc_in; + String str; + boolean mustRecompileAll; + Penalties penalty = new Penalties(SIM_DIR + "src_simulator"); + int changed = penalty.handlePenalties(false); + + if (changed == 1) { + mustRecompileAll = true; + } else { + mustRecompileAll = false; + } + + if (mustRecompileAll) { + System.out.println("executing: " + "make -C " + SIM_DIR + " clean"); + try { + proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + " clean"); + proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream())); + while ((str = proc_in.readLine()) != null) { + // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." ); + System.out.println("executing: " + str); + } + } catch (Exception e) { + // probably make is not installed + System.out.println("FAILED: executing: " + "make -C " + SIM_DIR + " clean"); + return; + } + } + + System.out.println("executing: " + "make -C " + SIM_DIR); + try { + proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + ""); + proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream())); + + monitorError(proc); + + while ((str = proc_in.readLine()) != null) { + // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." ); + System.out.println("executing: " + str); + } + } catch (Exception e) { + // Probably make is not installed + System.out.println("FAILED: executing: " + "make -C " + SIM_DIR); + return; + } + + System.out.println("SUCCESS: executing: " + "make -C " + SIM_DIR); + + String graphPath = SIM_DIR + "testgraph_" + s; + try { + + String[] params = new String[3]; + + params[0] = "./" + SIM_DIR + "run.x"; + params[1] = "-cmd"; + params[2] = "1 6 10; 1 7 100 100 " + graphPath; + proc = Runtime.getRuntime().exec(params); + proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream())); + + monitorError(proc); + + while ((str = proc_in.readLine()) != null) { + // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." ); + System.out.println("executing: " + str); + } + } catch (Exception e) { + // Probably make is not installed + System.out.println("FAILED: executing simulation " + e.getCause()); + return; + } + + File graphFile = new File(graphPath + ".aut"); + String graphData = ""; + try { + graphData = FileUtils.loadFileData(graphFile); + } catch (Exception e) { + assertTrue(false); + } + + AUTGraph graph = new AUTGraph(); + graph.buildGraph(graphData); + + // States and transitions + System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates()); + assertTrue(NB_OF_CS_STATES[i] == graph.getNbOfStates()); + System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions()); + assertTrue(NB_OF_CS_TRANSTIONS[i] == graph.getNbOfTransitions()); + + // Min and max cycles + int minValue = graph.getMinValue("allCPUsFPGAsTerminated"); + System.out.println("executing: minvalue of " + s + " " + minValue); + assertTrue(MIN_CS_CYCLES[i] == minValue); + + int maxValue = graph.getMaxValue("allCPUsFPGAsTerminated"); + System.out.println("executing: maxvalue of " + s + " " + maxValue); + assertTrue(MAX_CS_CYCLES[i] == maxValue); + } + } +} diff --git a/ttool/src/test/resources/tmltranslator/simulator/crossCpuScheduling.xml b/ttool/src/test/resources/tmltranslator/simulator/crossCpuScheduling.xml new file mode 100644 index 0000000000000000000000000000000000000000..2939fb52a7014d903c3f5c7818aaf38c7e61ee69 --- /dev/null +++ b/ttool/src/test/resources/tmltranslator/simulator/crossCpuScheduling.xml @@ -0,0 +1,727 @@ +<?xml version="1.0" encoding="UTF-8"?> + +<TURTLEGMODELING version="1.0beta" ANIMATE_INTERACTIVE_SIMULATION="false" ACTIVATE_PENALTIES="false" UPDATE_INFORMATION_DIPLO_SIM="false" ANIMATE_WITH_INFO_DIPLO_SIM="true" OPEN_DIAG_DIPLO_SIM="false" LAST_SELECTED_MAIN_TAB="1" LAST_SELECTED_SUB_TAB="0"> + +<Modeling type="TML Component Design" nameTab="TestCycleEvt_wait" tabs="TML Component Task Diagram$C1$C0$C_START" > +<TMLComponentTaskDiagramPanel name="TML Component Task Diagram" minX="10" maxX="2500" minY="10" maxY="1500" channels="true" events="true" requests="true" zoom="1.0" > +<CONNECTOR type="126" id="1" > +<cdparam x="315" y="207" /> +<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<infoparam name="connector" value="Connector between ports" /> +<P1 x="315" y="211" id="25" /> +<P2 x="242" y="199" id="3" /> +<AutomaticDrawing data="true" /> +</CONNECTOR> +<CONNECTOR type="126" id="2" > +<cdparam x="442" y="295" /> +<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<infoparam name="connector" value="Connector between ports" /> +<P1 x="541" y="231" id="27" /> +<P2 x="613" y="277" id="14" /> +<AutomaticDrawing data="true" /> +</CONNECTOR> +<COMPONENT type="1202" id="13" > +<cdparam x="29" y="101" /> +<sizeparam width="200" height="150" minWidth="150" minHeight="100" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" /> +<infoparam name="Primitive component" value="C_START" /> +<TGConnectingPoint num="0" id="5" /> +<TGConnectingPoint num="1" id="6" /> +<TGConnectingPoint num="2" id="7" /> +<TGConnectingPoint num="3" id="8" /> +<TGConnectingPoint num="4" id="9" /> +<TGConnectingPoint num="5" id="10" /> +<TGConnectingPoint num="6" id="11" /> +<TGConnectingPoint num="7" id="12" /> +<extraparam> +<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ms" Operation="" /> +<Attribute access="2" id="x" value="0" type="0" typeOther="" /> +</extraparam> +</COMPONENT> +<SUBCOMPONENT type="1203" id="4" > +<father id="13" num="0" /> +<cdparam x="216" y="186" /> +<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" /> +<infoparam name="Primitive port" value="Event start_evt" /> +<TGConnectingPoint num="0" id="3" /> +<extraparam> +<Prop commName="start_evt" commType="1" origin="true" finite="true" blocking="false" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="0" /> +<Type type="1" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +</extraparam> +</SUBCOMPONENT> + +<COMPONENT type="1202" id="24" > +<cdparam x="626" y="195" /> +<sizeparam width="200" height="150" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" /> +<infoparam name="Primitive component" value="C1" /> +<TGConnectingPoint num="0" id="16" /> +<TGConnectingPoint num="1" id="17" /> +<TGConnectingPoint num="2" id="18" /> +<TGConnectingPoint num="3" id="19" /> +<TGConnectingPoint num="4" id="20" /> +<TGConnectingPoint num="5" id="21" /> +<TGConnectingPoint num="6" id="22" /> +<TGConnectingPoint num="7" id="23" /> +<extraparam> +<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="" Operation="" /> +<Attribute access="2" id="x" value="" type="0" typeOther="" /> +</extraparam> +</COMPONENT> +<SUBCOMPONENT type="1203" id="15" > +<father id="24" num="0" /> +<cdparam x="613" y="264" /> +<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" /> +<infoparam name="Primitive port" value="Event evt" /> +<TGConnectingPoint num="0" id="14" /> +<extraparam> +<Prop commName="evt" commType="1" origin="false" finite="false" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="0" /> +<Type type="1" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +</extraparam> +</SUBCOMPONENT> + +<COMPONENT type="1202" id="37" > +<cdparam x="328" y="131" /> +<sizeparam width="200" height="150" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" /> +<infoparam name="Primitive component" value="C0" /> +<TGConnectingPoint num="0" id="29" /> +<TGConnectingPoint num="1" id="30" /> +<TGConnectingPoint num="2" id="31" /> +<TGConnectingPoint num="3" id="32" /> +<TGConnectingPoint num="4" id="33" /> +<TGConnectingPoint num="5" id="34" /> +<TGConnectingPoint num="6" id="35" /> +<TGConnectingPoint num="7" id="36" /> +<extraparam> +<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ns" Operation="" /> +<Attribute access="2" id="x" value="" type="0" typeOther="" /> +</extraparam> +</COMPONENT> +<SUBCOMPONENT type="1203" id="26" > +<father id="37" num="0" /> +<cdparam x="315" y="198" /> +<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" /> +<infoparam name="Primitive port" value="Event start_evt" /> +<TGConnectingPoint num="0" id="25" /> +<extraparam> +<Prop commName="start_evt" commType="1" origin="false" finite="true" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="0" /> +<Type type="1" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +</extraparam> +</SUBCOMPONENT> +<SUBCOMPONENT type="1203" id="28" > +<father id="37" num="1" /> +<cdparam x="515" y="218" /> +<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" /> +<infoparam name="Primitive port" value="Event evt" /> +<TGConnectingPoint num="0" id="27" /> +<extraparam> +<Prop commName="evt" commType="1" origin="true" finite="false" blocking="false" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="0" /> +<Type type="1" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +<Type type="0" typeOther="" /> +</extraparam> +</SUBCOMPONENT> + + +</TMLComponentTaskDiagramPanel> + +<TMLActivityDiagramPanel name="C1" minX="10" maxX="2500" minY="10" maxY="1500" zoom="1.0" > +<COMPONENT type="1001" id="39" > +<cdparam x="428" y="181" /> +<sizeparam width="20" height="20" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" /> +<infoparam name="stop state" value="null" /> +<TGConnectingPoint num="0" id="38" /> +</COMPONENT> + +<COMPONENT type="1020" id="43" > +<cdparam x="389" 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value="TestCycleEvt_wait::C1" taskName="C1" referenceTaskName="TestCycleEvt_wait" priority="0" operationMEC="C1" fatherComponentMECType="0" /> +</extraparam> +</SUBCOMPONENT> +<SUBCOMPONENT type="1101" id="174" > +<father id="208" num="1" /> +<cdparam x="257" y="152" /> +<sizeparam width="168" height="40" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="0" maxX="177" minY="0" maxY="192" /> +<infoparam name="TGComponent" value="TestCycleEvt_wait::C0" /> +<TGConnectingPoint num="0" id="166" /> +<TGConnectingPoint num="1" id="167" /> +<TGConnectingPoint num="2" id="168" /> +<TGConnectingPoint num="3" id="169" /> +<TGConnectingPoint num="4" id="170" /> +<TGConnectingPoint num="5" id="171" /> +<TGConnectingPoint num="6" id="172" /> +<TGConnectingPoint num="7" id="173" /> +<extraparam> +<info value="TestCycleEvt_wait::C0" taskName="C0" referenceTaskName="TestCycleEvt_wait" priority="0" operationMEC="C0" fatherComponentMECType="0" /> +</extraparam> +</SUBCOMPONENT> +<SUBCOMPONENT type="1101" id="183" > +<father id="208" num="2" /> +<cdparam x="256" y="203" /> +<sizeparam width="204" height="40" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<hidden value="false" /> +<cdrectangleparam minX="0" maxX="141" minY="0" maxY="192" /> +<infoparam name="TGComponent" value="TestCycleEvt_wait::C_START" /> +<TGConnectingPoint num="0" id="175" /> +<TGConnectingPoint num="1" id="176" /> +<TGConnectingPoint num="2" id="177" /> +<TGConnectingPoint num="3" id="178" /> +<TGConnectingPoint num="4" id="179" /> +<TGConnectingPoint num="5" id="180" /> +<TGConnectingPoint num="6" id="181" /> +<TGConnectingPoint num="7" id="182" /> +<extraparam> +<info value="TestCycleEvt_wait::C_START" taskName="C_START" referenceTaskName="TestCycleEvt_wait" priority="0" operationMEC="C_START" fatherComponentMECType="0" /> +</extraparam> +</SUBCOMPONENT> + +<CONNECTOR type="125" id="209" > +<cdparam x="799" y="286" /> +<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<infoparam name="connector" value="{info}" /> +<P1 x="799" y="286" id="146" /> +<P2 x="683" y="341" id="116" /> +<AutomaticDrawing data="true" /> +<extraparam> +<info priority="0" /> +<spy value="false" /> +</extraparam> +</CONNECTOR> +<CONNECTOR type="125" id="210" > +<cdparam x="389" y="286" /> +<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" /> +<infoparam name="connector" value="{info}" /> +<P1 x="385" y="287" id="190" /> +<P2 x="558" y="341" id="115" /> +<AutomaticDrawing data="true" /> +<extraparam> +<info priority="0" /> +<spy value="false" /> +</extraparam> +</CONNECTOR> + +</TMLArchiDiagramPanel> + +</Modeling> + + + + +</TURTLEGMODELING> \ No newline at end of file