From 3264afbded4df401ce36535d6fa3c6c5e042d408 Mon Sep 17 00:00:00 2001
From: niusiyuan <siyuan.niu@telecom-paristech.fr>
Date: Mon, 13 May 2019 14:29:03 +0200
Subject: [PATCH] fpga not ok
---
simulators/c++2/Makefile | 2 +-
simulators/c++2/src_simulator/arch/Bus.cpp | 2 +-
simulators/c++2/src_simulator/arch/FPGA.cpp | 340 ++++++++++++------
simulators/c++2/src_simulator/arch/FPGA.h | 31 +-
.../c++2/src_simulator/sim/Simulator.cpp | 217 ++++++++---
simulators/c++2/src_simulator/sim/Simulator.h | 8 +-
6 files changed, 428 insertions(+), 172 deletions(-)
diff --git a/simulators/c++2/Makefile b/simulators/c++2/Makefile
index 3d6ee018b3..5c49e608eb 100755
--- a/simulators/c++2/Makefile
+++ b/simulators/c++2/Makefile
@@ -24,7 +24,7 @@ OS := $(shell uname)
MODULE = run
include Makefile.src
-SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/OrderScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
+SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/OrderScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
SRCS_base_DIR = src_simulator
SRCS_generated = .
diff --git a/simulators/c++2/src_simulator/arch/Bus.cpp b/simulators/c++2/src_simulator/arch/Bus.cpp
index c99ab546a7..ecafa4852a 100644
--- a/simulators/c++2/src_simulator/arch/Bus.cpp
+++ b/simulators/c++2/src_simulator/arch/Bus.cpp
@@ -107,7 +107,7 @@ bool Bus::addTransaction(TMLTransaction* iTransToBeAdded){
#endif
_nextTransaction = 0;
_schedulingNeeded=true;
- //std::cout << "End Bus add trans\n";
+ std::cout << "End Bus add trans\n";
return true;
}
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index 4888dc7984..9de58f1aeb 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -48,27 +48,21 @@
FPGA::FPGA( ID iID,
- std::string iName,
+ std::string iName,
WorkloadSource* iScheduler,
- TMLTime iTimePerCycle,
TMLTime iReconfigTime,
unsigned int iChangeIdleModeCycles,
unsigned int iCyclesBeforeIdle,
unsigned int iCyclesPerExeci,
unsigned int iCyclesPerExecc ) : SchedulableDevice(iID, iName, iScheduler)
- ,_timePerCycle(iTimePerCycle)
,_reconfigTime(iReconfigTime)
,_lastTransaction(0)
-#ifdef PENALTIES_ENABLED
- ,_changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
-#endif
-#ifdef PENALTIES_ENABLED
- , _timePerExeci(_cyclesPerExeci * _timePerCycle /100.0)
- , _timeBeforeIdle(_cyclesBeforeIdle*_timePerCycle)
- , _changeIdleModeTime(_changeIdleModeCycles*_timePerCycle)
-#else
- , _timePerExeci(_cyclesPerExeci*_timePerCycle)
-#endif
+ ,_changeIdleModeCycles(iChangeIdleModeCycles)
+ ,_cyclesBeforeIdle(iCyclesBeforeIdle)
+ ,_cyclesPerExeci(iCyclesPerExeci)
+ ,_cyclesPerExecc(iCyclesPerExecc)
+ ,_transNumber(0)
+
{}
FPGA::~FPGA(){}
@@ -78,53 +72,54 @@ void FPGA::streamBenchmarks(std::ostream& s) const{
std::cout<<"test fpga stramBenchmarks"<<std::endl;
s << TAG_FPGAo << " id=\"" << _ID << "\" name=\"" << _name << "\">" << std::endl;
if (_simulatedTime!=0) s << TAG_UTILo << (static_cast<float>(_busyCycles)/static_cast<float>(_simulatedTime)) << TAG_UTILc;
- s << TAG_ENERGYo << ( (_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle) << TAG_ENERGYc;
- std::cout<< "power consumption "<< ((_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle)<< std::endl;
+ s << TAG_ENERGYo << ( (_simulatedTime)*_static_consumPerCycle) + ((_busyCycles)*_dynamic_consumPerCycle) << TAG_ENERGYc;
+ std::cout<< "power consumption "<< ((_simulatedTime)*_static_consumPerCycle) + ((_busyCycles)*_dynamic_consumPerCycle)<< std::endl;
for(BusMasterList::const_iterator i=_busMasterList.begin(); i != _busMasterList.end(); ++i) (*i)->streamBenchmarks(s);
s << TAG_FPGAc;
}
-
-
TMLTransaction* FPGA::getNextTransaction(){
-std::cout<<"fpga getNextTransaction"<<std::endl;
-#ifdef BUS_ENABLE
- if(_masterNextTransaction==0 || _nextTransaction==0){
- return _nextTransaction;
- }
- else{
+ std::cout<<"fpga getNextTransaction"<<_name<<" ";
+ #ifdef BUS_ENABLED
+ if (_masterNextTransaction==0 || _nextTransaction==0){
+ if(_masterNextTransaction == 0) std::cout<<"master is 0"<<std::endl;
+ if(_nextTransaction==0) std::cout<<"nexttrans is 0"<<std::endl;
+ //if(_nextTransaction) std::cout<<_nextTransaction->toString()<<std::endl;
+ return _nextTransaction;
+ //return 0;
+ }else{
+ //std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
+ std::cout << "1 aTempMaster: " << aTempMaster << std::endl;
bool aResult = aTempMaster->accessGranted();
-
+ // std::cout << "2" << std::endl;
while (aResult && aTempMaster!=_masterNextTransaction){
-
+ // std::cout << "3" << std::endl;
aTempMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
-
+ // std::cout << "4" << std::endl;
aResult = aTempMaster->accessGranted();
-
+ // std::cout << "5" << std::endl;
}
+ if(_nextTransaction)std::cout<<"haha1"<<_nextTransaction->toString()<<std::endl;
return (aResult)?_nextTransaction:0;
}
#else
+ if(_nextTransaction)std::cout<<"haha2"<<_nextTransaction->toString()<<std::endl;
+
return _nextTransaction;
#endif
}
-void FPGA::calcStartTimeLength(TMLTime iTimeSlice){
-std::cout<<"fpga calStartTimeLength"<<std::endl;
+void FPGA::calcStartTimeLength(){
+ std::cout<<"fpga calStartTimeLength "<<std::endl;
#ifdef BUS_ENABLED
std::cout << "FPGA:calcSTL: scheduling decision of FPGA " << _name << ": " << _nextTransaction->toString() << std::endl;
- std::cout << "get channel " << std::endl;
TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
- std::cout << "after get channel " << std::endl;
if (aChannel==0) {
- std::cout<<"test111"<<std::endl;
- //std::cout << "no channel " << std::endl;
_masterNextTransaction=0;
} else {
- std::cout << "get bus " << std::endl;
_masterNextTransaction= getMasterForBus(aChannel->getFirstMaster(_nextTransaction));
if (_masterNextTransaction!=0){
std::cout << "before register transaction at bus " << _masterNextTransaction->toString() << std::endl;
@@ -135,47 +130,28 @@ std::cout<<"fpga calStartTimeLength"<<std::endl;
}
}
#endif
- std::cout<<"test222"<<std::endl;
//round to full cycles!!!
- std::cout<<"time per cycle is "<<_timePerCycle<<std::endl;
- std::cout<<"test333"<<std::endl;
- TMLTime aStartTime = _nextTransaction->getRunnableTime();
- TMLTime aReminder = aStartTime % _timePerCycle;
- if (aReminder!=0) aStartTime+=_timePerCycle - aReminder;
- std::cout << "FPGA: set start time in FPGA=" << aStartTime << " Reminder=" << aReminder <<"\n";
+ TMLTime aStartTime = _nextTransaction->getRunnableTime();
+ std::cout<<"start time !!!!!!!!!!"<<_nextTransaction->toShortString()<<"is "<<aStartTime<<std::endl;
+ //or setStartTime(0)???
_nextTransaction->setStartTime(aStartTime);
#ifdef BUS_ENABLED
if (_masterNextTransaction==0){
-#endif
- //calculate length of transaction
- //if (_nextTransaction->getOperationLength()!=-1){
- std::cout<<"at first virtual length "<<_nextTransaction->getVirtualLength()<<std::endl;
- std::cout<<"another "<<(TMLLength)(iTimeSlice /_timePerExeci)<<std::endl;
- if (iTimeSlice!=0){
- _nextTransaction->setVirtualLength(max(min(_nextTransaction->getVirtualLength(), (TMLLength)(iTimeSlice /_timePerExeci)), (TMLTime)1));
- }
- _nextTransaction->setLength(_nextTransaction->getVirtualLength()*_timePerExeci);
- std::cout<<"!!!!!virtual length is "<<_nextTransaction->getVirtualLength()<<std::endl;
-#ifdef BUS_ENABLED
- }
-#endif
-#ifdef PENALTIES_ENABLED
- //std::cout << "starttime=" << _nextTransaction->getStartTime() << "\n";
- if ((_nextTransaction->getStartTime()-_endSchedule) >=_timeBeforeIdle){
- _nextTransaction->setIdlePenalty(_changeIdleModeTime);
+#endif
+ _nextTransaction->setLength(max(_nextTransaction->getVirtualLength(),(TMLTime)1));
}
-#endif
}
+
void FPGA::truncateAndAddNextTransAt(TMLTime iTime){
std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
//std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
//return truncateNextTransAt(iTime);
//not a problem if scheduling does not take place at time when transaction is actually truncated, tested
//std::cout << "CPU:truncateAndAddNextTransAt " << _name << "time: +++++++++++++++++++++" << iTime << "\n";
- TMLTime aTimeSlice = _scheduler->schedule(iTime);
+// TMLTime aTimeSlice = _scheduler->schedule(iTime);
//_schedulingNeeded=false; 05/05/11
TMLTransaction* aNewTransaction =_scheduler->getNextTransaction(iTime);
//std::cout << "before if\n";
@@ -188,7 +164,7 @@ std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
//if (_nextTransaction!=0 && truncateNextTransAt(iTime)!=0) addTransaction(); //NEW!!!!
if (_nextTransaction!=0 && _masterNextTransaction!=0) _masterNextTransaction->registerTransaction(0);
_nextTransaction = aNewTransaction;
- if (_nextTransaction!=0) calcStartTimeLength(aTimeSlice);
+ if (_nextTransaction!=0) calcStartTimeLength();
}
//std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
@@ -196,30 +172,10 @@ std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
TMLTime FPGA::truncateNextTransAt(TMLTime iTime){
std::cout<<"fpga truncateNextTransAt"<<std::endl;
if (_masterNextTransaction==0){
-#ifdef PENALTIES_ENABLED
-
- //std::cout << "CPU:nt.startTime: " << _nextTransaction->getStartTime() << std::endl;
- if (iTime < _nextTransaction->getStartTime()) {
- return 0;
- }
-
- TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
- TMLTime aStaticPenalty = _nextTransaction->getIdlePenalty() + _nextTransaction->getTaskSwitchingPenalty();
- if (aNewDuration<=aStaticPenalty){
- _nextTransaction->setLength(_timePerExeci);
- _nextTransaction->setVirtualLength(1);
-
- } else{
- aNewDuration-=aStaticPenalty;
- _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration /_timePerExeci),(TMLTime)1));
- _nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
- }
-#else
if (iTime <= _nextTransaction->getStartTime()) return 0; //before: <=
TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
- _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration /_timePerExeci), (TMLTime)1));
- _nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
-#endif
+ _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration), (TMLTime)1));
+ _nextTransaction->setLength(_nextTransaction->getVirtualLength());
}
return _nextTransaction->getOverallLength();
}
@@ -235,41 +191,45 @@ std::cout<<"fpga addTransaction"<<std::endl;
}else{
BusMaster* aFollowingMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
if (aFollowingMaster==0){
- std::cout << "1\n";
+ //std::cout << "1\n";
aFinish=true;
BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
- std::cout << "2\n";
+ // std::cout << "2\n";
Slave* aTempSlave= _nextTransaction->getChannel()->getNextSlave(_nextTransaction);
- std::cout << "3\n";
- aTempMaster->addBusContention(_nextTransaction->getStartTime()-max(_endSchedule,_nextTransaction->getRunnableTime()));
+ //std::cout << "3\n";
while (aTempMaster!=0){
- std::cout << "3a\n";
+ // std::cout << "3a\n";
aTempMaster->addTransaction(_nextTransaction);
- std::cout << "3b\n";
+ // std::cout << "3b\n";
//if (aTempSlave!=0) aTempSlave->addTransaction(_nextTransaction);
if (aTempSlave!=0) aTempSlave->addTransaction(_nextTransaction); //NEW
- std::cout << "4\n";
+ //std::cout << "4\n";
aTempMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
- std::cout << "5\n";
+ //std::cout << "5\n";
aTempSlave= _nextTransaction->getChannel()->getNextSlave(_nextTransaction);
}
- std::cout << "6\n";
+ // std::cout << "6\n";
} else {
std::cout << _name << " bus transaction next round" << std::endl;
_masterNextTransaction=aFollowingMaster;
- std::cout << "7\n";
+ // std::cout << "7\n";
_masterNextTransaction->registerTransaction(_nextTransaction);
aFinish=false;
}
//std::cout << "8\n";
}
+
if (aFinish){
+ //std::cout<<"I am in finish!!!"<<std::endl;
_endSchedule=0;
_simulatedTime=max(_simulatedTime,_endSchedule);
_overallTransNo++; //NEW!!!!!!!!
_overallTransSize+=_nextTransaction->getOperationLength(); //NEW!!!!!!!!
//std::cout << "lets crash execute\n";
- _nextTransaction->getCommand()->execute(); //NEW!!!!
+
+ // std::cout<<_nextTransaction->toString()<<std::endl;
+ if(_nextTransaction->getCommand()==0) std::cout<<"d"<<std::endl;
+ _nextTransaction->getCommand()->execute(); //NEW!!!!
//std::cout << "not crashed\n";
#ifdef TRANSLIST_ENABLED
_transactList.push_back(_nextTransaction);
@@ -279,29 +239,39 @@ std::cout<<"fpga addTransaction"<<std::endl;
#ifdef LISTENERS_ENABLED
NOTIFY_TRANS_EXECUTED(_nextTransaction);
#endif
+
_nextTransaction=0;
+
return true;
} else return false;
}
void FPGA::schedule(){
-
std::cout << "fpga:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
-
- TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
-
+ _scheduler->schedule(_endSchedule);
TMLTransaction* aOldTransaction = _nextTransaction;
_nextTransaction=_scheduler->getNextTransaction(_endSchedule);
-
- if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW
-
+ /* TaskList::const_iterator iter_task=_taskList.begin();
+ std::advance(iter_task,_transNumber);
+ if(iter_task!=_taskList.end()){
+ _nextTransaction=(*iter_task)->getNextTransaction(_endSchedule);
+ if(_nextTransaction!=0 && _nextTransaction->getVirtualLength()==0){
+ _nextTransaction=0;
+ _transNumber=0;
+ }
+ else if(++iter_task==_taskList.end())
+ _transNumber=0;
+ else if(_nextTransaction->getCommand()->getProgress()==_nextTransaction->getLength())
+ _transNumber++;
+ }
+ */
+ if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW
if (_masterNextTransaction!=0) {
_masterNextTransaction->registerTransaction(0);
}
}
-
- if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
+ if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength();
std::cout << "fpga:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
@@ -432,6 +402,170 @@ void FPGA::latencies2XML(std::ostringstream& glob, unsigned int id1, unsigned in
return;
}
+double FPGA::averageLoad (TMLTask* currTask) const{
+ double _averageLoad=0;
+ TMLTime _maxEndTime=0;
+ for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ if( (*i)-> getCommand()->getTask() == currTask ){
+ TMLTime _endTime= (*i)->getEndTime();
+ _maxEndTime=max(_maxEndTime,_endTime);
+ }
+ }
+ for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ if( (*i)-> getCommand()->getTask() == currTask ){
+ _averageLoad += (*i)->getEndTime() - (*i)->getStartTime();
+ }
+ }
+ if(_maxEndTime == 0)
+ return 0;
+ else {
+ _averageLoad = (double)_averageLoad/_maxEndTime;
+ return _averageLoad;
+ }
+ /*if( _maxEndTime == 0 )
+ myfile << "average load is 0" << "<br>";
+ else
+ myfile<<" average load is "<<(double)_averageLoad/_maxEndTime<<"<br>";*/
+
+}
+
+
+void FPGA::drawPieChart(std::ofstream& myfile) const {
+ std::cout<<"fpga drawpie chart"<<std::endl;
+ TMLTime _maxEndTime=0;
+ for(TaskList::const_iterator j =_taskList.begin(); j != _taskList.end(); ++j){
+ for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ if( (*i)-> getCommand()->getTask() == (*j) ){
+ TMLTime _endTime= (*i)->getEndTime();
+ _maxEndTime=max(_maxEndTime,_endTime);
+ }
+ }
+ std::cout<<"max end time is "<<_maxEndTime<<std::endl;
+ std::map <TMLTask*, double > transPercentage;
+ for( TransactionList::const_iterator i = _transactList.begin(); i!= _transactList.end(); ++i){
+ if( (*i)-> getCommand()->getTask() == (*j) ){
+ transPercentage[(*i)-> getCommand()->getTask()]+=(double)((*i)->getEndTime()-(*i)->getStartTime())/_maxEndTime;
+ }
+ }
+ std::map <TMLTask*, double>::iterator iter = transPercentage.begin();
+ myfile << " var chart" << _ID << "_" << (*j)->toShortString() << "= new CanvasJS.Chart(\"chartContainer" << _ID << "_" << (*j)->toShortString() <<"\"," << std::endl;
+ myfile << SCHED_HTML_JS_CONTENT2 << "Average load is " << averageLoad(*j) << SCHED_HTML_JS_CONTENT3 << std::endl;
+ double idle=1;
+ while( iter != transPercentage.end()){
+ myfile << " { y:" << (iter->second)*100 << ", indexLabel: \"" << iter->first->toString() << "\" }," << std::endl;
+ idle-=iter->second;
+ ++iter;
+ }
+ myfile << " { y:" << idle*100 << ", indexLabel: \"idle time\"" << " }" << std::endl;
+ myfile << std::endl;
+ myfile << SCHED_HTML_PIE_END;
+ myfile << "chart" << _ID << "_" << (*j)->toShortString() << ".render();" << std::endl;
+ }
+
+}
+
+void FPGA::showPieChart(std::ofstream& myfile) const{
+ myfile << SCHED_HTML_JS_DIV_ID << _ID << "_" << _htmlCurrTask->toShortString() << SCHED_HTML_JS_DIV_END << "<br>";
+}
+
+void FPGA::schedule2HTML(std::ofstream& myfile) const {
+ myfile << "<h2><span>Scheduling for device: "<< _name << "</span></h2>" << std::endl;
+
+ if ( _transactList.size() == 0 ) {
+ myfile << "<h4>Device never activated</h4>" << std::endl;
+ }
+ else {
+ myfile << "<table>" << std::endl << "<tr>";
+
+ std::map<TMLTask*, std::string> taskCellClasses;
+ unsigned int nextCellClassIndex = 0;
+ TMLTime aCurrTime = 0;
+
+ for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ std::cout << (*i)-> getCommand()->getTask()->toString() <<std::endl;
+ std::cout<< _htmlCurrTask->toString()<<std::endl;
+ if( (*i)-> getCommand()->getTask() == _htmlCurrTask ){
+ std::cout<<"in!!"<<_htmlCurrTask->toString()<<std::endl;
+ TMLTransaction* aCurrTrans = *i;
+ unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
+ std::cout<<"blank is "<<aBlanks<<std::endl;
+ if ( aBlanks > 0 ) {
+ writeHTMLColumn( myfile, aBlanks, "not", "idle time" );
+ }
+
+ unsigned int aLength = aCurrTrans->getOperationLength();
+
+
+ // Issue #4
+ TMLTask* task = aCurrTrans->getCommand()->getTask();
+ std::cout<<"what is this task?"<<task->toString()<<std::endl;
+ const std::string cellClass = determineHTMLCellClass( taskCellClasses, task, nextCellClassIndex );
+
+ writeHTMLColumn( myfile, aLength, cellClass, aCurrTrans->toShortString() );
+
+ aCurrTime = aCurrTrans->getEndTime();
+ }
+ }
+
+
+ myfile << "</tr>" << std::endl << "<tr>";
+
+ for ( unsigned int aLength = 0; aLength < aCurrTime; aLength++ ) {
+ myfile << "<th></th>";
+ }
+
+ myfile << "</tr>" << std::endl << "<tr>";
+
+ for ( unsigned int aLength = 0; aLength <= aCurrTime; aLength += 5 ) {
+ std::ostringstream spanVal;
+ spanVal << aLength;
+ writeHTMLColumn( myfile, 5, "sc", "", spanVal.str(), false );
+ //myfile << "<td colspan=\"5\" class=\"sc\">" << aLength << "</td>";
+ }
+
+ myfile << "</tr>" << std::endl << "</table>" << std::endl << "<table>" << std::endl << "<tr>";
+
+ for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
+ TMLTask* task = (*taskColIt).first;
+ // Unset the default td max-width of 5px. For some reason setting the max-with on a specific t style does not work
+ myfile << "<td class=\"" << taskCellClasses[ task ] << "\"></td><td style=\"max-width: unset;\">" << task->toString() << "</td><td class=\"space\"></td>";
+ }
+
+ myfile << "</tr>" << std::endl;
+
+#ifdef ADD_COMMENTS
+ bool aMoreComments = true, aInit = true;
+ Comment* aComment;
+
+ while ( aMoreComments ) {
+ aMoreComments = false;
+ myfile << "<tr>";
+
+ for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
+ //for(TaskList::const_iterator j=_taskList.begin(); j != _taskList.end(); ++j){
+ TMLTask* task = (*taskColIt).first;
+ std::string aCommentString = task->getNextComment( aInit, aComment );
+
+ if ( aComment == 0 ) {
+ myfile << "<td></td><td></td><td class=\"space\"></td>";
+ }
+ else {
+ replaceAll(aCommentString,"<","<");
+ replaceAll(aCommentString,">",">");
+ aMoreComments = true;
+ myfile << "<td style=\"max-width: unset;\">" << aComment->_time << "</td><td><pre>" << aCommentString << "</pre></td><td class=\"space\"></td>";
+ }
+ }
+
+ aInit = false;
+ myfile << "</tr>" << std::endl;
+ }
+#endif
+ myfile << "</table>" << std::endl;
+ }
+ std::cout<<"end in!!!"<<std::endl;
+}
+
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index e7aa72e06d..26b652f550 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -71,9 +71,6 @@ public:
\param iID ID of the device
\param iName Name of the device
\param iScheduler Pointer to the scheduler object
- \param iTimePerCycle 1/Processor frequency
- \param iMapCapacity Pointer to the overall mapping capacity ????
- \param iMapPenalty Pointer to the mapping penalty ????
\param iReconfigTime reconfiguration time
\param iChangeIdleModeCycles Cycles needed to switch into indle mode
\param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle
@@ -81,7 +78,7 @@ public:
\param iCyclesPerExecc Cycles needed to execute one EXECC unit
*/
- FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iTimePerCycle, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
+ FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
///Destructor
virtual ~FPGA();
///Determines the next FPGA transaction to be executed
@@ -130,10 +127,18 @@ public:
_taskList.push_back(iTask);
if (_scheduler!=0) _scheduler->addWorkloadSource(iTask);
}
+ inline void setTransNumber(unsigned int num) { _transNumber=num;}
+ inline unsigned int getTransNumber() { return _transNumber;}
+ double averageLoad (TMLTask* currTask) const;
+ void drawPieChart(std::ofstream& myfile) const;
+ void showPieChart(std::ofstream& myfile) const;
+ void schedule2HTML(std::ofstream& myfile) const;
+ inline const TaskList& getTaskList() const{return _taskList;}
+ inline void setHtmlCurrTask(TMLTask *t) { _htmlCurrTask=t;}
protected:
///List of all tasks running on the FPGA
TaskList _taskList;
-
+ TMLTask* _htmlCurrTask;
/**
\param iTime Indicates at what time the transaction should be truncated
*/
@@ -142,12 +147,11 @@ protected:
/**
\param iTimeSlice FPGA Time slice granted by the scheduler
*/
- void calcStartTimeLength(TMLTime iTimeSlice);
- ///1/Processor frequency
- TMLTime _timePerCycle;
+ void calcStartTimeLength();
TMLTime _reconfigTime;
+
///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
/**
\param iDummy Dummy Bus Master
@@ -159,22 +163,25 @@ protected:
TMLTransaction* _lastTransaction;
///List of bus masters
BusMasterList _busMasterList;
-#ifdef PENALTIES_ENABLED
+
+
///Cycles needed to switch to idle mode
unsigned int _changeIdleModeCycles;
///Idle cycles which elapse before entering idle mode
unsigned int _cyclesBeforeIdle;
-#endif
+
///Cycles needed to execute one execi unit
unsigned int _cyclesPerExeci;
+ unsigned int _cyclesPerExecc;
///Time needed to execute one execi unit
float _timePerExeci;
-#ifdef PENALTIES_ENABLED
+
///Idle time which elapses before entering idle mode
TMLTime _timeBeforeIdle;
///Time needed to switch into idle mode
TMLTime _changeIdleModeTime;
-#endif
+ unsigned int _transNumber;
+
///State variable for the VCD output
vcdFPGAVisState _vcdOutputState;
};
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index bb0683206c..ad5bd0e022 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -46,6 +46,7 @@
#include <SimComponents.h>
#include <IndeterminismSource.h>
#include <CPU.h>
+#include <FPGA.h>
#include <TMLTask.h>
#include <TMLChannel.h>
#include <ServerIF.h>
@@ -67,7 +68,7 @@ Simulator::~Simulator(){
//if (_randChoiceBreak!=0) delete _randChoiceBreak;
}
-TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevice) const{
+TMLTransaction* Simulator::getTransLowestEndTimeCPU(SchedulableDevice*& oResultDevice) const{
//int tmp=0;
TMLTransaction *aMarker=0, *aTempTrans;
TMLTime aLowestTime=-1;
@@ -107,6 +108,39 @@ TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevi
return aMarker;
}
+TMLTransaction* Simulator::getTransLowestEndTimeFPGA(SchedulableDevice*& oResultDevice) const{
+ //int tmp=0;
+ TMLTransaction *aMarker=0, *aTempTrans;
+ TMLTime aLowestTime=-1;
+ SchedulableDevice* aTempDevice;
+
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:getTLET: before loop" << std::endl;
+#endif
+ for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
+ aTempDevice=*i;
+ aTempTrans=aTempDevice->getNextTransaction();
+ if (aTempTrans!=0 && aTempTrans->getVirtualLength()>0){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:getTLET: transaction found on " << aTempDevice->toString() << ": " << aTempTrans->toString() << std::endl;
+#endif
+ std::cout<<aTempTrans->toShortString()<<"getEndtime is "<<aTempTrans->getEndTime()<<std::endl;
+ std::cout<<"alowest time is "<<aLowestTime<<std::endl;
+ if (aTempTrans->getEndTime() < aLowestTime){
+ std::cout<<"in!!!"<<std::endl;
+ aMarker=aTempTrans;
+ aLowestTime=aTempTrans->getEndTime();
+ oResultDevice=aTempDevice;
+ }
+ }
+ //#ifdef DEBUG_KERNEL
+ else {
+
+ }
+ }
+ return aMarker;
+}
+
ID Simulator::schedule2GraphAUT(std::ostream& iAUTFile, ID iStartState, unsigned int& oTransCounter) const{
CPUList::iterator i;
@@ -249,6 +283,9 @@ void Simulator::schedule2TXT(std::string& iTraceFileName) const{
//for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
(*i)->schedule2TXT(myfile);
+ }
+ for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
+ (*i)->schedule2TXT(myfile);
}
//for(BusList::const_iterator j=_simComp->getBusIterator(false); j != _simComp->getBusIterator(true); ++j){
for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
@@ -362,6 +399,9 @@ std::cout<<"schedule2HTML--------------------------------------*****************
for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
(*i)->drawPieChart(myfile);
}
+ for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
+ (*i)->drawPieChart(myfile);
+ }
for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
(*j)->drawPieChart(myfile);
}
@@ -387,6 +427,17 @@ std::cout<<"schedule2HTML--------------------------------------*****************
}
jsfile.close();
+
+ for(FPGAList::const_iterator j=_simComp->getFPGAList().begin(); j != _simComp->getFPGAList().end(); ++j){
+ for(TaskList::const_iterator i = (*j)->getTaskList().begin(); i != (*j)->getTaskList().end(); ++i){
+ (*j)->setHtmlCurrTask(*i);
+ std::cout<<"begin fpga html "<<(*j)->toShortString()<<std::endl;
+ (*j)->schedule2HTML(myfile);
+ std::cout<<"end fpga html "<<(*j)->toShortString()<<std::endl;
+ (*j)->showPieChart(myfile);
+ }
+ }
+
for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
(*j)->schedule2HTML(myfile);
(*j)->showPieChart(myfile);
@@ -554,48 +605,39 @@ bool Simulator::channelImpactsCommand(TMLChannel* iCh, TMLCommand* iCmd){
}
bool Simulator::simulate(TMLTransaction*& oLastTrans){
- TMLTransaction* depTransaction,*depCPUnextTrans,*transLET;
- TMLCommand* commandLET,*depCommand,*depCPUnextCommand;
+ TMLTransaction* depTransaction,*depCPUnextTrans,*depFPGAnextTrans,*transLETcpu,*transLETfpga;
+ TMLCommand* commandLET,*depCommand,*depCPUnextCommand,*depFPGAnextCommand;
TMLTask* depTask;
- SchedulableDevice* cpuLET;
+ SchedulableDevice* cpuLET, *fpgaLET;
CPU* depCPU;
+ FPGA *depFPGA;
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: first schedule" << std::endl;
#endif
_simComp->setStopFlag(false,"");
- //std::cout << "before loop " << std::endl;
- //for(TaskList::const_iterator i=_simComp->getTaskIterator(false); i!=_simComp->getTaskIterator(true);i++){
for(TaskList::const_iterator i=_simComp->getTaskList().begin(); i!=_simComp->getTaskList().end();i++){
- //std::cout << "loop it " << (*i)->toString() << std::endl;
if ((*i)->getCurrCommand()!=0) (*i)->getCurrCommand()->prepare(true);
- //std::cout << "loop it end" << (*i)->toString() << std::endl;
}
- //std::cout << "after loop1" << std::endl;
#ifdef EBRDD_ENABLED
for(EBRDDList::const_iterator i=_simComp->getEBRDDIterator(false); i!=_simComp->getEBRDDIterator(true);i++){
if ((*i)->getCurrCommand()!=0) (*i)->getCurrCommand()->prepare();
}
#endif
- //std::cout << "after loop2" << std::endl;
- //for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::setRescheduleFlag));
- //for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::schedule));
std::cout<<"simulate"<<std::endl;
- for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
+ /* for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
//std::cout << "after schedule" << std::endl;
- transLET=getTransLowestEndTime(cpuLET);
+ transLETcpu=getTransLowestEndTimeCPU(cpuLET);
//std::cout << "after getTLET" << std::endl;
#ifdef LISTENERS_ENABLED
if (_wasReset) NOTIFY_SIM_STARTED();
_wasReset=false;
#endif
- while (transLET!=0 && !_simComp->getStopFlag()){
+ while (transLETcpu!=0 && !_simComp->getStopFlag()){
#ifdef DEBUG_KERNEL
- std::cout << "kernel:simulate: scheduling decision: " << transLET->toString() << std::endl;
+ std::cout << "kernel:simulate: scheduling decision: " << transLETcpu->toString() << std::endl;
#endif
- commandLET=transLET->getCommand();
- //if (depTask!=NULL){
- // transLET->setTaskID(commandLET->getID());
- //}
+ commandLET=transLETcpu->getCommand();
+
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: BEFORE add trans " << commandLET->toString() << std::endl;
std::cout << "cpuLET= " << cpuLET->toString() << std::endl;
@@ -603,10 +645,8 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#endif
std::cout<<"in simulator begin addTransaction "<<std::endl;
bool x = cpuLET->addTransaction(0);
- // cpuLET->setCycleTime(0);
std::cout<<"in simulator end addTransactin "<<std::endl;
- //std::cout << "kernel:simulate: x=" << x << std::endl;
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: AFTER add trans: " << x << std::endl;
#endif
@@ -615,22 +655,18 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
std::cout << "kernel:simulate: add transaction 0" << commandLET->toString() << std::endl;
#endif
unsigned int nbOfChannels = commandLET->getNbOfChannels();
- //bool aRescheduleCoresFlag=false;
for (unsigned int i=0;i<nbOfChannels; i++){
if ((depTask=commandLET->getDependentTask(i))==0) continue;
- //if (depTask!=0){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: dependent Task found" << std::endl;
#endif
depCPU=depTask->getCPU();
- //std::cout << "CPU this task : " << cpuLET->toString();
- //if (depCPU==0) std::cout << " CPU dep task " << depTask->toString() << ": 0\n"; else std::cout << " CPU dep task: "<< depTask->toString() << " " << depCPU->toString() << std::endl;
+
if (depCPU!=cpuLET){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: Tasks running on different CPUs" << std::endl;
#endif
depCommand=depTask->getCurrCommand();
- //if (depCommand!=0 && (dynamic_cast<TMLSelectCommand*>(depCommand)!=0 || channelImpactsCommand(commandLET->getChannel(i), depCommand))){
if (depCommand!=0 && channelImpactsCommand(commandLET->getChannel(i), depCommand)) { //RIGHT one
#ifdef DEBUG_KERNEL
@@ -641,17 +677,8 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: dependent task has a current transaction and is not blocked any more" << std::endl;
#endif
- /* if (depCPU==0){
- aRescheduleCoresFlag=true;
- //#ifdef DEBUG_KERNEL
- std::cout << "Multi Core scheduling procedure\n";
- //#endif
- depTask->setRescheduleFlagForCores();
- continue;
- }*/
- //std::cout << "Let's crash!!!!!!!!\n";
+
depCPUnextTrans=depCPU->getNextTransaction();
- //std::cout << "Not crahed!!!!!!!!\n";
if (depCPUnextTrans!=0){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: transaction scheduled on dependent CPU" << std::endl;
@@ -662,7 +689,7 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
std::cout << "kernel:simulate: dependent task not yet scheduled on dependent CPU" << std::endl;
#endif
- depCPU->truncateAndAddNextTransAt(transLET->getEndTime());
+ depCPU->truncateAndAddNextTransAt(transLETcpu->getEndTime());
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: dependent transaction truncated" << std::endl;
#endif
@@ -680,29 +707,112 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: invoke schedule on executing CPU" << std::endl;
#endif
- /*if (aRescheduleCoresFlag){
- for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
- if (*i!=cpuLET) (*i)->truncateIfNecessary(transLET->getEndTime());
- }
- for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
- if (*i!=cpuLET) (*i)->rescheduleIfNecessary();
- }
- }*/
cpuLET->schedule();
#ifdef LISTENERS_ENABLED
- NOTIFY_TIME_ADVANCES(transLET->getEndTime());
+ NOTIFY_TIME_ADVANCES(transLETcpu->getEndTime());
+#endif
+ }
+ oLastTrans=transLETcpu;
+
+ transLETcpu=getTransLowestEndTimeCPU(cpuLET);
+
+ }
+ */
+ for_each(_simComp->getFPGAList().begin(), _simComp->getFPGAList().end(),std::mem_fun(&FPGA::schedule));
+ //std::cout << "after schedule" << std::endl;
+ transLETfpga=getTransLowestEndTimeFPGA(fpgaLET);
+ //std::cout << "after getTLET" << std::endl;
+#ifdef LISTENERS_ENABLED
+ if (_wasReset) NOTIFY_SIM_STARTED();
+ _wasReset=false;
+#endif
+ while (transLETfpga!=0 && !_simComp->getStopFlag()){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: scheduling decision: " << transLETfpga->toString() << std::endl;
+#endif
+ commandLET=transLETfpga->getCommand();
+
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: BEFORE add trans " << commandLET->toString() << std::endl;
+ std::cout << "cpuLET= " << fpgaLET->toString() << std::endl;
+ std::cout << "kernel:simulate:cpuLET printed" << std::endl;
+#endif
+ std::cout<<"in simulator begin addTransaction "<<std::endl;
+ bool x = fpgaLET->addTransaction(0);
+ std::cout<<"in simulator end addTransactin "<<std::endl;
+
+ #ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: AFTER add trans: " << x << std::endl;
+#endif
+ if (x){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: add transaction 0" << commandLET->toString() << std::endl;
+#endif
+ unsigned int nbOfChannels = commandLET->getNbOfChannels();
+ for (unsigned int i=0;i<nbOfChannels; i++){
+ if ((depTask=commandLET->getDependentTask(i))==0) continue;
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: dependent Task found" << std::endl;
+#endif
+ depFPGA=depTask->getFPGA();
+
+ if (depCPU!=cpuLET){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: Tasks running on different CPUs" << std::endl;
+#endif
+ depCommand=depTask->getCurrCommand();
+ if (depCommand!=0 && channelImpactsCommand(commandLET->getChannel(i), depCommand)) { //RIGHT one
+
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: commands are accessing the same channel" << std::endl;
+#endif
+ depTransaction=depCommand->getCurrTransaction();
+ if (depTransaction!=0 && depTransaction->getVirtualLength()!=0){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: dependent task has a current transaction and is not blocked any more" << std::endl;
+#endif
+
+ depFPGAnextTrans=depCPU->getNextTransaction();
+ if (depFPGAnextTrans!=0){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: transaction scheduled on dependent CPU" << std::endl;
+#endif
+ depFPGAnextCommand=depFPGAnextTrans->getCommand();
+ if (depFPGAnextCommand->getTask()!=depTask){
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: dependent task not yet scheduled on dependent CPU" << std::endl;
+#endif
+
+ // depFPGA->truncateAndAddNextTransAt(transLETcpu->getEndTime());
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: dependent transaction truncated" << std::endl;
+#endif
+ }
+ }else{
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: schedule dependent CPU " << depFPGA->toString() << std::endl;
+#endif
+ depFPGA->schedule();
+ }
+ }
+ }
+ }
+ }
+#ifdef DEBUG_KERNEL
+ std::cout << "kernel:simulate: invoke schedule on executing FPGA" << std::endl;
+#endif
+ fpgaLET->schedule();
+#ifdef LISTENERS_ENABLED
+ NOTIFY_TIME_ADVANCES(transLETfpga->getEndTime());
#endif
}
- oLastTrans=transLET;
+ oLastTrans=transLETfpga;
- //std::cout << "kernel:simulate: getTransLowestEndTime" << std::endl;
- transLET=getTransLowestEndTime(cpuLET);
+ transLETfpga=getTransLowestEndTimeFPGA(fpgaLET);
- //_syncInfo->_server->sendReply("Sleep once again\n");
- //sleep(1);
}
- bool aSimCompleted = (transLET==0 && !_simComp->getStoppedOnAction());
+ bool aSimCompleted = (transLETcpu==0 && transLETfpga==0 && !_simComp->getStoppedOnAction());
if (aSimCompleted){
#ifdef LISTENERS_ENABLED
@@ -711,7 +821,6 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#endif
_longRunTime = max(_longRunTime, SchedulableDevice::getSimulatedTime());
_shortRunTime = min(_shortRunTime, SchedulableDevice::getSimulatedTime());
- //_simComp->showTaskStates();
}
return (aSimCompleted);
}
diff --git a/simulators/c++2/src_simulator/sim/Simulator.h b/simulators/c++2/src_simulator/sim/Simulator.h
index 173b66cb50..d04b19337e 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.h
+++ b/simulators/c++2/src_simulator/sim/Simulator.h
@@ -293,7 +293,13 @@ protected:
\param oResultDevice Pointer to the CPU which is running the returned transaction
\return Pointer to transaction with lowest end time
*/
- TMLTransaction* getTransLowestEndTime(SchedulableDevice*& oResultDevice) const;
+ TMLTransaction* getTransLowestEndTimeCPU(SchedulableDevice*& oResultDevice) const;
+ ///Returns a pointer to the transaction with the lowest end time proposed by FPGA schedulers
+ /**
+ \param oResultDevice Pointer to the FPGA which is running the returned transaction
+ \return Pointer to transaction with lowest end time
+ */
+ TMLTransaction* getTransLowestEndTimeFPGA(SchedulableDevice*& oResultDevice) const;
///Decodes a simulation command
/**
\param iCmd Pointer to the command
--
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