diff --git a/src/main/java/camstranslator/toTopcell/Declaration.java b/src/main/java/camstranslator/toTopcell/Declaration.java
new file mode 100755
index 0000000000000000000000000000000000000000..c0a84ad254fff81cfa763a8d9985bfe32d924e9a
--- /dev/null
+++ b/src/main/java/camstranslator/toTopcell/Declaration.java
@@ -0,0 +1,326 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015
+ v2.1 Daniela GENIUS, 2016, 2017 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.*;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarBlock;
+import avatartranslator.AvatarSignal;
+import avatartranslator.AvatarSpecification;
+
+public class Declaration {
+ public static AvatarSpecification avspec;
+ private static String CR = "\n";
+ private static String CR2 = "\n\n";
+
+ public static String generateName(AvatarRelation _ar, int _index) {
+ return _ar.block1.getName() + "_" + _ar.getSignal1(_index).getName() + "__" + _ar.block2.getName() + "_" + _ar.getSignal2(_index).getName();
+ }
+
+ public static String getDeclarations(AvatarSpecification _avspec) {
+ avspec =_avspec;
+
+ String declaration = "//----------------------------Instantiation-------------------------------" + CR2;
+
+
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar().size();
+
+ boolean trace_caba=true;
+
+ if(nb_clusters==0){
+ declaration += CR
+ + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);" + CR;
+ }
+ else{
+ declaration += CR
+ + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);" + CR;
+ }
+ if(nb_clusters==0){
+ declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);" + CR;
+ }
+ else{
+ declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);" + CR;
+ }
+
+ if(nb_clusters==0){
+ declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);" + CR;
+}
+ else{
+ declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);" + CR;
+ }
+
+ if(nb_clusters==0){
+ declaration = declaration + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());" + CR;
+ }
+ else{
+ declaration = declaration + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());" + CR;
+ }
+
+ if(nb_clusters==0){
+ declaration = declaration + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);" + CR2;
+ }
+ else{
+ declaration = declaration + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);" + CR2;
+ }
+
+ if(nb_clusters==0){
+ declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);" + CR;
+ }
+ else{
+ declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);" + CR;
+ }
+
+ if(nb_clusters==0){
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ }
+ else{
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
+ }
+
+ if(nb_clusters==0){
+ int i=0;
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab(" + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
+ i++;
+ }
+
+ //target address depends on number of TTYs and RAMs
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
+ if(ram.getIndex()==0){
+ declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab(2), maptab);" + CR;
+ }
+ else{
+ declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab("
+ + ram.getNo_target() + "), maptab);" + CR;
+ }
+ }
+ else{
+ int i=0;
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab("+ tty.getNo_cluster()+"," + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
+ i++;}
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
+ declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab("+ram.getNo_cluster()+","
+ + ram.getNo_target() + "), maptab);" + CR2;
+ }
+ if(nb_clusters==0){
+ declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+(TopCellGenerator.avatardd.getNb_target())+"));" + CR;
+ declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("+(TopCellGenerator.avatardd.getNb_target()+1)+"), \"soclib0\");" + CR;
+ declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" + CR;
+ }else{
+ declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));" + CR;
+ declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");" + CR;
+ declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);" + CR;
+ }
+
+if(nb_clusters==0){
+ for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
+ System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
+ System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
+
+ //declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
+ declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
+ int i=0;
+
+ //if BUS was not last in input file, update here
+
+ bus.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
+ bus.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
+ }
+
+ for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
+ //System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
+ //System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
+ /* The user might have forgotten to specify the following, thus set default values */
+
+ if(vgmn.getMinLatency()<2)
+ vgmn.setMinLatency(10); //default value; must be > 2
+ if(vgmn.getFifoDepth()<2)
+ vgmn.setFifoDepth(8); //default value; must be > 2
+
+
+ //declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNbRAM()+TopCellGenerator.avatardd.getNbTTY()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+
+ // if VGMN was not last in input file, update here
+ vgmn.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
+ vgmn.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target()+4);
+
+ }
+
+
+
+ /* VciMwmrController(
+ sc_module_name name,
+ const MappingTable &mt,
+ const IntTab &srcid,
+ const IntTab &tgtid,
+ const size_t plaps,
+ const size_t fifo_to_coproc_depth,
+ const size_t fifo_from_coproc_depth,
+ const size_t n_to_coproc,
+ const size_t n_from_coproc,
+ const size_t n_config,
+ const size_t n_status,
+ const bool use_llsc );
+ */
+
+ //only non-clustered version
+ for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
+ declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
+
+ }
+}
+else {
+
+ /***************************************/
+ /* clustered interconnect architecture */
+ /***************************************/
+
+
+ for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
+
+ declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, "+ +nb_clusters+"," + nb_clusters + ");" + CR2;
+
+ //if BUS was not last in input file, update here
+ int i=0;
+ }
+
+ for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
+ System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
+ System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
+
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "+ nb_clusters +"," + nb_clusters +
+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+
+ }
+
+ int i=0;
+ for (AvatarCrossbar crossbar : TopCellGenerator.avatardd.getAllCrossbar()) {
+
+ //currently the number on initiators and targets is fixed
+
+ crossbar.setClusterIndex(i);
+
+ if (crossbar.getClusterIndex()==0){
+ crossbar.setNbOfAttachedInitiators(nb_clusters);
+ crossbar.setNbOfAttachedTargets(13);
+ }
+ else{
+ //processor(s) and link to central interconnect are initiators
+ //crossbar.setNbOfAttachedInitiators(2);
+ //crossbar.setNbOfAttachedTargets(2);
+ crossbar.setNbOfAttachedInitiators(1);
+ crossbar.setNbOfAttachedTargets(1);
+ }
+
+ System.out.println("initiators: "+crossbar.getNbOfAttachedInitiators());
+ System.out.println("targets: "+crossbar.getNbOfAttachedTargets());
+
+ declaration += "soclib::caba::VciLocalCrossbar<vci_param> crossbar"+crossbar.getClusterIndex()+"(\"" + crossbar.getCrossbarName() + "\"" + " , maptab, IntTab("+ crossbar.getClusterIndex()+"),IntTab("+crossbar.getClusterIndex()+"), "+crossbar.getNbOfAttachedInitiators()+", "+crossbar.getNbOfAttachedTargets()+");" + CR2;
+
+
+ //if CROSSBAR was not last in input file, update here
+ crossbar.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
+ crossbar.setNbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
+
+ }
+}
+int i=0;
+ //monitoring CPU by logger(1)
+ for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
+
+ if (cpu.getMonitored()==1){
+ System.out.println("Spy CPU");
+ declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
+ i++;
+ }
+ }
+
+ int j=0;
+ //monitoring RAM either by logger(1) ou stats (2)
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ if (ram.getMonitored()==0){
+
+ }
+ if (ram.getMonitored()==1){
+ System.out.println("Spy RAM : Logger");
+ declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
+ i++;
+ }
+ else{
+ if (ram.getMonitored()==2){
+ System.out.println("Spy RAM : Stats");
+ String strArray="";
+
+ for(AvatarRelation ar: avspec.getRelations()) {
+
+ for(i=0; i<ar.nbOfSignals() ; i++) {
+
+ AvatarSignal as1=ar.getSignal1(i);
+ AvatarSignal as2=ar.getSignal2(i);
+
+ String chname = generateName(ar,i);
+ strArray=strArray+"\""+chname+"\",";
+ }
+
+ }
+
+
+ declaration += "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"+j+"(\"mwmr_stats" + j+"\",maptab, data_ldr, \"mwmr"+j+".log\",stringArray("+strArray+"NULL));" + CR2;
+ j++;
+ }
+ }
+ }
+
+return declaration;
+ }
+
+}
\ No newline at end of file
diff --git a/src/main/java/camstranslator/toTopcell/Header.java b/src/main/java/camstranslator/toTopcell/Header.java
new file mode 100755
index 0000000000000000000000000000000000000000..18cb9813c130afdfd1bfe8e41bba2c8424c31663
--- /dev/null
+++ b/src/main/java/camstranslator/toTopcell/Header.java
@@ -0,0 +1,141 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+public class Header {
+
+ static private String header;
+int nb_clusters=5;
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ Header(){
+ }
+ public static String getHeader() {
+ int with_vgsb=TopCellGenerator.avatardd.getAllBus().size();
+
+ header = "//-------------------------------Header------------------------------------" + CR2
+ + "#include <iostream>" + CR
+ + "#include <cstdlib>" + CR
+ + "#include <vector>" + CR
+ + "#include <string>" + CR
+ + "#include <stdexcept>" + CR
+ + "#include <cstdarg>" +CR2
+ + "#define CONFIG_GDB_SERVER" + CR
+ + "#define CONFIG_SOCLIB_MEMCHECK" + CR2;
+
+ header = header + "#include \"iss_memchecker.h\"" + CR
+ +"#include \"gdbserver.h\""+ CR2
+ +"#include \"ppc405.h\"" + CR
+ +"#include \"niosII.h\"" + CR
+ +"#include \"mips32.h\"" + CR
+ +"#include \"arm.h\"" + CR
+ +"#include \"sparcv8.h\"" + CR
+ +"#include \"lm32.h\"" + CR2
+ + "#include \"mapping_table.h\"" + CR
+ + "#include \"vci_fdt_rom.h\"" + CR + "#include \"vci_xcache_wrapper.h\"" + CR
+ + "#include \"vci_ram.h\"" + CR + "#include \"vci_heterogeneous_rom.h\"" + CR
+ + "#include \"vci_multi_tty.h\"" + CR + "#include \"vci_locks.h\"" + CR + "#include \"vci_xicu.h\""+ CR
+ + "#include \"vci_mwmr_stats.h\""+ CR;//DG 20.09.
+ if (with_vgsb>0){
+ header +="#include \"vci_vgsb.h\""+ CR;
+ }
+ else{
+ header +="#include \"vci_vgmn.h\""+ CR;
+ }
+
+ header+= "#include \"vci_block_device.h\"" + CR
+ + "#include \"vci_simhelper.h\"" + CR + "#include \"vci_fd_access.h\"" + CR
+ + "#include \"vci_ethernet.h\"" + CR
+ + "#include \"vci_rttimer.h\"" + CR
+ + "#include \"vci_logger.h\"" + CR
+ + "#include \"vci_local_crossbar.h\"" + CR2;
+
+ header = header +"namespace {" + CR
++"std::vector<std::string> stringArray(" + CR
++" const char *first, ... )" + CR
++"{" + CR
++" std::vector<std::string> ret;" + CR
++" va_list arg;" + CR
++" va_start(arg, first);" + CR
++" const char *s = first;" + CR
++" while(s) {" + CR
++" ret.push_back(std::string(s));" + CR
++" s = va_arg(arg, const char *);" + CR
++" };" + CR
++" va_end(arg);" + CR
++" return ret;" + CR
++"}" + CR2
++"std::vector<int> intArray(" + CR
++" const int length, ... )" + CR
++"{" + CR
++" int i;" + CR
++" std::vector<int> ret;" + CR
++" va_list arg;" + CR
++" va_start(arg, length);" + CR2
++" for (i=0; i<length; ++i) {" + CR
++" ret.push_back(va_arg(arg, int));" + CR
++" };" + CR
++" va_end(arg);" + CR
++" return ret;" + CR
++"}" + CR
+ +"}" + CR2;
+
+ header = header + "using namespace soclib;" + CR + "using common::IntTab;" + CR + "using common::Segment;";
+
+
+ if(TopCellGenerator.avatardd.getNbClusters()==0){
+ header = header + CR2 + "static common::MappingTable maptab(32, IntTab(8), IntTab(8), 0xfff00000);";
+ }
+ else{
+header = header + CR2 + "static common::MappingTable maptab(32, IntTab(8,4), IntTab(8,4), 0xfff00000);";
+ }
+ return header;
+ }
+}
diff --git a/src/main/java/camstranslator/toTopcell/NetList.java b/src/main/java/camstranslator/toTopcell/NetList.java
new file mode 100755
index 0000000000000000000000000000000000000000..74870d23ee8af377e4bed015477f95024caafd69
--- /dev/null
+++ b/src/main/java/camstranslator/toTopcell/NetList.java
@@ -0,0 +1,448 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCPU;
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+
+public class NetList {
+ public static final String NAME_CLK = "signal_clk";
+ public static final String CR = "\n";
+ public static final String CR2 = "\n\n";
+ private static final String NAME_RST = "signal_resetn";
+ private static boolean tracing;
+
+ public static String getNetlist(String icn, boolean _tracing) {
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
+
+ tracing = _tracing;
+
+ String netlist;
+
+ netlist = CR2 + "//------------------------------Netlist---------------------------------" + CR2;
+
+ netlist = netlist + "// icu" + CR2;
+ netlist = netlist + " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));" + CR2;
+
+ netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
+ netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
+
+ netlist = netlist + " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");" + CR;
+
+ netlist = netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");" + CR2;
+ netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
+ netlist = netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
+ netlist = netlist + " {" + CR;
+ netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
+ netlist = netlist + " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
+ netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
+ netlist = netlist + " }" + CR2;
+ netlist = netlist + " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR2;
+
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
+ netlist = netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
+
+ netlist = netlist + "///////////////// cpus" + CR2;
+
+ netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
+ netlist = netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
+ netlist = netlist + " // configure het_rom" + CR;
+ netlist = netlist + " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
+
+ netlist = netlist + " // add cpu node to device tree" + CR;
+ netlist = netlist + " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+ netlist = netlist + " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);" + CR;
+ if(icn=="vgmn")
+ {
+ netlist = netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ else{
+ netlist = netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+
+ netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
+ netlist = netlist + " }" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " vcihetrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcifdtrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcisimhelper.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirttimer.p_clk(signal_clk);" + CR;
+
+ netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcifdtrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcisimhelper.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirttimer.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
+
+ netlist = netlist + " vcifdtrom.p_vci(signal_vci_vcifdtrom);" + CR;
+ netlist = netlist + " vcirom.p_vci(signal_vci_vcirom);" + CR;
+ netlist = netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
+ netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
+ netlist = netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
+
+ if(icn=="vgmn"){
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" + CR;
+ netlist = netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist = netlist + " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist = netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist = netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" + CR2;
+ netlist = netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
+ netlist = netlist + " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist = netlist + " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
+ netlist = netlist + " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
+ }
+ else{
+ netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" + CR;
+ netlist = netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist = netlist + " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist = netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist = netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" + CR2;
+ netlist = netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
+ netlist = netlist + " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist = netlist + " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
+ netlist = netlist + " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
+ }
+
+ if(nb_clusters==0){
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+
+ netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ }
+ else{
+ netlist = netlist + "vgsb.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ }
+ }
+ }
+
+ /* clustered version */
+ /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster*/
+ else{
+ int i;
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+
+ netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ //target number for local cluster: this is set at avatardd creation
+ netlist = netlist + "crossbar"+ram.getNo_cluster()+".p_to_target["+ram.getNo_target()+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ }
+
+ //one mwmr ram and one mwmrdram per cluster are added transparently
+
+ /*convention for local target ids on cluster :
+ channel: 0
+ mwmr_ram: 1
+ mwmrd_ram: 2
+ locks: 3
+ ram: 4
+ tty: 5
+ */
+
+ /* for(i=0;i<nb_clusters;i++){
+ netlist = netlist + "crossbar"+i+".p_to_target["+1+"](signal_vci_mwmr_ram"+i+");" + CR2;
+ //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
+ netlist = netlist + "crossbar"+i+".p_to_target["+2+"](signal_vci_mwmrd_ram"+i+");" + CR2;
+ //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
+ } */
+ }
+
+ if(nb_clusters==0){
+ /* we can have several TTYs and each is associated to the fdtrom */
+ if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
+ }else{ /* vgsb */
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
+ }
+ }else{
+ /* cluster case */
+ if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+6+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+7+"](signal_vci_bdt);" + CR;
+ }else{
+ netlist = netlist + "vgsb.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+6+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+7+"](signal_vci_bdt);" + CR;
+ }
+ }
+ //netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty\",\"soclib:vci_multi_tty\");" + CR2;
+
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
+ netlist = netlist + "vcifdtrom.end_node();;" + CR2;
+
+ netlist = netlist + "// TTY netlist" + CR2;
+ int i=0;
+
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ netlist = netlist + tty.getTTYName()+".p_clk(signal_clk);" + CR;
+ netlist = netlist + tty.getTTYName()+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist + tty.getTTYName()+".p_vci(signal_vci_tty"+i+");" + CR2;
+ int no_irq_tty=0;
+ if(nb_clusters==0){
+
+ if(icn=="vgmn"){
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+i+"\");" + CR2;
+ netlist = netlist + "vgmn.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
+ netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
+ }else{
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+tty.getNo_tty()+"\");" + CR2;
+ netlist = netlist + "vgsb.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
+ netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
+ }
+ }
+
+ //we have a clustered architecture: identify local crossbar
+ else{
+ int j;
+ for(j=0;j<nb_clusters;j++){
+ netlist = netlist + "crossbar"+j+".p_to_target["+tty.getNo_target()+"](signal_vci_tty"+j+");" + CR2;
+ //recalculate irq addresses, 5 devices generating irq per cluster
+ netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+(tty.getNo_cluster()*5)+"]);" + CR2;
+ }
+ }
+ i++;
+ //One ICU per cluster per default
+ no_irq_tty+=6;//if there is more than one tty, irq >5
+ }
+
+ //////////////// fdrom
+
+ netlist = netlist + "{" + CR2;
+ netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR; netlist = netlist + " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR;
+ netlist = netlist + "}" + CR2;
+
+ //////////////// ethernet
+
+ netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
+ netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
+ netlist = netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
+
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");" + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// block device
+
+ netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
+ netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
+ netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
+
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");" + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// fd access
+ netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
+
+ netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
+ netlist = netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
+
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");" + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR2;
+
+ //////////////// locks
+
+ netlist = netlist + "vcilocks.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcilocks.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcilocks.p_vci(signal_vci_vcilocks);" + CR;
+
+ ////////////////MWMR controller; hypothesis 1 per coprocessor
+ // if(nb_cluster == 0){
+ i=0;
+ for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
+ //a coprocessor with FIFO interface
+ netlist = netlist +copro.getCoprocName()+".p_clk(signal_clk);" + CR;
+ netlist = netlist +copro.getCoprocName()+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist + copro.getCoprocName()+".p_"+i+"_ctrl(signal_fifo_"+i+"_ctrl);" + CR;
+ //and its mwmr controller
+ netlist = netlist + "mwmr"+i+".p_clk(signal_clk);" + CR;
+ netlist = netlist + "mwmr"+i+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "mwmr"+i+".p_vci_initiator(signal_mwmr_"+i+"initiator);" + CR;
+ netlist = netlist + "mwmr"+i+".p_vci_target(signal_mwmr_"+i+"_target);" + CR;
+ netlist = netlist + copro.getCoprocName()+".p_"+i+"_ctrl(signal_fifo_"+i+"_ctrl);" + CR;
+ }
+
+
+ //If there is a spy, add logger or stats to vci interface
+
+ i=0;
+ for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
+ int number = cpu.getNo_proc();
+ if(cpu.getMonitored()==1){
+ netlist=netlist+CR+
+ "logger"+i+".p_clk(signal_clk);" +CR+
+ "logger"+i+".p_resetn(signal_resetn);" +CR+
+ "logger"+i+".p_vci(signal_vci_m["+number+"]);" +CR2;
+ i++;
+ }
+
+ }
+ int j=0;
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ if (ram.getMonitored()==1){
+ int number = number = ram.getIndex();
+ netlist += "logger"+i+".p_clk(signal_clk);" + CR;
+ netlist += "logger"+i+".p_resetn(signal_resetn);" + CR;
+ netlist += "logger"+i+".p_vci(signal_vci_vciram"+number+");" + CR2;
+ i++;
+ }
+ else{
+
+ if (ram.getMonitored()==2){
+ int number = number = ram.getIndex();
+ netlist += "mwmr_stats"+j+".p_clk(signal_clk);" + CR;
+ netlist += "mwmr_stats"+j+".p_resetn(signal_resetn);" + CR;
+ netlist += "mwmr_stats"+j+".p_vci(signal_vci_vciram"+number+");" + CR2;
+ j++;
+ }
+ }
+ }
+
+ //generate trace file if marked trace option
+
+ if(tracing){
+ netlist += "sc_trace_file *tf;" + CR;
+ netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
+ netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
+ netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
+
+ netlist += "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");" + CR;
+ netlist += "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");" + CR;
+ netlist += "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");" + CR;
+ netlist += "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");" + CR;
+
+ for(i=0;i<TopCellGenerator.avatardd.getNb_init();i++){
+ netlist += "sc_trace(tf,signal_vci_m["+ i +"] ,\"signal_vci_m["+ i +"]\");" + CR;
+ }
+
+ i=0;
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
+
+ netlist += "sc_trace(tf,signal_vci_tty"+tty.getNo_tty()+",\"TTY"+tty.getNo_tty()+"\");" + CR;
+ netlist += "sc_trace(tf,signal_xicu_irq["+ i +"] ,\"signal_xicu_irq["+ i +"]\");" + CR;
+ i++;
+ }
+
+ netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
+ netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
+ netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ if (ram.getMonitored()==0){
+ netlist += "sc_trace(tf,signal_vci_vciram"+ram.getIndex()+",\"Memory"+ram.getIndex()+"\");" + CR;
+ }
+ }
+ }
+ netlist = netlist + " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = false;" + CR;
+ netlist = netlist + " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = true;" + CR;
+ netlist = netlist + " sc_core::sc_start();" + CR;
+ if(tracing){
+ netlist += "sc_close_vcd_trace_file(tf);" + CR;
+ }
+ netlist = netlist + CR + " return EXIT_SUCCESS;"+ CR;
+ netlist = netlist +"}" + CR;
+ return netlist;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/camstranslator/toTopcell/Signal.java b/src/main/java/camstranslator/toTopcell/Signal.java
new file mode 100755
index 0000000000000000000000000000000000000000..73ecb81e10452be786ef97ad04e5a0191b506473
--- /dev/null
+++ b/src/main/java/camstranslator/toTopcell/Signal.java
@@ -0,0 +1,127 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* This class generates the lines of the topcell where the signals are declared*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+
+public class Signal {
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private final static String NAME_CLK = "signal_clk";
+ private static final String NAME_RST = "signal_resetn";
+
+ public static String getSignal() {
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
+ //nb_clusters=2;
+ String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
+
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];"+ CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");"+ CR;
+
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");"+ CR;
+ signal = signal +" caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");"+ CR;
+ signal = signal +" caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");"+ CR;
+ signal = signal +" caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");"+ CR;
+signal = signal +"caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");"+ CR;
+//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
+//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccessi;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccesst;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_bdi;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_bdt;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_etherneti;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_ethernett;"+ CR;
+ signal = signal +""+ CR;
+ signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
+ signal = signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" + CR2;
+ int i=0;
+ for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_fifo_"+i+"_ctrl;"+ CR;
+ }
+
+if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
+ i = 0;
+
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ //signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
+signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
+i++;
+ }
+
+ signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+ System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
+}
+
+else{
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2; i=0;
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ // signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
+signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
+ i++;
+ }
+
+ signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+ //System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
+ System.out.print("number of clusters : " + TopCellGenerator.avatardd.getNbClusters()+"\n");
+
+}
+ return signal;
+ }
+}
diff --git a/src/main/java/camstranslator/toTopcell/Simulation.java b/src/main/java/camstranslator/toTopcell/Simulation.java
new file mode 100755
index 0000000000000000000000000000000000000000..8ab750f451d4d48f426684f12ef8f4a29ebba867
--- /dev/null
+++ b/src/main/java/camstranslator/toTopcell/Simulation.java
@@ -0,0 +1,74 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+public class Simulation {
+
+ private static String simulation;
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public Simulation(){
+ }
+
+ public static String getSimulation(){
+ simulation = CR2+ CR2+
+ "/***************************************************************************" + CR +
+ "----------------------------simulation-------------------------" + CR +
+ "***************************************************************************/"+CR2 ;
+ simulation =simulation+"int sc_main (int argc, char *argv[])" + CR + "{" + CR;
+ simulation = simulation +" try {" + CR +" return _main(argc, argv);" + CR + " }" + CR2;
+ simulation =simulation +" catch (std::exception &e) {" + CR + " std::cout << e.what() << std::endl;" + CR + " throw;"+ CR+" }";
+ simulation =simulation+" catch (...) {" + CR;
+ simulation =simulation+"std::cout << \"Unknown exception occured\" << std::endl;" + CR;
+ simulation =simulation+"throw;" + CR;
+ simulation =simulation+"}" + CR;
+ simulation = simulation+ CR +" return 1;"+ CR + "}" ;
+ return simulation;
+ }
+}
diff --git a/src/main/java/camstranslator/toTopcell/TopCellGenerator.java b/src/main/java/camstranslator/toTopcell/TopCellGenerator.java
index 2b2864456be8fbec48f1f27dd6897b69c695324e..f41a7146c37c88ef4fa81cf4e1858d4c6d266d96 100755
--- a/src/main/java/camstranslator/toTopcell/TopCellGenerator.java
+++ b/src/main/java/camstranslator/toTopcell/TopCellGenerator.java
@@ -124,10 +124,7 @@ public class TopCellGenerator
}
makeVCIparameters();
makeConfig();
- String top = Header.getHeader() +
- Code.getCode() +
- MappingTable.getMappingTable() +
- Loader.getLoader(avspec) +
+ String top = Header.getHeader() +
Declaration.getDeclarations(avspec) +
Signal.getSignal() +
NetList.getNetlist(icn,tracing) +
@@ -160,73 +157,8 @@ public class TopCellGenerator
fw.write(top);
fw.close();
} catch (IOException ex) {
- }
- saveFileDeploy(path);
- saveFilePlatform(path);
- saveFileProcinfo(path);
- saveFileNBproc(path);
- }
-
- public void saveFileDeploy(String path) {
-
- try {
- System.err.println(path + GENERATED_PATH + "deployinfo.h");
- FileWriter fw = new FileWriter(path + GENERATED_PATH + "/deployinfo.h");
- deployinfo = Deployinfo.getDeployInfo();
- fw.write(deployinfo);
- fw.close();
-
- System.err.println(path + GENERATED_PATH + "deployinfo_map.h");
- FileWriter fw_map = new FileWriter(path + GENERATED_PATH + "/deployinfo_map.h");
- deployinfo_map = Deployinfo.getDeployInfoMap(avspec);
- fw_map.write(deployinfo_map);
- fw_map.close();
-
- //ajout CD 9.6
- System.err.println(path + GENERATED_PATH + "deployinfo_ram.h");
- FileWriter fw_ram = new FileWriter(path + GENERATED_PATH + "/deployinfo_ram.h");
- deployinfo_ram = Deployinfo.getDeployInfoRam(avspec);
- fw_ram.write(deployinfo_ram);
- fw_ram.close();
- } catch (Exception ex) {
- ex.printStackTrace();
- }
- }
-
- public void saveFileProcinfo(String path) {
-
- try {
- System.err.println(path + GENERATED_PATH + "procinfo.mk");
- FileWriter fw = new FileWriter(path + GENERATED_PATH + "/procinfo.mk");
- procinfo = Deployinfo.getProcInfo();
- fw.write(procinfo);
- fw.close();
- } catch (IOException ex) {
- }
- }
-
- public void saveFileNBproc(String path) {
-
- try {
- System.err.println(path + GENERATED_PATH + "nbproc");
- FileWriter fw = new FileWriter(path + GENERATED_PATH + "/nbproc");
- nbproc = Deployinfo.getNbProc();
- fw.write(nbproc);
- fw.close();
- } catch (IOException ex) {
- }
- }
-
- public void saveFilePlatform(String path) {
-
- try {
- System.err.println(path + GENERATED_PATH + "platform_desc");
- FileWriter fw = new FileWriter(path + GENERATED_PATH + "/platform_desc");
- platform_desc = Platforminfo.getPlatformInfo();
- fw.write(platform_desc);
- fw.close();
- } catch (IOException ex) {
- }
+ }
}
+
}