From 3d43afaa3d32c567092c3cae96ccd47bdd40f6af Mon Sep 17 00:00:00 2001
From: Daniela Genius <genius@debussy.soc.lip6.fr>
Date: Tue, 26 Jun 2018 11:30:16 +0200
Subject: [PATCH] update for clustered and IO
---
src/main/java/ddtranslatorSoclib/Code.java | 224 +++++
.../java/ddtranslatorSoclib/Declaration.java | 587 ++++++++++++
.../java/ddtranslatorSoclib/Deployinfo.java | 322 +++++++
src/main/java/ddtranslatorSoclib/Header.java | 216 +++++
src/main/java/ddtranslatorSoclib/Loader.java | 182 ++++
.../java/ddtranslatorSoclib/MappingTable.java | 465 +++++++++
src/main/java/ddtranslatorSoclib/NetList.java | 881 ++++++++++++++++++
.../java/ddtranslatorSoclib/Platforminfo.java | 161 ++++
src/main/java/ddtranslatorSoclib/Signal.java | 280 ++++++
.../java/ddtranslatorSoclib/Simulation.java | 118 +++
.../ddtranslatorSoclib/TopCellGenerator.java | 363 ++++++++
.../ui/AvatarDeploymentPanelTranslator.java | 729 ++++++++-------
src/main/java/ui/AvatarDesignPanel.java | 2 +-
13 files changed, 4210 insertions(+), 320 deletions(-)
create mode 100755 src/main/java/ddtranslatorSoclib/Code.java
create mode 100755 src/main/java/ddtranslatorSoclib/Declaration.java
create mode 100755 src/main/java/ddtranslatorSoclib/Deployinfo.java
create mode 100755 src/main/java/ddtranslatorSoclib/Header.java
create mode 100755 src/main/java/ddtranslatorSoclib/Loader.java
create mode 100755 src/main/java/ddtranslatorSoclib/MappingTable.java
create mode 100755 src/main/java/ddtranslatorSoclib/NetList.java
create mode 100755 src/main/java/ddtranslatorSoclib/Platforminfo.java
create mode 100755 src/main/java/ddtranslatorSoclib/Signal.java
create mode 100755 src/main/java/ddtranslatorSoclib/Simulation.java
create mode 100755 src/main/java/ddtranslatorSoclib/TopCellGenerator.java
diff --git a/src/main/java/ddtranslatorSoclib/Code.java b/src/main/java/ddtranslatorSoclib/Code.java
new file mode 100755
index 0000000000..bdb31f5cde
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Code.java
@@ -0,0 +1,224 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCPU;
+import common.ConfigurationTTool;
+
+import java.io.BufferedReader;
+import java.io.File;
+import java.io.FileReader;
+import java.io.IOException;
+
+public class Code
+{
+
+ static private String creation;
+ static private String creation2;
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private final static String GENERATED_PATH =
+ "generated_topcell" + File.separator;
+
+ public static String getCode ()
+ {
+
+ creation = CR +
+ "//**********************************************************************"
+ + CR + "// Processor entry and connection code" +
+ CR +
+ "//**********************************************************************"
+ + CR2 +
+ "#define CPU_CONNECT(n) void (n)(CpuEntry *e, sc_core::sc_clock &clk, \\"
+ + CR +
+ "sc_core::sc_signal<bool> &rstn, caba::VciSignals<vci_param> &m)"
+ + CR2 +
+ "#define INIT_TOOLS(n) void (n)(const common::Loader &ldr)" +
+ CR2 + "#define NEW_CPU(n) caba::BaseModule * (n)(CpuEntry *e)" +
+ CR2 + "struct CpuEntry { " + CR + " caba::BaseModule *cpu; " +
+ CR + " common::Loader *text_ldr;" + CR +
+ " sc_core::sc_signal<bool> *irq_sig;" + CR +
+ " size_t irq_sig_count;" + CR + " std::string type;" + CR +
+ " std::string name;" + CR + " int id;" + CR +
+ " CPU_CONNECT(*connect);" + CR + " INIT_TOOLS(*init_tools);" +
+ CR + " NEW_CPU(*new_cpu);" + CR + "};" + CR2 +
+ " template <class Iss_>" + CR + " CPU_CONNECT(cpu_connect){" +
+ CR + " typedef ISS_NEST(Iss_) Iss;" + CR +
+ " caba::VciXcacheWrapper<vci_param, Iss> *cpu = static_cast<caba::VciXcacheWrapper<vci_param, Iss> *>(e->cpu);"
+ + CR + " cpu->p_clk(clk);" + CR + " cpu->p_resetn(rstn);" +
+ CR + " e->irq_sig_count = Iss::n_irq; " + CR +
+ " e->irq_sig = new sc_core::sc_signal<bool>[Iss::n_irq];" + CR +
+ " for ( size_t irq = 0; irq < (size_t)Iss::n_irq; ++irq )" + CR +
+ " cpu->p_irq[irq](e->irq_sig[irq]); " + CR +
+ " cpu->p_vci(m);" + CR + " }" + CR2;
+
+ creation = creation + "template <class Iss>" + CR +
+ "INIT_TOOLS(initialize_tools){" + CR;
+
+ // Mips based platform requires a special bootstrap where only cpu 0 starts first
+
+ int isMipsArchitecture = 0;
+
+ try
+ {
+ String path = ConfigurationTTool.AVATARMPSoCCodeDirectory;
+ BufferedReader in =
+ new BufferedReader (new
+ FileReader (path +
+ "/Makefile.forsoclib"));
+ String line = null;
+ while ((line = in.readLine ()) != null)
+ {
+
+ if (line.equals ("SOCLIB_CPU=mips32el"))
+ {
+ isMipsArchitecture = 1;
+ }
+ }
+ in.close ();
+ }
+ catch (IOException e)
+ {
+ e.printStackTrace ();
+ }
+
+ if (isMipsArchitecture == 1)
+ {
+ creation = creation +
+ "Iss::setBoostrapCpuId(0);" + CR +
+ "/* Only processor 0 starts execution on reset */" + CR;
+ }
+ creation = creation +
+ "#if defined(CONFIG_GDB_SERVER)" + CR +
+ "ISS_NEST(Iss)::set_loader(ldr);" + CR +
+ "#endif" + CR +
+ "#if defined(CONFIG_SOCLIB_MEMCHECK)" + CR +
+ " common::IssMemchecker<Iss>::init(maptab, ldr, \"vci_multi_tty0,vci_xicu,vci_block_device,vci_fd_acccess,vci_ethernet,vci_fdt_rom,vci_rttimer\");"
+ + CR + "#endif" + CR + "}" + CR2;
+
+ // currently, all caches must have the same parameters : take one
+ AvatarCPU cpu = TopCellGenerator.avatardd.getAllCPU ().getFirst ();
+
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+
+
+ if (nb_clusters == 0)
+ {
+ creation = creation + "template <class Iss>" + CR +
+ "NEW_CPU(new_cpu){" + CR +
+ "return new caba::VciXcacheWrapper<vci_param, ISS_NEST(Iss)>(e->name.c_str(), e->id, maptab, IntTab(e->id),"
+ + cpu.getICacheWays () + "," + cpu.getICacheSets () + "," +
+ cpu.getICacheWords () + "," + cpu.getDCacheWays () + "," +
+ cpu.getDCacheSets () + "," + cpu.getDCacheWords () + ")" +
+ ";" + CR + "}" + CR2;
+ }
+ else
+ {
+ creation = creation + "template <class Iss>" + CR +
+ "NEW_CPU(new_cpu){" + CR +
+ "return new caba::VciXcacheWrapper<vci_param, ISS_NEST(Iss)>(e->name.c_str(), e->id, maptab, IntTab(e->id,e->id),"
+ + cpu.getICacheWays () + "," + cpu.getICacheSets () + "," +
+ cpu.getICacheWords () + "," + cpu.getDCacheWays () + "," +
+ cpu.getDCacheSets () + "," + cpu.getDCacheWords () + ")" +
+ ";" + CR + "}" + CR2;
+ }
+
+ creation = creation +
+ "/***************************************************************************"
+ + CR +
+ "--------------------Processor creation code-------------------------"
+ + CR +
+ "***************************************************************************/"
+ + CR2 + "template <class Iss> " + CR +
+ " CpuEntry * newCpuEntry_(CpuEntry *e){" + CR +
+ " e->new_cpu = new_cpu<Iss>;" + CR +
+ " e->connect = cpu_connect<Iss>;" + CR +
+ " e->init_tools = initialize_tools<Iss>;" + CR + " return e;" +
+ CR + "}" + CR2 +
+ " struct CpuEntry * newCpuEntry(const std::string &type, int id, common::Loader *ldr) {"
+ + CR + " CpuEntry *e = new CpuEntry;" + CR +
+ " std::ostringstream o;" + CR + " o << type << \"_\" << id; " +
+ CR2 + " e->cpu = 0;" + CR + " e->text_ldr = ldr;" + CR +
+ " e->type = type;" + CR + " e->name = o.str();" + CR +
+ " e->id = id; " + CR2 + " switch (type[0]) {" + CR +
+ " case 'm':" + CR + " if (type == \"mips32el\")" + CR +
+ " return newCpuEntry_<common::Mips32ElIss>(e);" + CR +
+ " else if (type == \"mips32eb\")" + CR +
+ " return newCpuEntry_<common::Mips32EbIss>(e);" + CR2 +
+ " case 'a':" + CR + " if (type == \"arm\")" + CR +
+ " return newCpuEntry_<common::ArmIss>(e);" + CR +
+ " case 'n':" + CR + " if (type == \"nios2\")" + CR +
+ " return newCpuEntry_<common::Nios2fIss>(e);" +
+ CR2 + " case \'p\':" + CR +
+ " if (type == \"ppc\")return newCpuEntry_<common::Ppc405Iss>(e);"
+ + CR2 + " case 's':" + CR +
+ " if (type == \"sparc\")" + CR +
+ " return newCpuEntry_<common::Sparcv8Iss<8> >(e);"
+ + CR + " else if (type == \"sparc_2wins\")" +
+ CR +
+ " return newCpuEntry_<common::Sparcv8Iss<2> >(e);"
+ + CR2 + " case 'l':" + CR +
+ " if (type == \"lm32\")" + CR +
+ " return newCpuEntry_<common::LM32Iss<true> >(e);"
+ + CR + " } " + CR2 +
+ " throw std::runtime_error(type + \": wrong processor type\"); "
+ + CR + "}" + CR2 +
+ "//**********************************************************************"
+ + CR +
+ "// Args parsing and netlist"
+ + CR2 +
+ "//**********************************************************************"
+ + CR2 + "int _main(int argc, char **argv)" + CR +
+ "{" + CR2 +
+ " // Avoid repeating these everywhere" + CR +
+ " std::vector<CpuEntry*> cpus;" + CR +
+ " common::Loader data_ldr;" + CR +
+ " data_ldr.memory_default(0x5a);" + CR;
+ return creation;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/Declaration.java b/src/main/java/ddtranslatorSoclib/Declaration.java
new file mode 100755
index 0000000000..d9da5832ed
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Declaration.java
@@ -0,0 +1,587 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015
+ v2.1 Daniela GENIUS, 2016, 2017 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.*;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarBlock;
+import avatartranslator.AvatarSignal;
+import avatartranslator.AvatarSpecification;
+import myutil.TraceManager;
+
+public class Declaration
+{
+ public static AvatarSpecification avspec;
+ private static String CR = "\n";
+ private static String CR2 = "\n\n";
+
+ public static String generateName (AvatarRelation _ar, int _index)
+ {
+ return _ar.block1.getName () + "_" +
+ _ar.getSignal1 (_index).getName () + "__" +
+ _ar.block2.getName () + "_" + _ar.getSignal2 (_index).getName ();
+ }
+
+ public static String getDeclarations (AvatarSpecification _avspec)
+ {
+ avspec = _avspec;
+
+ String declaration =
+ "//----------------------------Instantiation-------------------------------"
+ + CR2;
+
+
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+
+ boolean trace_caba = true;
+
+ if (nb_clusters == 0)
+ {
+ declaration += CR
+ +
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration += CR
+ +
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);"
+ + CR;
+ }
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);"
+ + CR;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);"
+ + CR;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration =
+ declaration +
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
+ else
+ {
+ declaration =
+ declaration +
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration =
+ declaration +
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);"
+ + CR2;
+ }
+ else
+ {
+ declaration =
+ declaration +
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);"
+ + CR2;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);"
+ + CR;
+ }
+
+ int last_tty = 0;
+ if (nb_clusters == 0)
+ {
+ int i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_target () + "), maptab, \"vci_multi_tty" +
+ i + "\", NULL);" + CR;
+ i++;
+ last_tty = tty.getNo_target () + 1;
+ }
+
+ //target address depends on number of TTYs and RAMs
+
+ if (nb_clusters == 0)
+ {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(last_tty+3)+"), maptab);" + CR;
+ }
+ else
+ {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
+ }
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ if (ram.getIndex () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" +
+ ram.getMemoryName () + "\"" +
+ ", IntTab(2), maptab);" + CR;
+ }
+ else
+ {
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" +
+ ram.getMemoryName () + "\"" + ", IntTab(" +
+ ram.getNo_target () + "), maptab);" + CR;
+ }
+ }
+ else
+ {
+ int i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_cluster () + "," + tty.getNo_target () +
+ "), maptab, \"vci_multi_tty" + i + "\", NULL);" + CR;
+ i++;
+ }
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" + ram.getMemoryName () +
+ "\"" + ", IntTab(" + ram.getNo_cluster () + "," +
+ ram.getNo_target () + "), maptab);" + CR2;
+ }
+ if (nb_clusters == 0)
+ {
+
+ declaration +=
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
+ + last_tty + "));" + CR;
+ declaration +=
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
+ + (last_tty + 1) + "), \"soclib0\");" + CR;
+ declaration +=
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
+ + (last_tty + 2) + "),\"block0.iso\", 2048);" + CR;
+
+ //non-clustered version
+ int hwa_no = 0;
+ //int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);
+ int init_no = TopCellGenerator.avatardd.getNb_init ();
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", maptab, IntTab(" + (init_no - 1) +
+ "), IntTab(" + target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+
+//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+
+ if (copro.getCoprocType () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciInputEngine<vci_param>" +
+ copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,\"input.txt\",1024,1,8);" + CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ declaration +=
+ "soclib::caba::VciOutputEngine<vci_param>"
+ + copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"
+ + CR;
+ }
+
+
+ else
+ {
+ declaration +=
+ "dsx::caba::MyHWA" + hwa_no + " hwa" +
+ hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+ hwa_no++;
+
+ }
+ }
+ init_no++;
+ target_no++;
+ }
+ }
+ else
+ {
+ declaration +=
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));"
+ + CR;
+ declaration +=
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");"
+ + CR;
+ declaration +=
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);"
+ + CR;
+
+ int hwa_no = 0;
+ //int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);
+ int init_no = TopCellGenerator.avatardd.getNb_init ();
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", maptab, IntTab(" + (init_no - 1) +
+ "), IntTab(" + target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+
+ //one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+ // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
+
+ if (copro.getCoprocType () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciInputEngine<vci_param>" +
+ copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,\"input.txt\",1024,1,8);" + CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ declaration +=
+ "soclib::caba::VciOutputEngine<vci_param>"
+ + copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"
+ + CR;
+ }
+
+
+ else
+ {
+ declaration +=
+ "dsx::caba::MyHWA" + hwa_no + " hwa" +
+ hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+
+ hwa_no++;
+ }
+ }
+ target_no++;
+ init_no++;
+ }
+
+ }
+
+ if (nb_clusters == 0)
+ {
+
+ for (AvatarBus bus:TopCellGenerator.avatardd.
+ getAllBus ())
+ {
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+ declaration +=
+ "soclib::caba::VciVgsb<vci_param> vgsb(\"" +
+ bus.getBusName () + "\"" + " , maptab," + (3 +
+ TopCellGenerator.
+ avatardd.getNb_init
+ ()) + "," +
+ (TopCellGenerator.avatardd.getNb_target () + 3) +
+ ");" + CR2;
+ int i = 0;
+
+ }
+
+ for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
+ getAllVgmn ())
+ {
+ /* set default values */
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+
+ if (vgmn.getMinLatency () < 2)
+ vgmn.setMinLatency (10); //default value; must be > 2
+ if (vgmn.getFifoDepth () < 2)
+ vgmn.setFifoDepth (8); //default value; must be > 2
+
+ declaration +=
+ "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
+ vgmn.getVgmnName () + "\"" + " , maptab, " + (3 +
+ TopCellGenerator.
+ avatardd.
+ getNb_init
+ ()) +
+ "," + (TopCellGenerator.avatardd.getNb_target () +
+ 3) + "," + vgmn.getMinLatency () + "," +
+ vgmn.getFifoDepth () + ");" + CR2;
+ }
+
+ }
+ else
+ {
+
+ /***************************************/
+ /* clustered interconnect architecture */
+ /***************************************/
+
+
+ for (AvatarBus bus:TopCellGenerator.avatardd.
+ getAllBus ())
+ {
+
+ declaration +=
+ "soclib::caba::VciVgsb<vci_param> vgsb(\"" +
+ bus.getBusName () + "\"" + " , maptab, " +
+ +nb_clusters + "," + nb_clusters + ");" + CR2;
+
+ //if BUS was not last in input file, update here
+ int i = 0;
+ }
+
+ for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
+ getAllVgmn ())
+ {
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+ declaration +=
+ "soclib::caba::VciVgmn<vci_param> vgmn (\"" +
+ vgmn.getVgmnName () + "\"" + " , maptab, " +
+ nb_clusters + "," + nb_clusters + "," +
+ vgmn.getMinLatency () + "," + vgmn.getFifoDepth () +
+ ");" + CR2;
+
+ }
+
+ int i = 0;
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.
+ getAllCrossbar
+ ())
+ {
+
+ crossbar.setClusterIndex (i);
+
+ if (crossbar.getClusterIndex () == 0)
+ {
+ crossbar.setNbOfAttachedInitiators (nb_clusters);
+ crossbar.setNbOfAttachedTargets (13);
+ }
+ else
+ {
+
+ crossbar.setNbOfAttachedInitiators (1);
+ crossbar.setNbOfAttachedTargets (1);
+ }
+
+ TraceManager.addDev ("initiators: " +
+ crossbar.
+ getNbOfAttachedInitiators ());
+ TraceManager.addDev ("targets: " +
+ crossbar.getNbOfAttachedTargets ());
+
+ declaration +=
+ "soclib::caba::VciLocalCrossbar<vci_param> crossbar" +
+ crossbar.getClusterIndex () + "(\"" +
+ crossbar.getCrossbarName () + "\"" +
+ " , maptab, IntTab(" + crossbar.getClusterIndex () +
+ "),IntTab(" + crossbar.getClusterIndex () + "), " +
+ crossbar.getNbOfAttachedInitiators () + ", " +
+ crossbar.getNbOfAttachedTargets () + ");" + CR2;
+
+ //if CROSSBAR was not last in input file, update here
+ crossbar.
+ setNbOfAttachedInitiators (TopCellGenerator.avatardd.
+ getNb_init ());
+ crossbar.
+ setNbOfAttachedTargets (TopCellGenerator.avatardd.
+ getNb_target ());
+ i++;
+ }
+ }
+ int i = 0;
+ //monitoring CPU by logger(1)
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+
+ if (cpu.getMonitored () == 1)
+ {
+
+ declaration +=
+ "soclib::caba::VciLogger<vci_param> logger" + i +
+ "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ }
+
+ int j = 0;
+ //monitoring RAM either by logger(1) or stats (2)
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+
+ }
+ if (ram.getMonitored () == 1)
+ {
+
+ declaration +=
+ "soclib::caba::VciLogger<vci_param> logger" + i +
+ "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ else
+ {
+ if (ram.getMonitored () == 2)
+ {
+
+ String strArray = "";
+
+ for (AvatarRelation ar:avspec.
+ getRelations
+ ())
+ {
+
+ for (i = 0; i < ar.nbOfSignals (); i++)
+ {
+
+ AvatarSignal as1 = ar.getSignal1 (i);
+ AvatarSignal as2 = ar.getSignal2 (i);
+
+ String chname = generateName (ar, i);
+ strArray =
+ strArray + "\"" + chname + "\",";
+ }
+
+ }
+
+ declaration +=
+ "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"
+ + j + "(\"mwmr_stats" + j +
+ "\",maptab, data_ldr, \"mwmr" + j +
+ ".log\",stringArray(" + strArray + "NULL));" +
+ CR2;
+ j++;
+ }
+ }
+ }
+
+ return declaration;
+ }
+
+}
diff --git a/src/main/java/ddtranslatorSoclib/Deployinfo.java b/src/main/java/ddtranslatorSoclib/Deployinfo.java
new file mode 100755
index 0000000000..47b994750a
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Deployinfo.java
@@ -0,0 +1,322 @@
+
+/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ Daniela Genius, Lip6, UMR 7606
+
+ ludovic.apvrille AT enst.fr
+ daniela.genius@lip6.fr
+
+ This software is a computer program whose purpose is to allow the
+ edition of TURTLE analysis, design and deployment diagrams, to
+ allow the generation of RT-LOTOS or Java code from this diagram,
+ and at last to allow the analysis of formal validation traces
+ obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ from INRIA Rhone-Alpes.
+
+ This software is governed by the CeCILL license under French law and
+ abiding by the rules of distribution of free software. You can use,
+ modify and/ or redistribute the software under the terms of the CeCILL
+ license as circulated by CEA, CNRS and INRIA at the following URL
+ "http://www.cecill.info".
+
+ As a counterpart to the access to the source code and rights to copy,
+ modify and redistribute granted by the license, users are provided only
+ with a limited warranty and the software's author, the holder of the
+ economic rights, and the successive licensors have only limited
+ liability.
+
+ In this respect, the user's attention is drawn to the risks associated
+ with loading, using, modifying and/or developing or reproducing the
+ software by the user in light of its specific status of free software,
+ that may mean that it is complicated to manipulate, and that also
+ therefore means that it is reserved for developers and experienced
+ professionals having in-depth computer knowledge. Users are therefore
+ encouraged to load and test the software's suitability as regards their
+ requirements in conditions enabling the security of their systems and/or
+ data to be ensured and, more generally, to use and operate it in the
+ same conditions as regards security.
+
+ The fact that you are presently reading this means that you have had
+ knowledge of the CeCILL license and that you accept its terms.
+*/
+
+/* This class generates the deployment info for the ldscript*/
+
+/* authors: v1.0 Daniela GENIUS 2015 modified for clustered architecture 08/2016 */
+
+/*
+
+/* here is an example of an ldscript :
+#define CHANNEL_0_NAME channel0
+#define CHANNEL_1_NAME channel1
+
+#define DEPLOY_RAM_0_NAME channel_ram0
+#define DEPLOY_RAM_0_ADDR 0x6f000000
+#define DEPLOY_RAM_0_SIZE 0x01000000
+
+#define DEPLOY_RAM_1_NAME channel_ram1
+#define DEPLOY_RAM_1_ADDR 0x5f000000
+#define DEPLOY_RAM_1_SIZE 0x01000000
+
+#define MAP_A\
+ .channel0 : { \
+ __channel_0_start = ABSOLUTE(.);\
+ *(section_channel0)\
+ } > DEPLOY_RAM_0_NAME\
+ .channel1 : { \
+ __channel_1_start = ABSOLUTE(.);\
+ *(section_channel1) \
+ } > DEPLOY_RAM_1_NAME
+ */
+
package ddtranslatorSoclib.toTopCell;
+
import ddtranslatorSoclib.*;
+
import ddtranslatorSoclib.toSoclib.*;
+
import avatartranslator.*;
+
import myutil.Conversion;
+
import myutil.FileException;
+
import myutil.FileUtils;
+
import myutil.TraceManager;
+
import java.io.File;
+
import java.util.LinkedList;
+
import java.util.List;
+
import java.util.Vector;
+
public class Deployinfo
+{
+
private final static String CR = "\n";
+
private final static String CR2 = "\n\n";
+
public static AvatarSpecification avspec;
+
public static AvatarddSpecification avddspec;
+
private Vector < ? >warnings;
+
private MainFileSoclib mainFile;
+
private Vector < TaskFileSoclib > taskFiles;
+
private String makefile_src;
+
private String makefile_SocLib;
+
+ /* for the moment, this is specific to PowerPC */
+
public Deployinfo (AvatarddSpecification _avddspec,
+ AvatarSpecification _avspec)
+ {
+
avspec = _avspec;
+
avddspec = _avddspec;
+
taskFiles = new Vector < TaskFileSoclib > ();
+
}
public static String getDeployInfo ()
+ {
+
int nb_clusters =
+ TopCellGenerator.avatardd.getAllCrossbar ().size ();
+
String deployinfo = CR;
+
+ /* dimension segments according to the number of clusters */
+
+ /*determine the "step" between segments dedicated to a cluster */
+
int CLUSTER_SIZE;
+
+ /*if the user does not specify the size, take default value */
+ if (nb_clusters < 16)
+ {
+
CLUSTER_SIZE = 268435456;
+
}
+
+ else
+ {
+
CLUSTER_SIZE = 134217728;
+
} // to be refined -> dynamically adapt
+
int size;
+
+ /* there can be many RAMS, but then must be smaller dimensioned */
+
int i = 0;
+
for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+
+ /* data memory always starts at 0x10000000 */
+
int address_start = 268435456;
+
String string_adress_start =
+ Integer.toHexString (i * 268435456);
+
+ /* segment size is either given by the user or a default value is calculated */
+
if (ram.getDataSize () == 0)
+ {
+
if ((nb_clusters < 16)
+ || (TopCellGenerator.avatardd.getAllRAM ().size () <
+ 16))
+ {
+
size = 268435456;
+
}
+
+ else
+ {
+
+ //smaller segments
+ size = 134217728;
+
}
+
}
+
+ else
+ {
+
size = ram.getDataSize ();
+
}
+
ram.setDataSize (size);
+
size = ram.getDataSize ();
+
TraceManager.addDev ("***hardware RAM size" + size);
+
String string_size_half = (Integer.toHexString (size / 2)); //segments are half uram, half cram
+
deployinfo +=
+ "#define CACHED_RAM" + ram.getIndex () + "_NAME cram" +
+ ram.getIndex () + CR;
+
deployinfo =
+ deployinfo + "#define CACHED_RAM" + ram.getIndex () +
+ "_ADDR 0x" + Integer.toHexString (address_start +
+ i * CLUSTER_SIZE) + CR;
+
deployinfo =
+ deployinfo + "#define CACHED_RAM" + ram.getIndex () +
+ "_SIZE 0x" + string_size_half + CR;
+
deployinfo +=
+ "#define DEPLOY_RAM" + ram.getIndex () + "_NAME uram" +
+ ram.getIndex () + CR;
+
int cacheability_bit = 2097152; //0x00200000
+ deployinfo =
+ deployinfo + "#define DEPLOY_RAM" + ram.getIndex () +
+ "_ADDR 0x" + Integer.toHexString (address_start +
+ i * CLUSTER_SIZE +
+ size / 2 +
+ cacheability_bit) + CR;
+
+ // 31.08. simplifie
+ deployinfo =
+ deployinfo + "#define DEPLOY_RAM" + ram.getIndex () +
+ "_SIZE 0x" + (string_size_half) + CR;
+
i++;
+
}
+ //Calculate Adresses of MWMR segments, one for each hardware accellerator
+ i = 0;
+
for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
deployinfo =
+ deployinfo + "#define MWMR_RAM" + i + "_NAME mwmr_ram" + i +
+ CR;
+
deployinfo =
+ deployinfo + "#define MWMR_RAM" + i + "_ADDR 0xA02" +
+ Integer.toHexString (i * 4096) + CR;
+
deployinfo =
+ deployinfo + "#define MWMR_RAM" + i + "_SIZE 0x1000" + CR;
+
i++;
+
}
+
return deployinfo;
+
}
+
public static String getDeployInfoMap (AvatarSpecification _avspec)
+ {
+
avspec = _avspec;
+
int i = 0;
+
String deployinfo_map = CR;
+
int j;
+
deployinfo_map += "#define MAP_A\\" + CR;
+
try
+ {
+
for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
if (!(ram.getChannels ().isEmpty ()))
+ {
+
for (AvatarRelation ar:avspec.
+ getRelations
+ ())
+ {
+
for (j = 0; j < ar.nbOfSignals (); j++)
+ {
+
deployinfo_map =
+ deployinfo_map + "\n .channel" + i +
+ " : {";
+
deployinfo_map =
+ deployinfo_map + "*(section_channel" +
+ i + ")";
+
deployinfo_map = deployinfo_map + "} > uram" + ram.getIndex () + CR; //ram n° was incorrect (see above)
+ i++;
+
}
+
}
+
i = 0;
+
for (AvatarRelation ar:avspec.
+ getRelations
+ ())
+ {
+
for (j = 0; j < ar.nbOfSignals (); j++)
+ {
+
deployinfo_map =
+ deployinfo_map + "\n .lock" + i +
+ " : { ";
+
deployinfo_map =
+ deployinfo_map + "*(section_lock" +
+ i + ")";
+
deployinfo_map =
+ deployinfo_map + "} > uram" +
+ ram.getIndex () + CR;
+
i++;
+
}
+
}
+
}
+
}
+
}
+ catch (Exception e)
+ {
+
e.printStackTrace ();
+
}
+
return deployinfo_map;
+
}
+
public static String getDeployInfoRam (AvatarSpecification _avspec)
+ {
+
avspec = _avspec;
+
int i = 0;
+
int j;
+
String deployinfo_ram = CR;
+
try
+ {
+
for (AvatarRelation ar:avspec.getRelations ())
+ {
+
for (j = 0; j < ar.nbOfSignals (); j++)
+ {
+
deployinfo_ram +=
+ "#if defined(DEPLOY_RAM" + i + "_NAME)" + CR;
+
deployinfo_ram +=
+ "\tDEPLOY_RAM" + i +
+ "_NAME (RWAL) : ORIGIN = DEPLOY_RAM" + i +
+ "_ADDR, LENGTH = DEPLOY_RAM" + i + "_SIZE" + CR;
+
deployinfo_ram += "#endif" + CR;
+
deployinfo_ram +=
+ "#if defined(CACHED_RAM" + i + "_NAME)" + CR;
+
deployinfo_ram +=
+ "\tCACHED_RAM" + i +
+ "_NAME (RWAL) : ORIGIN = CACHED_RAM" + i +
+ "_ADDR, LENGTH = CACHED_RAM" + i + "_SIZE" + CR;
+
deployinfo_ram += "#endif" + CR;
+
i++;
+
}
+
}
+
}
+ catch (Exception e)
+ {
+
e.printStackTrace ();
+
}
+
return deployinfo_ram;
+
}
+
public static String getProcInfo ()
+ {
+
int i = 0;
+
String procinfo = "SOCLIB_CPU_COUNT = ";
+
for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+
i++;
+
}
+
procinfo += i + CR;
+
return procinfo;
+
}
+
public static String getNbProc ()
+ {
+
int i = 0;
+
String nbproc = "CONFIG_CPU_MAXCOUNT ";
+
for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+
i++;
+
}
+
nbproc += i + CR;
+
return nbproc;
+
}
+
}
+
+
diff --git a/src/main/java/ddtranslatorSoclib/Header.java b/src/main/java/ddtranslatorSoclib/Header.java
new file mode 100755
index 0000000000..6438da9703
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Header.java
@@ -0,0 +1,216 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.*; //DG 23.08.
+
+public class Header
+{
+
+ static private String header;
+ int nb_clusters = 5;
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ Header ()
+ {
+ }
+ public static String getHeader ()
+ {
+ int with_vgsb = TopCellGenerator.avatardd.getAllBus ().size ();
+
+ header =
+ "//-------------------------------Header------------------------------------"
+ + CR2 + "#include <iostream>" + CR + "#include <cstdlib>" + CR +
+ "#include <vector>" + CR + "#include <string>" + CR +
+ "#include <stdexcept>" + CR + "#include <cstdarg>" + CR2 +
+ "#define CONFIG_GDB_SERVER" + CR +
+ "#define CONFIG_SOCLIB_MEMCHECK" + CR2;
+
+ header = header + "#include \"iss_memchecker.h\"" + CR
+ + "#include \"gdbserver.h\"" + CR2
+ + "#include \"ppc405.h\"" + CR
+ + "#include \"niosII.h\"" + CR
+ + "#include \"mips32.h\"" + CR
+ + "#include \"arm.h\"" + CR
+ + "#include \"sparcv8.h\"" + CR
+ + "#include \"lm32.h\"" + CR2
+ + "#include \"mapping_table.h\"" + CR
+ + "#include \"vci_fdt_rom.h\"" + CR +
+ "#include \"vci_xcache_wrapper.h\"" + CR +
+ "#include \"vci_ram.h\"" + CR +
+ "#include \"vci_heterogeneous_rom.h\"" + CR +
+ "#include \"vci_multi_tty.h\"" + CR
+ //+ "#include \"vci_locks.h\"" + CR
+ + "#include \"vci_xicu.h\"" + CR + "#include \"vci_mwmr_stats.h\"" + CR; //DG 20.09.
+ if (with_vgsb > 0)
+ {
+ header += "#include \"vci_vgsb.h\"" + CR;
+ }
+ else
+ {
+ header += "#include \"vci_vgmn.h\"" + CR;
+ }
+ int with_hw_accellerator = 1; //DG 23.08. a la main
+ if (with_hw_accellerator > 0)
+ {
+ header += "#include \"mwmr_controller.h\"" + CR;
+ header += "#include \"vci_mwmr_controller.h\"" + CR;
+ }
+ //include statements for all coprocessors found
+ //The user must ensure that there is a SoCLib component corresponding to this coprocessor
+ // if (with_hw_accellerator>0){
+ //DG 23.08. actuellement il ne les trouve pas!
+ int hwas = 0;
+ header += "#include \"fifo_virtual_copro_wrapper.h\"" + CR;
+
+ for (AvatarCoproMWMR HWAccelerator:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+ // String name = HWAccelerator.getCoprocName();
+ // header +="#include \""+name+"\""+ CR;
+
+ //Per default for testing
+ // header +="#include \"input_coproc.h\""+ CR;
+ //header +="#include \"output_coproc.hh\""+ CR;
+
+ /* can be found in /users/outil/soc/soclib/soclib/module/internal_component/fifo* */
+ //header +="#include \"fifo_virtual_copro_wrapper.h\""+ CR;
+ if (HWAccelerator.getCoprocType () == 0)
+ {
+ header += "#include \"vci_input_engine.h\"" + CR;
+ header += "#include \"papr_slot.h\"" + CR;
+ header += "#include \"generic_fifo.h\"" + CR;
+ header += "#include \"network_io.h\"" + CR;
+ }
+ else
+ {
+ if (HWAccelerator.getCoprocType () == 1)
+ {
+ header += "#include \"vci_output_engine.h\"" + CR;
+ }
+
+
+ else
+ {
+ header += "#include \"my_hwa" + hwas + ".h\"" + CR;
+ hwas++;
+ }
+ }
+ // }
+ }
+ header += "#include \"vci_block_device.h\"" + CR
+ + "#include \"vci_simhelper.h\"" + CR +
+ "#include \"vci_fd_access.h\"" + CR +
+ "#include \"vci_ethernet.h\"" + CR +
+ "#include \"vci_rttimer.h\"" + CR + "#include \"vci_logger.h\"" +
+ CR + "#include \"vci_local_crossbar.h\"" + CR2;
+
+ header = header + "namespace {" + CR
+ + "std::vector<std::string> stringArray(" + CR
+ + " const char *first, ... )" + CR
+ + "{" + CR
+ + " std::vector<std::string> ret;" + CR
+ + " va_list arg;" + CR
+ + " va_start(arg, first);" + CR
+ + " const char *s = first;" + CR
+ + " while(s) {" + CR
+ + " ret.push_back(std::string(s));" + CR
+ +
+ " s = va_arg(arg, const char *);"
+ + CR + " };" + CR +
+ " va_end(arg);" + CR +
+ " return ret;" + CR +
+ "}" + CR2 +
+ "std::vector<int> intArray("
+ + CR +
+ " const int length, ... )"
+ + CR + "{" + CR +
+ " int i;" + CR +
+ " std::vector<int> ret;"
+ + CR +
+ " va_list arg;"
+ + CR +
+ " va_start(arg, length);"
+ + CR2 +
+ " for (i=0; i<length; ++i) {"
+ +
+ CR
+ +
+ " ret.push_back(va_arg(arg, int));"
+ +
+ CR
+ +
+ " };"
+ +
+ CR
+ +
+ " va_end(arg);"
+ + CR + " return ret;" + CR + "}" + CR + "}" + CR2;
+
+ header =
+ header + "using namespace soclib;" + CR +
+ "using common::IntTab;" + CR + "using common::Segment;";
+
+
+ if (TopCellGenerator.avatardd.getNbClusters () == 0)
+ {
+ header =
+ header + CR2 +
+ "static common::MappingTable maptab(32, IntTab(8), IntTab(8), 0xfff00000);";
+ }
+ else
+ {
+ header =
+ header + CR2 +
+ "static common::MappingTable maptab(32, IntTab(8,4), IntTab(8,4), 0xfff00000);";
+ }
+ return header;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/Loader.java b/src/main/java/ddtranslatorSoclib/Loader.java
new file mode 100755
index 0000000000..7f864733c6
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Loader.java
@@ -0,0 +1,182 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+/* authors: v1.0 Daniela GENIUS, Julien HENON 2015 */
+
+
+package ddtranslatorSoclib.toTopCell;
+import avatartranslator.AvatarRelation; //DG 23.06.
+import avatartranslator.AvatarSpecification; //DG 23.06.
+import ddtranslatorSoclib.AvatarChannel;
+
+public class Loader
+{
+ public static AvatarSpecification avspec;
+ static private String loader;
+ private final static String NAME_CLK = "signal_clk";
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public Loader (AvatarSpecification _avspec)
+ {
+
+ avspec = _avspec;
+ }
+
+ public static String getLoader (AvatarSpecification _avspec)
+ { //DG 23.06.
+ avspec = _avspec; //DG 23.06.
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+ //nb_clusters=2;
+
+ loader =
+ CR2 +
+ "//-------------------------Call Loader---------------------------------"
+ + CR2;
+ loader =
+ loader +
+ "std::cerr << \"caba-vgmn-mutekh_kernel_tutorial SoCLib simulator for MutekH\" << std::endl;"
+ + CR2;
+
+ loader = loader + "if ( (argc < 2) || ((argc % 2) == 0) ) {" + CR;
+
+ loader = loader + "exit(0); }" + CR;
+
+ loader = loader + " argc--;" + CR;
+ loader = loader + " argv++;" + CR2;
+ loader = loader + "bool heterogeneous = (argc > 2);" + CR2;
+
+ loader = loader + " for (int i = 0; i < (argc - 1); i += 2){" + CR;
+ loader = loader + " char *cpu_p = argv[i];" + CR;
+ loader = loader + " const char *kernel_p = argv[i+1];" + CR;
+ loader =
+ loader + " const char *arch_str = strsep(&cpu_p, \":\");" + CR;
+ loader = loader + " int count = cpu_p ? atoi(cpu_p) : 1;" + CR;
+
+ loader = loader + " common::Loader *text_ldr; " + CR;
+
+ loader = loader + " if (heterogeneous) {" + CR;
+ loader =
+ loader +
+ " text_ldr = new common::Loader(std::string(kernel_p) + \";.text\");"
+ + CR;
+ loader = loader + " text_ldr->memory_default(0x5a);;" + CR;
+ loader =
+ loader +
+ " data_ldr.load_file(std::string(kernel_p) + \";.rodata;.boot;.excep\");"
+ + CR;
+ loader = loader + " if (i == 0)" + CR;
+ loader =
+ loader +
+ " data_ldr.load_file(std::string(kernel_p) + \";.data;";
+ // We generated so far until arriving at first channel segment, if any
+ //current hypothesis : one segment per channel
+ int j = 0;
+ //for (AvatarChannel channel : TopCellGenerator.avatardd.getAllMappedChannels()) {
+ //DG 23.06. per signal!!hack pour l'instant
+ int i = 0;
+ //for (i=0;i<30;i++){
+
+ for (AvatarRelation ar:avspec.getRelations ())
+ {
+
+ for (i = 0; i < ar.nbOfSignals (); i++)
+ {
+
+ loader = loader + ".channel" + j + ";";
+ j++;
+ }
+ }
+ // We resume the generation of the fixed code
+ loader = loader + ".cpudata;.contextdata\");" + CR;
+ loader = loader + " } else {" + CR;
+ loader =
+ loader +
+ " text_ldr = new common::Loader(std::string(kernel_p));" + CR;
+ loader = loader + " text_ldr->memory_default(0x5a);" + CR;
+ loader =
+ loader + " data_ldr.load_file(std::string(kernel_p));" + CR;
+ loader = loader + " }" + CR2;
+
+ loader = loader + " common::Loader tools_ldr(kernel_p);" + CR;
+ loader = loader + " tools_ldr.memory_default(0x5a);" + CR2;
+
+ loader = loader + " for (int j = 0; j < count; j++) {" + CR;
+ loader = loader + " int id = cpus.size();" + CR;
+ loader =
+ loader +
+ " std::cerr << \"***\" << cpus.size() << std::endl;" + CR;
+
+ loader =
+ loader +
+ " CpuEntry *e = newCpuEntry(arch_str, id, text_ldr);" + CR;
+
+ loader = loader + " if (j == 0)" + CR;
+ loader = loader + " e->init_tools(tools_ldr);" + CR;
+
+ loader = loader + " e->cpu = e->new_cpu(e);" + CR;
+ loader = loader + " cpus.push_back(e);" + CR;
+ loader = loader + " }" + CR;
+ loader = loader + " }" + CR2;
+ int nb_tty = 1; //DG currently only one (multi) tty
+
+ if (nb_clusters == 0)
+ {
+ loader =
+ loader + " const size_t xicu_n_irq = " + (1 + nb_tty + 3) +
+ ";" + CR2;
+ }
+ else
+ {
+ loader =
+ loader + " const size_t xicu_n_irq = " +
+ (5 * nb_clusters) + ";" + CR2;
+ }
+ return loader;
+ }
+
+ String getNAME_CLK ()
+ {
+ return NAME_CLK;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/MappingTable.java b/src/main/java/ddtranslatorSoclib/MappingTable.java
new file mode 100755
index 0000000000..4af3f6f5ae
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/MappingTable.java
@@ -0,0 +1,465 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* this class produces the lines pertaining to the segment table. Except the segments containing CHANNEL channels and those corresponding to targets in shared memory, they need not be sepcified by the user of the deployment diagram */
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 - 2016 */
+
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+import ddtranslatorSoclib.*;
+import myutil.TraceManager;
+
+public class MappingTable
+{
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private static String mapping;
+
+ public static String getMappingTable ()
+ {
+ int l = 0;
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+ int nb_ram = TopCellGenerator.avatardd.getAllRAM ().size ();
+
+ TraceManager.addDev ("Number of clusters : " + nb_clusters);
+ if (nb_clusters == 0)
+ {
+ mapping =
+ CR2 +
+ "//-----------------------mapping table------------------------"
+ + CR2;
+ mapping = mapping + "// ppc segments" + CR2;
+
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetppc\", 0xffffff80, 0x0080, IntTab(1), true));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetnios\", 0x00802000, 0x1000, IntTab(1), true));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetzero\", 0x00000000, 0x1000, IntTab(1), true));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetmips\", 0xbfc00000, 0x1000, IntTab(1), true));"
+ + CR;
+
+ /*seven targets are fixed; target 3 to 6 are transparent and do not appear in the TTool deployment diagram:
+
+ Targets on RAM0 :
+ the text segment (target 0)
+ the reset segment (target 1)
+ the data segment (target 2)
+
+ Other targets :
+ the simhelper segment (target 3)
+ the icu segment (target 4)
+ the timer segment (target 5)
+ the fdt segment (target 6)
+
+ additional RAM segments (target 6+i)
+ tty segments (target 6+i+j)
+ fd access segment (target 6+i+j+1)
+ ethernet segment (target 6+i+j+2)
+ block device segment (target 6+i+j+3)
+ */
+
+ mapping += CR2 + "// RAM segments" + CR2;
+ mapping +=
+ "maptab.add(Segment(\"text\", 0x60000000, 0x00100000, IntTab(0), true));"
+ + CR;
+ mapping +=
+ "maptab.add(Segment(\"rodata\", 0x80000000, 0x01000000, IntTab(1), true));"
+ + CR;
+ mapping +=
+ "maptab.add(Segment(\"data\", 0x7f000000, 0x01000000, IntTab(2), false)); "
+ + CR2;
+
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"simhelper\", 0xd3200000, 0x00000100, IntTab(3), false));"
+ + CR;
+ mapping =
+ mapping +
+ " maptab.add(Segment(\"vci_xicu\", 0xd2200000, 0x00001000, IntTab(4), false));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_rttimer\", 0xd6000000, 0x00000100, IntTab(5), false));"
+ + CR2;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_fdt_rom\", 0xe0000000, 0x00001000, IntTab(6), false));"
+ + CR2;
+
+
+ int address_start = 268435456;
+ int j = 0;
+ int i = 0;
+ int size;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ // if no data size is given calculate default data size
+ if (ram.getDataSize () == 0)
+ {
+
+ if ((nb_clusters < 16)
+ || (TopCellGenerator.avatardd.getAllRAM ().
+ size () < 16))
+ {
+ size = 1073741824;
+ }
+ else
+ { //dimension segments to be smaller
+ size = 268435456;
+ }
+ }
+ else
+ {
+ size = ram.getDataSize ();
+ }
+ ram.setDataSize (size);
+
+ size = ram.getDataSize (); // this is the hardware RAM size
+
+ int step = 268435456;
+
+ int cacheability_bit = 2097152; //0x00200000
+
+ /* Boot Ram segments 0,1,2 */
+ if (ram.getNo_ram () == 0)
+ {
+ ram.setNo_target (2);
+
+ mapping +=
+ "maptab.add(Segment(\"cram" + ram.getNo_ram () +
+ "\", 0x" + Integer.toHexString (address_start +
+ i * step) +
+ ", 0x" +
+ Integer.toHexString (ram.getDataSize () / 2) +
+ ", IntTab(" + (ram.getNo_target ()) +
+ "), true));" + CR;
+ mapping +=
+ "maptab.add(Segment(\"uram" + ram.getNo_ram () +
+ "\", 0x" + Integer.toHexString (address_start +
+ i * step +
+ cacheability_bit
+ +
+ ram.
+ getDataSize () /
+ 2) + ", 0x" +
+ Integer.toHexString (ram.getDataSize () / 2) +
+ ", IntTab(" + (ram.getNo_target ()) +
+ "), false));" + CR;
+ i++;
+ }
+ else
+ {
+ ram.setNo_target (7 + j);
+
+ mapping +=
+ "maptab.add(Segment(\"cram" + ram.getNo_ram () +
+ "\", 0x" + Integer.toHexString (address_start +
+ i * step) +
+ ", 0x" +
+ Integer.toHexString (ram.getDataSize () / 2) +
+ ", IntTab(" + (ram.getNo_target ()) +
+ "), true));" + CR;
+ mapping +=
+ "maptab.add(Segment(\"uram" + ram.getNo_ram () +
+ "\", 0x" + Integer.toHexString (address_start +
+ i * step +
+ ram.
+ getDataSize () /
+ 2 +
+ cacheability_bit)
+ + " , 0x" +
+ Integer.toHexString (ram.getDataSize () / 2) +
+ ", IntTab(" + (ram.getNo_target ()) +
+ "), false));" + CR;
+ j++;
+ i++;
+ }
+ }
+ int m = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ /* we calculate the target number of one or several (multi-) ttys which come after the j rams and the 7 compulsory targets */
+ tty.setNo_target (7 + j);
+ /* we use a simple formula for calculating the TTY address in case of multiple (multi-) ttys */
+
+ /* attention this will not work for more than 10 TTYs */
+ mapping +=
+ "maptab.add(Segment(\"vci_multi_tty" + m +
+ "\" , 0xd" + tty.getNo_tty () +
+ "200000, 0x00000010, IntTab(" + tty.getNo_target () +
+ "), false));" + CR;
+
+ j++;
+ m++;
+ l = tty.getNo_target ();
+ }
+ // }
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_fd_access\", 0xd4200000, 0x00000100, IntTab("
+ + (l + 1) + "), false));" + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_ethernet\", 0xd5000000, 0x00000020, IntTab("
+ + (l + 2) + "), false));" + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("
+ + (l + 3) + "), false));" + CR2;
+
+ /* Experimental: tnstanciation of the MWMR wrappers for hardware accellerators */
+ /* The accelerators themselves are specifies on DIPLODOCUS level */
+ int count = l + 5;
+ int hwa_count = 0;
+ int nb_hwa = 0;
+ int MWMR_SIZE = 4096;
+ int MWMRd_SIZE = 12288;
+ // int MWMR_BASE=0xA0200000;
+ i = 0;
+ for (AvatarCoproMWMR MWMRwrapper:TopCellGenerator.
+ avatardd.getAllCoproMWMR
+ ())
+ {
+ nb_hwa++;
+ }
+
+ for (AvatarCoproMWMR MWMRwrapper:TopCellGenerator.
+ avatardd.getAllCoproMWMR
+ ())
+ {
+ mapping +=
+ "maptab.add(Segment(\"mwmr_ram" + hwa_count +
+ "\", 0xA0" + Integer.toHexString (2097152 +
+ MWMR_SIZE * i) +
+ ", 0x00001000, IntTab(" + count + "), false));" + CR;
+ mapping +=
+ "maptab.add(Segment(\"mwmrd_ram" + hwa_count +
+ "\", 0x20" + Integer.toHexString (2097152 +
+ MWMRd_SIZE * i) +
+ ", 0x00003000, IntTab(" + (count + nb_hwa) +
+ "), false));" + CR;
+ hwa_count++;
+ count += 1;
+ }
+ hwa_count = 0;
+
+ return mapping;
+ }
+
+ else
+ {
+ /* clustered version */
+
+ mapping =
+ CR2 +
+ "maptab.add(Segment(\"resetppc\", 0xffffff80, 0x0080, IntTab(0,1), true));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetnios\", 0x00802000, 0x1000, IntTab(0,1), true));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetzero\", 0x00000000, 0x1000, IntTab(0,1), true));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"resetmips\", 0xbfc00000, 0x1000, IntTab(0,1), true));"
+ + CR;
+
+ mapping += CR2 + "// RAM shared segments on cluster 0" + CR2;
+ mapping +=
+ "maptab.add(Segment(\"text\", 0x60000000, 0x00100000, IntTab(0,0), true));"
+ + CR;
+ mapping +=
+ "maptab.add(Segment(\"rodata\", 0x80000000, 0x01000000, IntTab(0,1), true));"
+ + CR;
+ mapping +=
+ "maptab.add(Segment(\"data\", 0x7f000000, 0x01000000, IntTab(0,2), false)); "
+ + CR2;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"simhelper\", 0x15200000, 0x00000100, IntTab(0,3), false));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_fdt_rom\", 0x16200000, 0x00001000, IntTab(0,4), false));"
+ + CR2;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_fd_access\", 0x17200000, 0x00000100, IntTab(0,5), false));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_ethernet\", 0x18200000, 0x00000020, IntTab(0,6), false));"
+ + CR;
+ mapping =
+ mapping +
+ "maptab.add(Segment(\"vci_block_device\", 0x19200000, 0x00000020, IntTab(0,7), false));"
+ + CR2;
+
+ int SEG_ICU_BASE = 285212672;
+ int SEG_ICU_SIZE = 20;
+
+ int NB_DMAS = 1;
+ int SEG_DMA_BASE = 304087040;
+ int SEG_DMA_SIZE = (NB_DMAS * 20);
+
+ int NB_TIMERS = 1;
+ int SEG_TIM_BASE = 318767104;
+ int SEG_TIM_SIZE = (NB_TIMERS * 16);
+
+ int SEG_TTY_BASE = 337641472;
+ int SEG_TTY_SIZE = 16;
+
+ int CLUSTER_SIZE;
+
+ //if the user does not specify the size, take default value
+ if (nb_clusters < 16)
+ {
+ CLUSTER_SIZE = 268435456;
+ }
+ else
+ {
+ CLUSTER_SIZE = 134217728;
+ } // to be refined, cf DSX -> dynamically adapt
+
+ /* RAM adresses always start at 0x10000000 decimal 268435456 */
+
+ int SEG_RAM_BASE = 268435456;
+ int cluster = 0;
+
+
+ mapping +=
+ "maptab.add(Segment(\"vci_xicu\",0x" +
+ Integer.toHexString (SEG_ICU_BASE) + ", 0x" +
+ Integer.toHexString (SEG_ICU_SIZE) +
+ ", IntTab(0,9), false));" + CR;
+
+ mapping +=
+ "maptab.add(Segment(\"dma\", 0x" +
+ Integer.toHexString (SEG_DMA_BASE) + ", 0x" +
+ Integer.toHexString (SEG_DMA_SIZE) +
+ ", IntTab(0,10), false));" + CR;
+
+ mapping +=
+ "maptab.add(Segment(\"vci_rttimer\", 0x" +
+ Integer.toHexString (SEG_TIM_BASE) + ", 0x" +
+ Integer.toHexString (SEG_TIM_SIZE) +
+ ", IntTab(0,11), true));" + CR;
+
+
+ int cacheability_bit = 2097152; //0x00200000
+
+ /* RAM base address is SEG_RAM_BASE + CLUSTER_NUMBER * CLUSTER_SIZE;
+ this is the memory space covered by the RAMs of a cluster */
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+ mapping +=
+ "maptab.add(Segment(\"cram" + ram.getNo_ram () +
+ "\", 0x" + Integer.toHexString (SEG_RAM_BASE +
+ ram.getNo_cluster () *
+ CLUSTER_SIZE) +
+ ", 0x" +
+ Integer.toHexString (ram.getDataSize () / 2) +
+ ", IntTab(" + ram.getNo_cluster () + "," +
+ (ram.getNo_target ()) + "), true));" + CR;
+
+ mapping +=
+ "maptab.add(Segment(\"uram" + ram.getNo_ram () +
+ "\", 0x" + Integer.toHexString (SEG_RAM_BASE +
+ ram.
+ getNo_cluster () *
+ CLUSTER_SIZE +
+ cacheability_bit) +
+ ", 0x" +
+ Integer.toHexString (ram.getDataSize () / 2) +
+ ", IntTab(" + ram.getNo_cluster () + "," +
+ (ram.getNo_target ()) + "), false));" + CR;
+ }
+
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ if (tty.getNo_cluster () == 0)
+ {
+ tty.setNo_target (10 + nb_ram);
+ }
+ else
+ {
+ tty.setNo_target (tty.getNo_cluster () + nb_ram);
+ }
+ mapping +=
+ "maptab.add(Segment(\"vci_multi_tty" +
+ tty.getIndex () + "\" , 0x" +
+ Integer.toHexString (SEG_TTY_BASE +
+ tty.getNo_cluster () *
+ CLUSTER_SIZE) +
+ ", 0x00000010, IntTab(" + tty.getNo_cluster () + "," +
+ (tty.getNo_target ()) + "), false));" + CR;
+ }
+
+ }
+ return mapping;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/NetList.java b/src/main/java/ddtranslatorSoclib/NetList.java
new file mode 100755
index 0000000000..950376763f
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/NetList.java
@@ -0,0 +1,881 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCPU;
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+
+public class NetList
+{
+ public static final String NAME_CLK = "signal_clk";
+ public static final String CR = "\n";
+ public static final String CR2 = "\n\n";
+ private static final String NAME_RST = "signal_resetn";
+ private static boolean tracing;
+
+ public static String getNetlist (String icn, boolean _tracing)
+ {
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+ int coproc_count = 0;
+
+ tracing = _tracing;
+
+ String netlist;
+
+ netlist =
+ CR2 +
+ "//------------------------------Netlist---------------------------------"
+ + CR2;
+
+ netlist = netlist + "// icu" + CR2;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));"
+ + CR2;
+
+ netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
+ netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");"
+ + CR;
+
+ netlist =
+ netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
+ CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");"
+ + CR2;
+ netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
+ netlist =
+ netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
+ netlist = netlist + " {" + CR;
+ netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
+ netlist =
+ netlist +
+ " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
+ netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
+ netlist = netlist + " }" + CR2;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
+ CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" +
+ CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());"
+ + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());"
+ + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist =
+ netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
+ netlist =
+ netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
+
+ netlist = netlist + "///////////////// cpus" + CR2;
+
+ netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
+ netlist =
+ netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
+ netlist = netlist + " // configure het_rom" + CR;
+ netlist =
+ netlist +
+ " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
+
+ netlist = netlist + " // add cpu node to device tree" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+ netlist =
+ netlist +
+ " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);"
+ + CR;
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+
+ netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
+ netlist = netlist + " }" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " vcihetrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcifdtrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcisimhelper.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirttimer.p_clk(signal_clk);" + CR;
+
+ netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcifdtrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcisimhelper.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirttimer.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
+
+ netlist = netlist + " vcifdtrom.p_vci(signal_vci_vcifdtrom);" + CR;
+ netlist = netlist + " vcirom.p_vci(signal_vci_vcirom);" + CR;
+ netlist =
+ netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
+ netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
+ netlist =
+ netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
+
+ if (icn == "vgmn")
+ {
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
+ netlist =
+ netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist =
+ netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist =
+ netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
+ netlist =
+ netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+ else
+ {
+ netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
+ netlist =
+ netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist =
+ netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist =
+ netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
+ netlist =
+ netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+
+ if (nb_clusters == 0)
+ {
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
+ }
+ }
+
+ /* clustered version */
+ /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster */
+ else
+ {
+ int i;
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ //target number for local cluster: this is set at avatardd creation
+ netlist =
+ netlist + "crossbar" + ram.getNo_cluster () +
+ ".p_to_target[" + ram.getNo_target () +
+ "](signal_vci_vciram" + ram.getIndex () + ");" + CR2;
+ }
+
+ /*convention for local target ids on cluster :
+ channel: 0
+ mwmr_ram: 1
+ mwmrd_ram: 2
+ locks: 3
+ ram: 4
+ tty: 5
+ */
+
+ }
+
+ if (nb_clusters == 0)
+ {
+
+ int l = 8; //number of last tty
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ int i;
+
+ for (i = 0; i < coproc_count; i++)
+ {
+
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+ else
+ { //vgsb
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ int i;
+ for (i = 0; i < coproc_count; i++)
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+
+ }
+ else
+ {
+ /* cluster */
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ }
+
+ netlist =
+ netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
+ netlist = netlist + "vcifdtrom.end_node();;" + CR2;
+
+ netlist = netlist + "// TTY netlist" + CR2;
+ int i = 0;
+
+ for (AvatarTTY tty:TopCellGenerator.avatardd.getAllTTY ())
+ {
+ netlist =
+ netlist + tty.getTTYName () + ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_vci(signal_vci_tty" + i +
+ ");" + CR2;
+ int no_irq_tty = 0;
+ if (nb_clusters == 0)
+ {
+
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" + i + "\");" +
+ CR2;
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" +
+ tty.getNo_tty () + "\");" + CR2;
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ }
+
+ //we have a clustered architecture: identify local crossbar
+ else
+ {
+ int j;
+ for (j = 0; j < nb_clusters; j++)
+ {
+ netlist =
+ netlist + "crossbar" + j + ".p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + j +
+ ");" + CR2;
+ //recalculate irq addresses, 5 devices generating irq per cluster
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" +
+ (tty.getNo_cluster () * 5) + "]);" + CR2;
+ }
+ }
+ i++;
+ //One ICU per cluster per default
+ no_irq_tty += 6; //if there is more than one tty, irq >5
+ }
+
+ //////////////// fdrom
+
+ netlist = netlist + "{" + CR2;
+ netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");"
+ + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");"
+ + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR;
+ netlist = netlist + "}" + CR2;
+
+ //////////////// ethernet
+
+ netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
+ netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// block device
+
+ netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
+ netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
+ netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// fd access
+ netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
+
+ netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
+ netlist =
+ netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR2;
+
+ i = 0;
+ int j = 0;
+
+ for (AvatarCoproMWMR copro:TopCellGenerator.
+ avatardd.getAllCoproMWMR ())
+ {
+
+ //IE and OE are special cases as they have VCI an fifo initiator interface
+
+ if (copro.getCoprocType () == 0)
+ {
+ i = 0;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_IE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_pktdesc[0](signal_fifo_" + j + "_" + i +
+ "_to_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_from_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_IE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_IE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_OE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_desc(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i + "_to_ctrl);" +
+ CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_to_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_OE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_OE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + "hwa" + i + ".p_from_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
+ netlist =
+ netlist + "hwa" + i + ".p_to_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
+ }
+
+
+ //additional interfaces for IE and OE
+
+ if (copro.getCoprocType () == 0)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //pktdesc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_from_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_IE_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_IE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //desc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_OE_to_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_OE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_target(signal_mwmr_" + i +
+ "_target);" + CR2;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_from_coproc[" + i +
+ "](signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_to_coproc[" + i + "](signal_fifo_" +
+ j + "_" + i + "_to_ctrl);" + CR;
+ }
+ i++;
+ }
+ j++;
+ coproc_count++;
+ }
+
+
+ //If there is a spy, add logger or stats to vci interface
+
+ i = 0;
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+ int number = cpu.getNo_proc ();
+ if (cpu.getMonitored () == 1)
+ {
+ netlist = netlist + CR +
+ "logger" + i + ".p_clk(signal_clk);" + CR +
+ "logger" + i + ".p_resetn(signal_resetn);" + CR +
+ "logger" + i + ".p_vci(signal_vci_m[" + number +
+ "]);" + CR2;
+ i++;
+ }
+
+ }
+ j = 0;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 1)
+ {
+ int number = number = ram.getIndex ();
+ netlist += "logger" + i + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "logger" + i + ".p_resetn(signal_resetn);" + CR;
+ netlist +=
+ "logger" + i + ".p_vci(signal_vci_vciram" + number +
+ ");" + CR2;
+ i++;
+ }
+ else
+ {
+
+ if (ram.getMonitored () == 2)
+ {
+ int number = number = ram.getIndex ();
+ netlist +=
+ "mwmr_stats" + j + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_vci(signal_vci_vciram" +
+ number + ");" + CR2;
+ j++;
+ }
+ }
+ }
+
+
+ int p = 0;
+
+ //generate trace file if marked trace option
+
+ if (tracing)
+ {
+ netlist += "sc_trace_file *tf;" + CR;
+ netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
+ netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
+ netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
+
+ netlist +=
+ "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" +
+ CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");"
+ + CR;
+
+ for (i = 0; i < TopCellGenerator.avatardd.getNb_init (); i++)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_m[" + i +
+ "] ,\"signal_vci_m[" + i + "]\");" + CR;
+ }
+
+ i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ netlist +=
+ "sc_trace(tf,signal_vci_tty" + tty.getNo_tty () +
+ ",\"TTY" + tty.getNo_tty () + "\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ i++;
+ }
+
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_vciram" +
+ ram.getIndex () + ",\"Memory" +
+ ram.getIndex () + "\");" + CR;
+ }
+ }
+ }
+ netlist =
+ netlist +
+ " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = false;" + CR;
+ netlist =
+ netlist +
+ " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = true;" + CR;
+ netlist = netlist + " sc_core::sc_start();" + CR;
+ if (tracing)
+ {
+ netlist += "sc_close_vcd_trace_file(tf);" + CR;
+ }
+ netlist = netlist + CR + " return EXIT_SUCCESS;" + CR;
+ netlist = netlist + "}" + CR;
+ return netlist;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/Platforminfo.java b/src/main/java/ddtranslatorSoclib/Platforminfo.java
new file mode 100755
index 0000000000..74f0d06090
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Platforminfo.java
@@ -0,0 +1,161 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* This class generates the platform_desc file t*/
+
+
+/* authors: v1.0 Daniela GENIUS august 2016 */
+
+package ddtranslatorSoclib.toTopCell;
+import ddtranslatorSoclib.*;
+
+public class Platforminfo
+{
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public static String getPlatformInfo ()
+ {
+ //determine if the platform is vgsb or vgmn based (mutually exclusive)
+ int with_vgsb = TopCellGenerator.avatardd.getAllBus ().size ();
+ int nb_hwa = TopCellGenerator.avatardd.getAllCoproMWMR ().size ();
+
+ //bus can be other than VGSB (CAN...), for the moment restricted to VGSB
+ String platforminfo = CR;
+ platforminfo += "use = [" + CR
+ // +"Uses('caba:vci_locks'),"+CR
+ + "Uses('caba:vci_ram')," + CR
+ + "Uses('caba:vci_fdt_rom')," + CR
+ + "Uses('caba:vci_heterogeneous_rom')," + CR
+ + "Uses('caba:vci_multi_tty')," + CR
+ + "Uses('caba:vci_xicu')," + CR
+ + "Uses('caba:vci_block_device')," + CR
+ + "Uses('caba:vci_ethernet')," + CR
+ + "Uses('caba:vci_rttimer')," + CR
+ + "Uses('caba:vci_fd_access')," + CR
+ + "Uses('caba:vci_simhelper')," + CR;
+
+ if (with_vgsb > 0)
+ {
+ platforminfo += "Uses('caba:vci_vgsb')," + CR;
+ }
+ else
+ {
+ platforminfo += "Uses('caba:vci_vgmn')," + CR;
+ }
+
+ //DG 23.08. added virtual coprocessor
+ platforminfo += "Uses('caba:vci_mwmr_stats')," + CR
+ + "Uses('caba:vci_logger')," + CR
+ + "Uses('caba:vci_local_crossbar')," + CR
+ + "Uses('caba:fifo_virtual_copro_wrapper')," + CR;
+
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+ if (copro.getCoprocType () == 0)
+ {
+ platforminfo += "Uses('caba:vci_input_engine')," + CR
+ + "Uses('common:papr_slot')," + CR
+ + "Uses('caba:generic_fifo')," + CR
+ + "Uses('common:network_io')," + CR;
+ nb_hwa--;
+ }
+
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ platforminfo +=
+ "Uses('caba:vci_output_engine')," + CR;
+ nb_hwa--;
+ }
+
+
+ else
+ {
+ int i;
+ for (i = 0; i < nb_hwa; i++)
+ {
+ platforminfo +=
+ "Uses('caba:my_hwa" + i + "')," + CR;
+ }
+ }
+ }
+ }
+
+ platforminfo += "Uses('common:elf_file_loader')," + CR
+ + "Uses('common:plain_file_loader')," + CR
+ +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:arm'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32eb'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32el'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:niosII'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:lm32'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=8),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=2),"
+ + CR + " ]" + CR2 + "todo = Platform('caba', 'top.cc'," + CR +
+ " uses=use," + CR + " cell_size = 4," + CR +
+ " plen_size = 9," + CR + " addr_size = 32," +
+ CR + " rerror_size = 1," + CR +
+ " clen_size = 1," + CR +
+ " rflag_size = 1," + CR +
+ " srcid_size = 8," +
+ CR +
+ " pktid_size = 1,"
+ + CR +
+ " trdid_size = 1,"
+ + CR + " wrplen_size = 1" + CR + ")" + CR2;
+
+ return platforminfo;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/Signal.java b/src/main/java/ddtranslatorSoclib/Signal.java
new file mode 100755
index 0000000000..b710f2ae17
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Signal.java
@@ -0,0 +1,280 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+/* This class generates the lines of the topcell where the signals are declared*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+
+public class Signal
+{
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private final static String NAME_CLK = "signal_clk";
+ private static final String NAME_RST = "signal_resetn";
+
+ public static String getSignal ()
+ {
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+
+ String signal =
+ CR2 +
+ "//-------------------------------signaux------------------------------------"
+ + CR2;
+
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];" + CR;
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");"
+ + CR;
+
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");"
+ + CR;
+ signal =
+ signal +
+ " caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");"
+ + CR;
+ signal =
+ signal +
+ " caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");"
+ + CR;
+ signal =
+ signal +
+ " caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");"
+ + CR;
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");"
+ + CR;
+
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_vci_vcifdaccessi;" +
+ CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_vci_vcifdaccesst;" +
+ CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_vci_bdi;" + CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_vci_bdt;" + CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_vci_etherneti;" + CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_vci_ethernett;" + CR;
+ signal = signal + "" + CR;
+ signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
+ signal =
+ signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" +
+ CR2;
+ int i = 0;
+
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
+ if (copro.getCoprocType () == 0)
+ {
+ signal =
+ signal +
+ "soclib::caba::VciSignals<vci_param> signal_vci_IE(\"signal_vci_IE\");"
+ + CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_mwmr_" +
+ i + "_initiator;" + CR;
+ signal =
+ signal + "caba::VciSignals<vci_param> signal_mwmr_" +
+ i + "_target;" + CR;
+ signal =
+ signal +
+ "soclib::caba::FifoSignals<uint32_t> signal_fifo_" +
+ i + "_0_from_ctrl;" + CR;
+ signal =
+ signal +
+ "soclib::caba::FifoSignals<uint32_t> signal_fifo_" +
+ i + "_1_from_ctrl;" + CR;
+ signal =
+ signal +
+ "sc_core::sc_signal<uint32_t> signal_IE_from_ctrl;" +
+ CR;
+ signal =
+ signal +
+ "soclib::caba::FifoSignals<uint32_t> signal_fifo_" +
+ i + "_0_to_ctrl;" + CR;
+ signal =
+ signal +
+ "sc_core::sc_signal<uint32_t> signal_IE_to_ctrl;" +
+ CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ signal =
+ signal +
+ "soclib::caba::VciSignals<vci_param> signal_vci_OE(\"signal_vci_OE\");"
+ + CR;
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_mwmr_" + i +
+ "_initiator;" + CR;
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_mwmr_" + i +
+ "_target;" + CR;
+ signal =
+ signal +
+ "soclib::caba::FifoSignals<uint32_t> signal_fifo_"
+ + i + "_0_from_ctrl;" + CR;
+ signal =
+ signal +
+ "sc_core::sc_signal<uint32_t> signal_OE_from_ctrl;"
+ + CR;
+ signal =
+ signal +
+ "soclib::caba::FifoSignals<uint32_t> signal_fifo_"
+ + i + "_0_to_ctrl;" + CR;
+ signal =
+ signal +
+ "soclib::caba::FifoSignals<uint32_t> signal_fifo_"
+ + i + "_1_to_ctrl;" + CR;
+ signal =
+ signal +
+ "sc_core::sc_signal<uint32_t> signal_OE_to_ctrl;"
+ + CR;
+ }
+
+ else
+ {
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_mwmr_" + i +
+ "_initiator;" + CR;
+ signal =
+ signal +
+ "caba::VciSignals<vci_param> signal_mwmr_" + i +
+ "_target;" + CR;
+ signal =
+ signal +
+ " soclib::caba::FifoSignals<uint32_t> signal_fifo_"
+ + i + "_from_ctrl;" + CR;
+ signal =
+ signal +
+ " soclib::caba::FifoSignals<uint32_t> signal_fifo_"
+ + i + "_to_ctrl;" + CR;
+ }
+
+ }
+ i++;
+ }
+
+ signal =
+ signal +
+ " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+
+
+
+ i = 0;
+ if (TopCellGenerator.avatardd.getAllCrossbar ().size () == 0)
+ {
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ signal =
+ signal +
+ "soclib::caba::VciSignals<vci_param> signal_vci_vciram"
+ + i + "(\"signal_vci_vciram" + i + "\");" + CR2;
+ i++;
+ }
+ i = 0;
+
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ signal =
+ signal +
+ "soclib::caba::VciSignals<vci_param> signal_vci_tty" +
+ i + "(\"signal_vci_tty" + i + "\");" + CR2;
+ i++;
+ }
+
+ }
+
+
+ else
+ {
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ signal =
+ signal +
+ "soclib::caba::VciSignals<vci_param> signal_vci_vciram"
+ + ram.getIndex () + "(\"signal_vci_vciram" +
+ ram.getIndex () + "\");" + CR2;
+ i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ signal =
+ signal +
+ "soclib::caba::VciSignals<vci_param> signal_vci_tty" +
+ i + "(\"signal_vci_tty" + i + "\");" + CR2;
+ i++;
+ }
+ int p = 0;
+
+ }
+
+ return signal;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/Simulation.java b/src/main/java/ddtranslatorSoclib/Simulation.java
new file mode 100755
index 0000000000..d77a47901b
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/Simulation.java
@@ -0,0 +1,118 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+import ddtranslatorSoclib.AvatarCoproMWMR; //DG 30.04.2018
+
+public class Simulation
+{
+
+ private static String simulation;
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public Simulation ()
+ {
+ }
+
+ public static String getSimulation ()
+ {
+ int network_io = 0;
+ simulation = CR;
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+ //a coprocessor with its FIFO interface built from HWA
+ /* netlist = netlist +"hwa"+i+".p_clk(signal_clk);" + CR;
+ netlist = netlist +"hwa"+i+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist +"hwa"+i+".p_from_ctrl["+i+"](signal_fifo_"+i+"_from_ctrl);" + CR;
+ netlist = netlist +"hwa"+i+".p_to_ctrl["+i+"](signal_fifo_"+i+"_to_ctrl);" + CR2; */
+
+
+ //IE and OE are special cases as they have VCI an fifo initiator interface!!!
+ // In that case, another main (for Network_IO) is substituted
+
+
+ if ((copro.getCoprocType () == 0)
+ || (copro.getCoprocType () == 1))
+ {
+ network_io = 1;
+ }
+ }
+
+ if ((network_io == 0))
+ {
+ simulation = CR2 + CR2 +
+ "/***************************************************************************"
+ + CR +
+ "----------------------------simulation-------------------------"
+ + CR +
+ "***************************************************************************/"
+ + CR2;
+ simulation =
+ simulation + "int sc_main (int argc, char *argv[])" + CR +
+ "{" + CR;
+ simulation =
+ simulation + " try {" + CR +
+ " return _main(argc, argv);" + CR + " }" + CR2;
+ simulation =
+ simulation + " catch (std::exception &e) {" + CR +
+ " std::cout << e.what() << std::endl;" + CR +
+ " throw;" + CR + " }";
+ simulation = simulation + " catch (...) {" + CR;
+ simulation =
+ simulation +
+ "std::cout << \"Unknown exception occured\" << std::endl;" +
+ CR;
+ simulation = simulation + "throw;" + CR;
+ simulation = simulation + "}" + CR;
+ simulation = simulation + CR + " return 1;" + CR + "}";
+
+ }
+ return simulation;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/TopCellGenerator.java b/src/main/java/ddtranslatorSoclib/TopCellGenerator.java
new file mode 100755
index 0000000000..2130ffd64a
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/TopCellGenerator.java
@@ -0,0 +1,363 @@
+
+/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ Daniela Genius, Lip6, UMR 7606
+
+ ludovic.apvrille AT enst.fr
+ daniela.genius@lip6.fr
+
+ This software is a computer program whose purpose is to allow the
+ edition of TURTLE analysis, design and deployment diagrams, to
+ allow the generation of RT-LOTOS or Java code from this diagram,
+ and at last to allow the analysis of formal validation traces
+ obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ from INRIA Rhone-Alpes.
+
+ This software is governed by the CeCILL license under French law and
+ abiding by the rules of distribution of free software. You can use,
+ modify and/ or redistribute the software under the terms of the CeCILL
+ license as circulated by CEA, CNRS and INRIA at the following URL
+ "http://www.cecill.info".
+
+ As a counterpart to the access to the source code and rights to copy,
+ modify and redistribute granted by the license, users are provided only
+ with a limited warranty and the software's author, the holder of the
+ economic rights, and the successive licensors have only limited
+ liability.
+
+ In this respect, the user's attention is drawn to the risks associated
+ with loading, using, modifying and/or developing or reproducing the
+ software by the user in light of its specific status of free software,
+ that may mean that it is complicated to manipulate, and that also
+ therefore means that it is reserved for developers and experienced
+ professionals having in-depth computer knowledge. Users are therefore
+ encouraged to load and test the software's suitability as regards their
+ requirements in conditions enabling the security of their systems and/or
+ data to be ensured and, more generally, to use and operate it in the
+ same conditions as regards security.
+
+ The fact that you are presently reading this means that you have had
+ knowledge of the CeCILL license and that you accept its terms.
+*/
+
+/* Generator of the top cell for simulation with SoCLib virtual component
+ library */
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarSpecification;
+import ddtranslatorSoclib.*;
+import ddtranslatorSoclib.toSoclib.*;
+
+import java.io.*;
+import java.util.ArrayList;
+import java.util.List;
+import myutil.TraceManager;
+
+public class TopCellGenerator
+{
+ private static final String MAPPING_TXT = "mapping.txt"; //$NON-NLS-1$
+ //--------------- accessing Avatardd -----------------
+ public static AvatarddSpecification avatardd;
+ // ---------------------------------------------------
+
+ public static AvatarSpecification avspec;
+
+ public String VCIparameters;
+ public String config;
+ public String mainFile;
+ public String src;
+ public String top;
+ public String deployinfo;
+ public String deployinfo_map;
+ public String deployinfo_ram;
+ public String platform_desc;
+ public String procinfo;
+ public String nbproc;
+ public final String DOTH = ".h";
+ public final String DOTCPP = ".cpp";
+ public final String SYSTEM_INCLUDE = "#include \"systemc.h\"";
+ public final String CR = "\n";
+ public final String CR2 = "\n\n";
+ public final String SCCR = ";\n";
+ public final String EFCR = "}\n";
+ public final String EFCR2 = "}\n\n";
+ public final String EF = "}";
+ public final String COTE = "";
+ public final String NAME_RST = "signal_resetn";
+ public final String TYPEDEF = "typedef";
+
+ private final static String GENERATED_PATH =
+ "generated_topcell" + File.separator;
+ private boolean tracing;
+ public TopCellGenerator (AvatarddSpecification dd, boolean _tracing,
+ AvatarSpecification _avspec)
+ {
+ avatardd = dd;
+ tracing = _tracing;
+ avspec = _avspec;
+ }
+
+ public String generateTopCell ()
+ {
+ String icn;
+
+ /* first test validity of the hardware platform */
+ if (TopCellGenerator.avatardd.getNbCPU () == 0)
+ {
+ TraceManager.addDev ("***Warning: require at least one CPU***");
+ }
+ if (TopCellGenerator.avatardd.getNbRAM () == 0)
+ {
+ TraceManager.addDev ("***Warning: require at least one RAM***");
+ }
+ if (TopCellGenerator.avatardd.getNbTTY () == 0)
+ {
+ TraceManager.addDev ("***Warning: require at least one TTY***");
+ }
+ /* if there is one VGMN, this is the central interconnect */
+ if (TopCellGenerator.avatardd.getNbVgmn () > 1)
+ {
+ TraceManager.
+ addDev ("***Warning: No more than one central VGMN***");
+ }
+ if (TopCellGenerator.avatardd.getNbVgmn () == 1)
+ {
+ TraceManager.addDev ("***VGMN based***");
+ icn = "vgmn";
+ }
+ else
+ {
+ TraceManager.addDev ("***VGSB based ***");
+ icn = "vgsb";
+ }
+
+ // If there is a spy, add spy component to vci interface;
+ // both adjacent componants are spied.
+ // Currently for CPU and RAM only.
+ // RAM monitoring is required for determining the buffer size and
+ // various infos on MWMR channels
+ // RAM and CPU monitoring are for required for determining latency
+ // of memory accesses other than channel
+
+ for (AvatarConnector connector:avatardd.getConnectors ())
+ {
+
+ AvatarConnectingPoint my_p1 = connector.get_p1 ();
+ AvatarConnectingPoint my_p2 = connector.get_p2 ();
+
+ //If a spy glass symbol is found, and component itself not yet marked
+
+ AvatarComponent comp1 = my_p1.getComponent ();
+ AvatarComponent comp2 = my_p2.getComponent ();
+
+ if (connector.getMonitored () == 1)
+ {
+ //comp2 devrait toujours etre un interconnect
+ if (comp1 instanceof AvatarRAM)
+ {
+ AvatarRAM comp1ram = (AvatarRAM) comp1;
+ TraceManager.addDev ("RAM monitored " +
+ comp1ram.getMonitored ());
+
+ }
+
+ if (comp1 instanceof AvatarCPU)
+ {
+ AvatarCPU comp1cpu = (AvatarCPU) comp1;
+ TraceManager.addDev ("CPU monitored " +
+ comp1cpu.getMonitored ());
+
+ }
+
+ /* if (comp2 instanceof AvatarRAM){
+ AvatarRAM comp2ram = (AvatarRAM)comp1;
+ TraceManager.addDev("RAM2 topcell monitored "+comp2ram.getMonitored());
+ comp2ram.setMonitored(comp2ram.getMonitored());
+ }
+
+ if (comp2 instanceof AvatarCPU){
+ AvatarCPU comp2cpu = (AvatarCPU)comp2;
+ TraceManager.addDev("CPU2 topcell monitored "+comp2cpu.getMonitored());
+ comp2cpu.setMonitored(comp2cpu.getMonitored());
+ } */
+ }
+ }
+
+ /* Central interconnect or local crossbars */
+
+ if (TopCellGenerator.avatardd.getNbCrossbar () > 0)
+ {
+ TraceManager.addDev ("***Clustered Interconnect***");
+ }
+ makeVCIparameters ();
+ makeConfig ();
+ String top = Header.getHeader () +
+ VCIparameters +
+ config +
+ Code.getCode () +
+ MappingTable.getMappingTable () +
+ Loader.getLoader (avspec) +
+ Declaration.getDeclarations (avspec) +
+ Signal.getSignal () +
+ NetList.getNetlist (icn, tracing) + Simulation.getSimulation ();
+ return (top);
+ }
+
+ public List < String > readInMapping ()
+ {
+ List < String > mappingLines = new ArrayList < String > ();
+ try
+ {
+ BufferedReader in =
+ new BufferedReader (new FileReader (MAPPING_TXT));
+ String line = null;
+ while ((line = in.readLine ()) != null)
+ {
+ TraceManager.addDev (" Line read : " + line);
+ mappingLines.add (line);
+ }
+ in.close ();
+ }
+ catch (IOException e)
+ {
+ e.printStackTrace ();
+ }
+
+ return mappingLines;
+ }
+
+ public void saveFile (String path)
+ {
+ try
+ {
+
+ FileWriter fw =
+ new FileWriter (path + GENERATED_PATH + "/top.cc");
+ top = generateTopCell ();
+ fw.write (top);
+ fw.close ();
+ } catch (IOException ex)
+ {
+ }
+ saveFileDeploy (path);
+ saveFilePlatform (path);
+ saveFileProcinfo (path);
+ saveFileNBproc (path);
+ }
+
+ public void saveFileDeploy (String path)
+ {
+
+ try
+ {
+
+ FileWriter fw =
+ new FileWriter (path + GENERATED_PATH + "/deployinfo.h");
+ deployinfo = Deployinfo.getDeployInfo ();
+ fw.write (deployinfo);
+ fw.close ();
+
+
+ FileWriter fw_map =
+ new FileWriter (path + GENERATED_PATH + "/deployinfo_map.h");
+ deployinfo_map = Deployinfo.getDeployInfoMap (avspec);
+ fw_map.write (deployinfo_map);
+ fw_map.close ();
+
+ FileWriter fw_ram =
+ new FileWriter (path + GENERATED_PATH + "/deployinfo_ram.h");
+ deployinfo_ram = Deployinfo.getDeployInfoRam (avspec);
+ fw_ram.write (deployinfo_ram);
+ fw_ram.close ();
+ } catch (Exception ex)
+ {
+ ex.printStackTrace ();
+ }
+ }
+
+ public void saveFileProcinfo (String path)
+ {
+
+ try
+ {
+
+ FileWriter fw =
+ new FileWriter (path + GENERATED_PATH + "/procinfo.mk");
+ procinfo = Deployinfo.getProcInfo ();
+ fw.write (procinfo);
+ fw.close ();
+ } catch (IOException ex)
+ {
+ }
+ }
+
+ public void saveFileNBproc (String path)
+ {
+
+ try
+ {
+
+ FileWriter fw =
+ new FileWriter (path + GENERATED_PATH + "/nbproc");
+ nbproc = Deployinfo.getNbProc ();
+ fw.write (nbproc);
+ fw.close ();
+ } catch (IOException ex)
+ {
+ }
+ }
+
+ public void saveFilePlatform (String path)
+ {
+
+ try
+ {
+
+ FileWriter fw =
+ new FileWriter (path + GENERATED_PATH + "/platform_desc");
+ platform_desc = Platforminfo.getPlatformInfo ();
+ fw.write (platform_desc);
+ fw.close ();
+ } catch (IOException ex)
+ {
+ }
+ }
+
+ public void makeVCIparameters ()
+ {
+ VCIparameters =
+ CR2 + "typedef caba::VciParams<4,9,32,1,1,1,8,1,1,1> vci_param;";
+ VCIparameters =
+ VCIparameters + "// Define our VCI parameters" + CR2 +
+ "struct CpuEntry;" + CR2;
+ }
+
+ public void makeConfig ()
+ {
+ config = CR2 + "#if defined(CONFIG_GDB_SERVER)" + CR;
+ config = config + "# if defined(CONFIG_SOCLIB_MEMCHECK)" + CR;
+ config = config + "# warning Using GDB and memchecker" + CR;
+ config =
+ config +
+ "# define ISS_NEST(T) common::GdbServer<common::IssMemchecker<T> >"
+ + CR;
+ config = config + "# else" + CR;
+ config = config + "# warning Using GDB" + CR;
+ config = config + "# define ISS_NEST(T) common::GdbServer<T>" + CR;
+ config = config + "# endif" + CR;
+ config = config + "#elif defined(CONFIG_SOCLIB_MEMCHECK)" + CR;
+ config = config + "# warning Using Memchecker" + CR;
+ config =
+ config +
+ "# define ISS_NEST(T) common::GdbServer<common::IssMemchecker<T> "
+ + CR;
+ config = config + "#else" + CR;
+ config = config + "# warning Using raw processor" + CR;
+ config = config + "# define ISS_NEST(T) T" + CR;
+ config = config + "#endif" + CR;
+ }
+}
diff --git a/src/main/java/ui/AvatarDeploymentPanelTranslator.java b/src/main/java/ui/AvatarDeploymentPanelTranslator.java
index 77f43a74d4..b386c6dc8e 100644
--- a/src/main/java/ui/AvatarDeploymentPanelTranslator.java
+++ b/src/main/java/ui/AvatarDeploymentPanelTranslator.java
@@ -38,7 +38,7 @@
-
+
package ui;
import ddtranslatorSoclib.*;
@@ -53,325 +53,416 @@ import java.util.*;
* Creation: 04/06/2015
* @version 2.0 01/03/2017
*/
-public class AvatarDeploymentPanelTranslator {
-
- private int nb_init = 0;
-
- /*
- * there are seven targets which are fixed but which are invisible to the user of thr TTool deployment diagram) :
- *
- * Targets on RAM0 :
- * the text segment (target 0)
- * the reset segment (target 1)
- * the data segment (target 2)
- *
- * Other targets :
- * the simhelper segment (target 3)
- * the icu segment (target 4)
- * the timer segment (target 5)
- * the fdt segment (target 6)
- *
- * There always is a RAM0
- */
-
- private int nb_target = 6;
-
- private int no_tty = 0;
-
- private int nb_clusters = 0;
- private List<TGComponent> tgcComponents;
-
- private List<AvatarComponent> avatarComponents;
- private List<AvatarConnector> avatarConnectors;
- private List<AvatarMappedObject> avatarMappedObject;
-
- public AvatarDeploymentPanelTranslator(ADDDiagramPanel _avatarddDiagramPanel) {
- tgcComponents = _avatarddDiagramPanel.getComponentList();
-
- avatarComponents = new LinkedList<AvatarComponent>();
- avatarConnectors = new LinkedList<AvatarConnector>();
- avatarMappedObject = new LinkedList<AvatarMappedObject>();
-
- MakeListOfComponentAndMappedObject(_avatarddDiagramPanel);
- }
-
- private void MakeListOfComponentAndMappedObject(ADDDiagramPanel avatarddDiagramPanel) {
-
- Map<TGComponent, AvatarComponent> avatarMap = new HashMap<TGComponent, AvatarComponent>();
-
- for (TGComponent dp : tgcComponents) {
- if (dp instanceof ADDCPUNode) {
- ADDCPUNode addCPUNode = (ADDCPUNode) dp;
- String cpuName = addCPUNode.getNodeName();
- int nbOfIRQs = addCPUNode.getNbOfIRQs();
- int ICacheWays = addCPUNode.getICacheWays();
- int ICacheSets = addCPUNode.getICacheSets();
- int ICacheWords = addCPUNode.getICacheWords();
- int dCacheWays = addCPUNode.getDCacheWays();
- int dCacheSets = addCPUNode.getDCacheSets();
- int dCacheWords = addCPUNode.getDCacheWords();
- AvatarCPU avcpu;
- //int monitored = addCPUNode.getMonitored();
-
- avcpu = new AvatarCPU(cpuName, nbOfIRQs, ICacheWays, ICacheSets, ICacheWords, dCacheWays, dCacheSets, dCacheWords, nb_init, addCPUNode.getIndex(), addCPUNode.getMonitored());
-
-
-
- Vector<ADDBlockArtifact> tasks = addCPUNode.getArtifactList();
-
- for (int i = 0; i < tasks.size(); i++) {
- ADDBlockArtifact task = tasks.get(i);
-
- String taskName = task.getTaskName();
- String referenceTaskName = task.getReferenceTaskName();
-
- AvatarTask avtask = new AvatarTask(taskName, referenceTaskName, avcpu, null);
-
- avcpu.addTask(avtask);
- avatarMappedObject.add(avtask);
- }
- nb_init++;
-
- avatarMap.put(dp, avcpu);
- avatarComponents.add(avcpu);
-
- } else if (dp instanceof ADDTTYNode) {
- ADDTTYNode tty = (ADDTTYNode) dp;
-
- int index = tty.getIndex();
- String ttyName = tty.getNodeName();
-
- AvatarTTY avtty = new AvatarTTY(ttyName, index, index, index);//DG 3.7.
- nb_target++;
-
- avatarMap.put(dp, avtty);
- avatarComponents.add(avtty);
-
- } else if (dp instanceof ADDBridgeNode) {
- ADDBridgeNode bridge = (ADDBridgeNode) dp;
-
- String bridgeName = bridge.getNodeName();
- AvatarBridge avbridge = new AvatarBridge(bridgeName);
-
- avatarMap.put(dp, avbridge);
- avatarComponents.add(avbridge);
-
- } else if (dp instanceof ADDBusNode) {
-
- ADDBusNode bus = (ADDBusNode) dp;
-
- String busName = bus.getNodeName();
- int nbOfAttachedInitiators = bus.getNbOfAttachedInitiators();
- int nbOfAttachedTargets = bus.getNbOfAttachedTargets();
- int fifoDepth = bus.getFifoDepth();
- int minLatency = bus.getMinLatency();
-
- AvatarBus avbus = new AvatarBus(busName, nbOfAttachedInitiators, nbOfAttachedTargets, fifoDepth, minLatency);
- avatarMap.put(dp, avbus);
- avatarComponents.add(avbus);
-
- } else if (dp instanceof ADDVgmnNode) {
-
- ADDVgmnNode vgmn = (ADDVgmnNode) dp;
-
- String vgmnName = vgmn.getNodeName();
- int nbOfAttachedInitiators = vgmn.getNbOfAttachedInitiators();
- int nbOfAttachedTargets = vgmn.getNbOfAttachedTargets();
- int fifoDepth = vgmn.getFifoDepth();
- int minLatency = vgmn.getMinLatency();
-
- AvatarVgmn avvgmn = new AvatarVgmn(vgmnName, nbOfAttachedInitiators, nbOfAttachedTargets, fifoDepth, minLatency);
- avatarMap.put(dp, avvgmn);
- avatarComponents.add(avvgmn);
-
- } else if (dp instanceof ADDCrossbarNode) {
-
- ADDCrossbarNode crossbar = (ADDCrossbarNode) dp;
-
- String crossbarName = crossbar.getNodeName();
- // int nbOfAttachedInitiators = crossbar.getNbOfAttachedInitiators();
- int nbOfAttachedInitiators = 0;
-
- // int nbOfAttachedTargets = crossbar.getNbOfAttachedTargets();
-
- int nbOfAttachedTargets = 0;
-
- int cluster_index = crossbar.getClusterIndex();
- int cluster_address = crossbar.getClusterAddress();
-
- AvatarCrossbar avcrossbar = new AvatarCrossbar(crossbarName, nbOfAttachedInitiators, nbOfAttachedTargets, cluster_index, cluster_address);
- nb_clusters++;
-
- avatarMap.put(dp, avcrossbar);
- avatarComponents.add(avcrossbar);
- } else if (dp instanceof ADDICUNode) {
-
- ADDICUNode icu = (ADDICUNode) dp;
-
- String ICUName = icu.getNodeName();
- int index = icu.getIndex();
- int nbIRQ = icu.getNIrq();
-
- AvatarICU avicu = new AvatarICU(ICUName, index, nbIRQ);
- avatarMap.put(dp, avicu);
- avatarComponents.add(avicu);
-
- } else if (dp instanceof ADDTimerNode) {
- ADDTimerNode timer = (ADDTimerNode) dp;
-
- String timerName = timer.getNodeName();
- int nIrq = timer.getNIrq();
- int index = timer.getIndex();
-
- AvatarTimer avtimer = new AvatarTimer(timerName, index, nIrq);
- avatarMap.put(dp, avtimer);
- avatarComponents.add(avtimer);
-
- } else if (dp instanceof ADDCoproMWMRNode) {
-
- ADDCoproMWMRNode addCoproMWMRNode = (ADDCoproMWMRNode) dp;
-
- String timerName = addCoproMWMRNode.getNodeName();
- int srcid = addCoproMWMRNode.getSrcid(); // initiator id
- int tgtid = addCoproMWMRNode.getTgtid(); // target id
- int plaps = addCoproMWMRNode.getPlaps(); // configuration of integrated timer
- int fifoToCoprocDepth = addCoproMWMRNode.getFifoToCoprocDepth();
- int fifoFromCoprocDepth = addCoproMWMRNode.getFifoFromCoprocDepth();
- int nToCopro = addCoproMWMRNode.getNToCopro(); // Nb of channels going to copro
- int nFromCopro = addCoproMWMRNode.getNFromCopro(); // Nb of channels coming from copro
- int nConfig = addCoproMWMRNode.getNConfig(); // Nb of configuration registers
- int nStatus = addCoproMWMRNode.getNStatus(); // nb of status registers
- boolean useLLSC = addCoproMWMRNode.getUseLLSC(); // more efficient protocol. 0: not used. 1 or more -> used
- int coprocType = addCoproMWMRNode.getCoprocType(); //virtual or real?
- nb_init++;
- nb_target+=2;//DG 28.08. two targets as two segments of memory are created mwmr and mwmrd
- AvatarCoproMWMR acpMWMR;
-
- //DG 19.09. map tasks to coproc
- acpMWMR = new AvatarCoproMWMR(timerName, srcid, srcid, tgtid, plaps, fifoToCoprocDepth, fifoFromCoprocDepth, nToCopro, nFromCopro, nConfig, nStatus, useLLSC, coprocType);
- // DG 27.04. : pourquoi deux fois new coproc? Bien: on peut mapper les tasks :)
-
- Vector<ADDBlockArtifact> tasks = addCoproMWMRNode.getArtifactList();
-
- for (int i = 0; i < tasks.size(); i++) {
-
- ADDBlockArtifact task = tasks.get(i);
-
- String taskName = task.getTaskName();
- String referenceTaskName = task.getReferenceTaskName();
-
- AvatarTask avtask = new AvatarTask(taskName, referenceTaskName, null, acpMWMR);
-
- acpMWMR.addTask(avtask);
- avatarMappedObject.add(avtask);
- //avtask.setAvatarCoprocReference(acpMWMR);
- }
- nb_init++;
- acpMWMR = new AvatarCoproMWMR(timerName, srcid, srcid, tgtid, plaps, fifoToCoprocDepth, fifoFromCoprocDepth, nToCopro, nFromCopro, nConfig, nStatus, useLLSC, coprocType);
-
- avatarMap.put(dp, acpMWMR);
- avatarComponents.add(acpMWMR);
-
- } else if (dp instanceof ADDMemoryNode) {
-
- if (dp instanceof ADDRAMNode) {
-
- ADDRAMNode addRamNode = (ADDRAMNode) dp;
- String name = addRamNode.getNodeName();
- int index = addRamNode.getIndex();
- int byteDataSize = addRamNode.getDataSize();
-
- //int monitored = addRamNode.getMonitored();
-
- AvatarRAM avram = new AvatarRAM(name, index, byteDataSize, index, index, addRamNode.getMonitored());//DG 3.7.
- avram.setNo_ram(index);
- int cluster_index = avram.getIndex();
-
- // no_ram++;
- nb_target++;
-
- Vector<ADDChannelArtifact> channels = addRamNode.getArtifactList();
- for (int i = 0; i < channels.size(); i++) {
- ADDChannelArtifact c = channels.get(i);
-
- String referenceDiagram = c.getReferenceDiagram();
- String channelName = c.getChannelName();
- //channel is inevitably on same cluster as RAM it is mapped on :)
- AvatarChannel avcl = new AvatarChannel(referenceDiagram, channelName, avram, cluster_index, addRamNode.getMonitored());
- avram.addChannel(avcl);
- avatarMappedObject.add(avcl);
- }
- avatarMap.put(dp, avram);
- avatarComponents.add(avram);
- }
- }
+public class AvatarDeploymentPanelTranslator
+{
+
+ private int nb_init = 0;
+
+ /*
+ * there are seven targets which are fixed but which are invisible to the user of thr TTool deployment diagram) :
+ *
+ * Targets on RAM0 :
+ * the text segment (target 0)
+ * the reset segment (target 1)
+ * the data segment (target 2)
+ *
+ * Other targets :
+ * the simhelper segment (target 3)
+ * the icu segment (target 4)
+ * the timer segment (target 5)
+ * the fdt segment (target 6)
+ *
+ * There always is a RAM0
+ */
+
+ private int nb_target = 6;
+
+ private int no_tty = 0;
+
+ private int nb_clusters = 0;
+ private List < TGComponent > tgcComponents;
+
+ private List < AvatarComponent > avatarComponents;
+ private List < AvatarConnector > avatarConnectors;
+ private List < AvatarMappedObject > avatarMappedObject;
+
+ public AvatarDeploymentPanelTranslator (ADDDiagramPanel
+ _avatarddDiagramPanel)
+ {
+ tgcComponents = _avatarddDiagramPanel.getComponentList ();
+
+ avatarComponents = new LinkedList < AvatarComponent > ();
+ avatarConnectors = new LinkedList < AvatarConnector > ();
+ avatarMappedObject = new LinkedList < AvatarMappedObject > ();
+
+ MakeListOfComponentAndMappedObject (_avatarddDiagramPanel);
+ }
+
+ private void MakeListOfComponentAndMappedObject (ADDDiagramPanel
+ avatarddDiagramPanel)
+ {
+
+ Map < TGComponent, AvatarComponent > avatarMap =
+ new HashMap < TGComponent, AvatarComponent > ();
+
+ for (TGComponent dp:tgcComponents)
+ {
+ if (dp instanceof ADDCPUNode)
+ {
+ ADDCPUNode addCPUNode = (ADDCPUNode) dp;
+ String cpuName = addCPUNode.getNodeName ();
+ int nbOfIRQs = addCPUNode.getNbOfIRQs ();
+ int ICacheWays = addCPUNode.getICacheWays ();
+ int ICacheSets = addCPUNode.getICacheSets ();
+ int ICacheWords = addCPUNode.getICacheWords ();
+ int dCacheWays = addCPUNode.getDCacheWays ();
+ int dCacheSets = addCPUNode.getDCacheSets ();
+ int dCacheWords = addCPUNode.getDCacheWords ();
+ AvatarCPU avcpu;
+ //int monitored = addCPUNode.getMonitored();
+
+ avcpu =
+ new AvatarCPU (cpuName, nbOfIRQs, ICacheWays,
+ ICacheSets, ICacheWords, dCacheWays,
+ dCacheSets, dCacheWords, nb_init,
+ addCPUNode.getIndex (),
+ addCPUNode.getMonitored ());
+
+
+ Vector < ADDBlockArtifact > tasks =
+ addCPUNode.getArtifactList ();
+
+ for (int i = 0; i < tasks.size (); i++)
+ {
+ ADDBlockArtifact task = tasks.get (i);
+
+ String taskName = task.getTaskName ();
+ String referenceTaskName =
+ task.getReferenceTaskName ();
+
+ AvatarTask avtask =
+ new AvatarTask (taskName, referenceTaskName,
+ avcpu, null);
+
+ avcpu.addTask (avtask);
+ avatarMappedObject.add (avtask);
+ }
+ nb_init++;
+
+ avatarMap.put (dp, avcpu);
+ avatarComponents.add (avcpu);
+
+ }
+ else if (dp instanceof ADDTTYNode)
+ {
+ ADDTTYNode tty = (ADDTTYNode) dp;
+
+ int index = tty.getIndex ();
+ String ttyName = tty.getNodeName ();
+
+ AvatarTTY avtty = new AvatarTTY (ttyName, index, index, index); //DG 3.7.
+ nb_target++;
+
+ avatarMap.put (dp, avtty);
+ avatarComponents.add (avtty);
+
+ }
+ else if (dp instanceof ADDBridgeNode)
+ {
+ ADDBridgeNode bridge = (ADDBridgeNode) dp;
+
+ String bridgeName = bridge.getNodeName ();
+ AvatarBridge avbridge = new AvatarBridge (bridgeName);
+
+ avatarMap.put (dp, avbridge);
+ avatarComponents.add (avbridge);
+
+ }
+ else if (dp instanceof ADDBusNode)
+ {
+
+ ADDBusNode bus = (ADDBusNode) dp;
+
+ String busName = bus.getNodeName ();
+ int nbOfAttachedInitiators =
+ bus.getNbOfAttachedInitiators ();
+ int nbOfAttachedTargets = bus.getNbOfAttachedTargets ();
+ int fifoDepth = bus.getFifoDepth ();
+ int minLatency = bus.getMinLatency ();
+
+ AvatarBus avbus =
+ new AvatarBus (busName, nbOfAttachedInitiators,
+ nbOfAttachedTargets, fifoDepth,
+ minLatency);
+ avatarMap.put (dp, avbus);
+ avatarComponents.add (avbus);
+
+ }
+ else if (dp instanceof ADDVgmnNode)
+ {
+
+ ADDVgmnNode vgmn = (ADDVgmnNode) dp;
+
+ String vgmnName = vgmn.getNodeName ();
+ int nbOfAttachedInitiators =
+ vgmn.getNbOfAttachedInitiators ();
+ int nbOfAttachedTargets = vgmn.getNbOfAttachedTargets ();
+ int fifoDepth = vgmn.getFifoDepth ();
+ int minLatency = vgmn.getMinLatency ();
+
+ AvatarVgmn avvgmn =
+ new AvatarVgmn (vgmnName, nbOfAttachedInitiators,
+ nbOfAttachedTargets, fifoDepth,
+ minLatency);
+ avatarMap.put (dp, avvgmn);
+ avatarComponents.add (avvgmn);
+
+ }
+ else if (dp instanceof ADDCrossbarNode)
+ {
+
+ ADDCrossbarNode crossbar = (ADDCrossbarNode) dp;
+
+ String crossbarName = crossbar.getNodeName ();
+ // int nbOfAttachedInitiators = crossbar.getNbOfAttachedInitiators();
+ int nbOfAttachedInitiators = 0;
+
+ // int nbOfAttachedTargets = crossbar.getNbOfAttachedTargets();
+
+ int nbOfAttachedTargets = 0;
+
+ int cluster_index = crossbar.getClusterIndex ();
+ int cluster_address = crossbar.getClusterAddress ();
+
+ AvatarCrossbar avcrossbar =
+ new AvatarCrossbar (crossbarName,
+ nbOfAttachedInitiators,
+ nbOfAttachedTargets,
+ cluster_index,
+ cluster_address);
+ nb_clusters++;
+
+ avatarMap.put (dp, avcrossbar);
+ avatarComponents.add (avcrossbar);
+ }
+ else if (dp instanceof ADDICUNode)
+ {
+
+ ADDICUNode icu = (ADDICUNode) dp;
+
+ String ICUName = icu.getNodeName ();
+ int index = icu.getIndex ();
+ int nbIRQ = icu.getNIrq ();
+
+ AvatarICU avicu = new AvatarICU (ICUName, index, nbIRQ);
+ avatarMap.put (dp, avicu);
+ avatarComponents.add (avicu);
+
}
-
-
- for (TGComponent dp : tgcComponents) {
-
- if (dp instanceof ADDConnector) {
-
- ADDConnector connector = (ADDConnector) dp;
-
- TGConnectingPoint connectingPoint1 = connector.get_p1();
- TGConnectingPoint connectingPoint2 = connector.get_p2();
-
- TGComponent owner_p1 = avatarddDiagramPanel.getComponentToWhichBelongs(connectingPoint1);
- TGComponent owner_p2 = avatarddDiagramPanel.getComponentToWhichBelongs(connectingPoint2);
-
- //
-
- AvatarComponent avowner_p1 = avatarMap.get(owner_p1);
- AvatarComponent avowner_p2 = avatarMap.get(owner_p2);
-
- //create Avatar connecting points
-
- AvatarConnectingPoint avConnectingPoint1 = new AvatarConnectingPoint(avowner_p1);
- AvatarConnectingPoint avConnectingPoint2 = new AvatarConnectingPoint(avowner_p2);
- // monitored = 0 VCD trace
- // monitored = 1 VCI logger
- // monitored = 2 MWMR stats
- boolean spy = connector.hasASpy();
- int monitored = 0;
- //
-
- if (spy == true) {
- monitored = 1;
- //
- //
-
- }
- AvatarConnector avconnector = new AvatarConnector(avConnectingPoint1, avConnectingPoint2, monitored);
-
- if (avowner_p1 instanceof AvatarRAM) {
- //if stats mode selected beforehand in menu of component or spy
- AvatarRAM ram1=(AvatarRAM) avowner_p1;
- //
- if ((((AvatarRAM)avowner_p1).getMonitored() == 2)||(spy == true))
- //if (((AvatarRAM)avowner_p1).getMonitored() == 2)
- {
- monitored = 2;
- //monitored = 1;
- //}
-
- (((AvatarRAM) avowner_p1)).setMonitored(monitored);
-
- //
-
- }
- }
-
- if (avowner_p1 instanceof AvatarCPU) {
- (((AvatarCPU) avowner_p1)).setMonitored(monitored);
- }
-
- avatarConnectors.add(avconnector);
- }
+ else if (dp instanceof ADDTimerNode)
+ {
+ ADDTimerNode timer = (ADDTimerNode) dp;
+
+ String timerName = timer.getNodeName ();
+ int nIrq = timer.getNIrq ();
+ int index = timer.getIndex ();
+
+ AvatarTimer avtimer =
+ new AvatarTimer (timerName, index, nIrq);
+ avatarMap.put (dp, avtimer);
+ avatarComponents.add (avtimer);
+
}
- }
+ else if (dp instanceof ADDCoproMWMRNode)
+ {
+
+ ADDCoproMWMRNode addCoproMWMRNode = (ADDCoproMWMRNode) dp;
+
+ String timerName = addCoproMWMRNode.getNodeName ();
+ int srcid = addCoproMWMRNode.getSrcid (); // initiator id
+ int tgtid = addCoproMWMRNode.getTgtid (); // target id
+ int plaps = addCoproMWMRNode.getPlaps (); // configuration of integrated timer
+ int fifoToCoprocDepth =
+ addCoproMWMRNode.getFifoToCoprocDepth ();
+ int fifoFromCoprocDepth =
+ addCoproMWMRNode.getFifoFromCoprocDepth ();
+ int nToCopro = addCoproMWMRNode.getNToCopro (); // Nb of channels going to copro
+ int nFromCopro = addCoproMWMRNode.getNFromCopro (); // Nb of channels coming from copro
+ int nConfig = addCoproMWMRNode.getNConfig (); // Nb of configuration registers
+ int nStatus = addCoproMWMRNode.getNStatus (); // nb of status registers
+ boolean useLLSC = addCoproMWMRNode.getUseLLSC (); // more efficient protocol. 0: not used. 1 or more -> used
+ int coprocType = addCoproMWMRNode.getCoprocType (); //virtual or real?
+ nb_init++;
+ nb_target += 2; //DG 28.08. two targets as two segments of memory are created mwmr and mwmrd
+ AvatarCoproMWMR acpMWMR;
+
+ //DG 19.09. map tasks to coproc
+ acpMWMR =
+ new AvatarCoproMWMR (timerName, srcid, srcid, tgtid,
+ plaps, fifoToCoprocDepth,
+ fifoFromCoprocDepth, nToCopro,
+ nFromCopro, nConfig, nStatus,
+ useLLSC, coprocType);
+ // DG 27.04. : pourquoi deux fois new coproc? Bien: on peut mapper les tasks :)
+
+ Vector < ADDBlockArtifact > tasks =
+ addCoproMWMRNode.getArtifactList ();
+
+ for (int i = 0; i < tasks.size (); i++)
+ {
+
+ ADDBlockArtifact task = tasks.get (i);
+
+ String taskName = task.getTaskName ();
+ String referenceTaskName =
+ task.getReferenceTaskName ();
+
+ AvatarTask avtask =
+ new AvatarTask (taskName, referenceTaskName,
+ null, acpMWMR);
+
+ acpMWMR.addTask (avtask);
+ avatarMappedObject.add (avtask);
+ //avtask.setAvatarCoprocReference(acpMWMR);
+ }
+ nb_init++;
+ acpMWMR =
+ new AvatarCoproMWMR (timerName, srcid, srcid, tgtid,
+ plaps, fifoToCoprocDepth,
+ fifoFromCoprocDepth, nToCopro,
+ nFromCopro, nConfig, nStatus,
+ useLLSC, coprocType);
+
+ avatarMap.put (dp, acpMWMR);
+ avatarComponents.add (acpMWMR);
+
+ }
+ else if (dp instanceof ADDMemoryNode)
+ {
+
+ if (dp instanceof ADDRAMNode)
+ {
+
+ ADDRAMNode addRamNode = (ADDRAMNode) dp;
+ String name = addRamNode.getNodeName ();
+ int index = addRamNode.getIndex ();
+ int byteDataSize = addRamNode.getDataSize ();
+
+ //int monitored = addRamNode.getMonitored();
+
+ AvatarRAM avram =
+ new AvatarRAM (name, index, byteDataSize, index,
+ index,
+ addRamNode.getMonitored ());
+ avram.setNo_ram (index);
+ int cluster_index = avram.getIndex ();
+
+
+ nb_target++;
+
+ Vector < ADDChannelArtifact > channels =
+ addRamNode.getArtifactList ();
+ for (int i = 0; i < channels.size (); i++)
+ {
+ ADDChannelArtifact c = channels.get (i);
+
+ String referenceDiagram =
+ c.getReferenceDiagram ();
+ String channelName = c.getChannelName ();
+ //channel is inevitably on same cluster as RAM it is mapped on :)
+ AvatarChannel avcl =
+ new AvatarChannel (referenceDiagram,
+ channelName, avram,
+ cluster_index,
+ addRamNode.
+ getMonitored ());
+ avram.addChannel (avcl);
+ avatarMappedObject.add (avcl);
+ }
+ avatarMap.put (dp, avram);
+ avatarComponents.add (avram);
+ }
+ }
+ }
+
+
+ for (TGComponent dp:tgcComponents)
+ {
+
+ if (dp instanceof ADDConnector)
+ {
+
+ ADDConnector connector = (ADDConnector) dp;
+
+ TGConnectingPoint connectingPoint1 = connector.get_p1 ();
+ TGConnectingPoint connectingPoint2 = connector.get_p2 ();
- public AvatarddSpecification getAvatarddSpecification() {
- return new AvatarddSpecification(avatarComponents, avatarConnectors, avatarMappedObject, nb_target, nb_init);
- }
+ TGComponent owner_p1 =
+ avatarddDiagramPanel.getComponentToWhichBelongs
+ (connectingPoint1);
+ TGComponent owner_p2 =
+ avatarddDiagramPanel.getComponentToWhichBelongs
+ (connectingPoint2);
+
+
+ AvatarComponent avowner_p1 = avatarMap.get (owner_p1);
+ AvatarComponent avowner_p2 = avatarMap.get (owner_p2);
+
+ //create Avatar connecting points
+
+ AvatarConnectingPoint avConnectingPoint1 =
+ new AvatarConnectingPoint (avowner_p1);
+ AvatarConnectingPoint avConnectingPoint2 =
+ new AvatarConnectingPoint (avowner_p2);
+ // monitored = 0 VCD trace
+ // monitored = 1 VCI logger
+ // monitored = 2 MWMR stats
+ boolean spy = connector.hasASpy ();
+ int monitored = 0;
+
+
+ if (spy == true)
+ {
+ monitored = 1;
+
+
+ }
+ AvatarConnector avconnector =
+ new AvatarConnector (avConnectingPoint1,
+ avConnectingPoint2,
+ monitored);
+
+ if (avowner_p1 instanceof AvatarRAM)
+ {
+ //if stats mode selected beforehand in menu of component or spy
+ AvatarRAM ram1 = (AvatarRAM) avowner_p1;
+
+ if ((((AvatarRAM) avowner_p1).getMonitored () == 2)
+ || (spy == true))
+ //if (((AvatarRAM)avowner_p1).getMonitored() == 2)
+ {
+ monitored = 2;
+
+ (((AvatarRAM) avowner_p1)).
+ setMonitored (monitored);
+
+ }
+ }
+
+ if (avowner_p1 instanceof AvatarCPU)
+ {
+ (((AvatarCPU) avowner_p1)).setMonitored (monitored);
+ }
+
+ avatarConnectors.add (avconnector);
+ }
+ }
+ }
+
+ public AvatarddSpecification getAvatarddSpecification ()
+ {
+ return new AvatarddSpecification (avatarComponents, avatarConnectors,
+ avatarMappedObject, nb_target,
+ nb_init);
+ }
}
diff --git a/src/main/java/ui/AvatarDesignPanel.java b/src/main/java/ui/AvatarDesignPanel.java
index f2e923013b..5e590ebbe4 100644
--- a/src/main/java/ui/AvatarDesignPanel.java
+++ b/src/main/java/ui/AvatarDesignPanel.java
@@ -406,7 +406,7 @@ public class AvatarDesignPanel extends TURTLEPanel {
//Check if the latency statement is true
int refTime = pragma.getTime();
float time = 0;
- //
+ //System.out.println("time " + latency.getAverageTime() + " " + refTime);
try {
time = Float.valueOf(latency.getAverageTime());
} catch (Exception e){
--
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