diff --git a/simulators/c++2/src_simulator/app/TMLTask.h b/simulators/c++2/src_simulator/app/TMLTask.h
index 50b69ab00464f35956a77adde9da910024626273..8c8e40a1ac3cd192b62ac30dacf5449c68314250 100755
--- a/simulators/c++2/src_simulator/app/TMLTask.h
+++ b/simulators/c++2/src_simulator/app/TMLTask.h
@@ -240,6 +240,8 @@ public:
unsigned int getNextCellIndex() const {return _nextCellIndex;}
void schedule2HTML(std::ofstream& myfile) const;
bool getIsDaemon() {return _isDaemon;};
+ bool getIsFirstTranExecuted() {return _isFirstTranExecuted;};
+ inline void setIsFirstTranExecuted(bool x) {_isFirstTranExecuted = x;};
protected:
///ID of the task
ID _ID;
@@ -264,6 +266,7 @@ protected:
///Number of cores assigned to the task
unsigned int _noOfFPGAs;
bool _isDaemon;
+ bool _isFirstTranExecuted;
unsigned int _nextCellIndex;
#ifdef ADD_COMMENTS
diff --git a/simulators/c++2/src_simulator/arch/CPU.cpp b/simulators/c++2/src_simulator/arch/CPU.cpp
index c950f9eee66994ac9544b5ddae4843a69e2812b5..5ccd63358397c212849afb006fe0f2c77bfcd9c0 100644
--- a/simulators/c++2/src_simulator/arch/CPU.cpp
+++ b/simulators/c++2/src_simulator/arch/CPU.cpp
@@ -208,8 +208,8 @@ std::map<TMLTask*, std::string> CPU::HWTIMELINE2HTML(std::ostringstream& myfile,
bool isBlankTooBig = false;
std::ostringstream tempString;
int tempBlanks;
- if(endTimeOfCore >= 250 && aBlanks > 10) {
- int newBlanks = 10;
+ if(endTimeOfCore >= MIN_RESIZE_THRESHOLD && aBlanks > MIN_RESIZE_TRANS) {
+ int newBlanks = MIN_RESIZE_TRANS;
tempBlanks = aBlanks;
tempReduce += aBlanks - newBlanks;
aBlanks = newBlanks;
@@ -248,9 +248,9 @@ std::map<TMLTask*, std::string> CPU::HWTIMELINE2HTML(std::ostringstream& myfile,
unsigned int aLength = aCurrTrans->getPenalties();
if ( aLength != 0 ) {
listScaleTime.push_back(listScaleTime.back()+aLength);
- if (endTimeOfCore >= 250 && aLength > 10){
- tempReduce += aLength - 10;
- aLength = 10;
+ if (endTimeOfCore >= MIN_RESIZE_THRESHOLD && aLength > MIN_RESIZE_TRANS){
+ tempReduce += aLength - MIN_RESIZE_TRANS;
+ aLength = MIN_RESIZE_TRANS;
}
listScale.push_back(aLength);
std::ostringstream title;
@@ -267,9 +267,9 @@ std::map<TMLTask*, std::string> CPU::HWTIMELINE2HTML(std::ostringstream& myfile,
unsigned int indexTrans=aCurrTransName.find_first_of(":");
std::string aCurrContent=aCurrTransName.substr(indexTrans+1,2);
if(!(!(aCurrTrans->getCommand()->getActiveDelay()) && aCurrTrans->getCommand()->isDelayTransaction())){
- if (endTimeOfCore >= 250 && aLength > 10){
- tempReduce += aLength - 10;
- aLength = 10;
+ if (endTimeOfCore >= MIN_RESIZE_THRESHOLD && aLength > MIN_RESIZE_TRANS){
+ tempReduce += aLength - MIN_RESIZE_TRANS;
+ aLength = MIN_RESIZE_TRANS;
}
std::string aCurrFullTransName = aCurrTrans->toString();
unsigned int indexTrans1 = aCurrFullTransName.find("len:");
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index f96123047409cbcbe537b5dc1ec868817d84d52b..dad3ee232a5a04558b7c30c4f214631e65bc1148 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -241,9 +241,12 @@ std::cout<<"fpga addTransaction"<<std::endl;
//std::cout<<"end schedule is ~~~~~~~"<<_endSchedule<<std::endl;
if(_endSchedule == 0 && (!(_nextTransaction->getCommand()->getTask()->getIsDaemon()==true && _nextTransaction->getCommand()->getTask()->getNextTransaction(0)==0)))
_maxEndTime=max(_maxEndTime,_nextTransaction->getEndTime());
- if(_reconfigNumber>0)
- _nextTransaction->setStartTime(_maxEndTime+_reconfigNumber*_reconfigTime);
-// _endSchedule=_maxEndTime+_reconfigNumber*_reconfigTime;
+ if(_reconfigNumber>0) {
+ if(!_nextTransaction->getCommand()->getTask()->getIsFirstTranExecuted()) {
+ _nextTransaction->setStartTime(_maxEndTime + _reconfigNumber * _reconfigTime);
+ _nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
+ }
+ }
else{
_endSchedule=0;
@@ -376,7 +379,11 @@ void FPGA::reset(){
_lastTransaction=0;
_masterNextTransaction=0;
_busyCycles=0;
+ _maxEndTime = 0;
maxScale = 0;
+ for(TaskList::const_iterator i = _taskList.begin(); i!= _taskList.end(); ++i){
+ (*i)->setIsFirstTranExecuted(false);
+ }
}
void FPGA::schedule2TXT(std::ofstream& myfile) const{
@@ -609,7 +616,7 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
} else {
if(_startFlagHTML == true){
myfile << "<tr><td title = \"Average load: " << std::setprecision(2) << averageLoad(_htmlCurrTask) << "; Utilization: " << (static_cast<float>(_busyCycles)/static_cast<float>(_simulatedTime)) << "\" width=\"170px\" style=\"max-width: unset;min-width: 170px;background-color: aqua;\">" << _name << "</td><td class=\"notfirst\"></td><td class=\"notlast\"></td>";
- } else {
+ } else if (_htmlCurrTask->getEndLastTransaction() > 0) {
myfile << "<tr><td title = \"Average load: " << std::setprecision(2) << averageLoad(_htmlCurrTask) << "; Utilization: " << (static_cast<float>(_busyCycles)/static_cast<float>(_simulatedTime)) << "\" width=\"170px\" style=\"max-width: unset;min-width: 170px;border-style: none none none none;\"></td><td class=\"notfirst\"></td><td class=\"notlast\"></td>";
}
TMLTime aCurrTime = 0;
@@ -637,8 +644,8 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
bool isBlankTooBig = false;
std::ostringstream tempString;
int tempBlanks;
- if(_htmlCurrTask->getEndLastTransaction() >= 250 && aBlanks >10) {
- int newBlanks = 10;
+ if(_htmlCurrTask->getEndLastTransaction() >= MIN_RESIZE_THRESHOLD && aBlanks > MIN_RESIZE_TRANS) {
+ int newBlanks = MIN_RESIZE_TRANS;
tempBlanks = aBlanks;
tempReduce += aBlanks - newBlanks;
aBlanks = newBlanks;
@@ -676,9 +683,9 @@ std::map<TMLTask*, std::string> FPGA::HWTIMELINE2HTML(std::ostringstream& myfile
unsigned int indexTrans=aCurrTransName.find_first_of(":");
std::string aCurrContent=aCurrTransName.substr(indexTrans+1,2);
if(!(!(aCurrTrans->getCommand()->getActiveDelay()) && aCurrTrans->getCommand()->isDelayTransaction())){
- if(_htmlCurrTask->getEndLastTransaction() >= 250 && aLength >10){
- tempReduce += aLength - 10;
- aLength = 10;
+ if(_htmlCurrTask->getEndLastTransaction() >= MIN_RESIZE_THRESHOLD && aLength > MIN_RESIZE_TRANS){
+ tempReduce += aLength - MIN_RESIZE_TRANS;
+ aLength = MIN_RESIZE_TRANS;
}
std::string aCurrFullTransName = aCurrTrans->toString();
unsigned int indexTrans1 = aCurrFullTransName.find("len:");
diff --git a/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp b/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp
index bfb367b63e8c9c86455c326cd1cee90061a6e567..5861234a6cbfd2f9c4c9742741eec75fa65b9a44 100644
--- a/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp
@@ -45,8 +45,7 @@ ReconfigScheduler::ReconfigScheduler(const std::string& iName, Priority iPrio, c
ReconfigScheduler::ReconfigScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources, const std::string iTaskOrder): WorkloadSource(iPrio, aSourceArray, iNbOfSources), _name(iName), _taskOrder(iTaskOrder), _nextTransaction(0), _lastSource(0), _tempWorkloadList(0), _indexMark(0), _reconfigNumber(0) {
}
-Priority previousRank = 0;
-Priority currentRank = 0;
+
TMLTime ReconfigScheduler::schedule(TMLTime iEndSchedule){
std::cout<<"reconfig scheduler"<<std::endl;
TaskList::iterator i;
@@ -100,9 +99,9 @@ TMLTime ReconfigScheduler::schedule(TMLTime iEndSchedule){
}
}
- _workloadList.sort(sortByPriority);//very importance
+// _workloadList.sort(sortByPriority);
Priority aHighestPrioPast=-1;
- for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
+ for(WorkloadList::iterator i = _workloadList.begin(); i != _workloadList.end(); ++i){
#ifdef DEBUG_FPGA
std::cout<<"schedule for"<<std::endl;
#endif
@@ -111,7 +110,6 @@ TMLTime ReconfigScheduler::schedule(TMLTime iEndSchedule){
if(aTempTrans==0) std::cout<< (*i)->toString() + "temp trans is 0"<<std::endl;
else {
std::cout<<(*i)->toString() + "temp trans is "<<aTempTrans->toShortString()<<std::endl;
- currentRank = (*i)->getPriority();
}
#ifdef DEBUG_FPGA
if(aTempTrans==0) std::cout<<"temp trans is 0"<<std::endl;
@@ -120,48 +118,32 @@ TMLTime ReconfigScheduler::schedule(TMLTime iEndSchedule){
if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0){
aRunnableTime=aTempTrans->getRunnableTime();
- if (aRunnableTime<=iEndSchedule){
- //Past
- if ((*i)->getPriority()<aHighestPrioPast || ((*i)->getPriority()==aHighestPrioPast && aRunnableTime<aLowestRunnableTimePast)){
- aHighestPrioPast=(*i)->getPriority();
- aLowestRunnableTimePast=aRunnableTime;
- aMarkerPast=aTempTrans;
- aSourcePast=*i;
- }
- }else{
- //Future
- if(aRunnableTime<aTransTimeFuture){
- aTransTimeFuture=aRunnableTime;
- aMarkerFuture=aTempTrans;
- aSourceFuture=*i;
- }
- }
+ //Past
+ if ((*i)->getPriority() < aHighestPrioPast || ((*i)->getPriority() == aHighestPrioPast && aRunnableTime < aLowestRunnableTimePast)) {
+ aHighestPrioPast = (*i)->getPriority();
+ aLowestRunnableTimePast = aRunnableTime;
+ aMarkerPast = aTempTrans;
+ aSourcePast = *i;
+ }
+
#ifdef DEBUG_FPGA
std::cout<<"erase"<<std::endl;
#endif
- break;
}
-
}
if (aMarkerPast==0){
- _nextTransaction=aMarkerFuture;
- _lastSource=aSourceFuture; //NEW
- }else{
- _nextTransaction=aMarkerPast;
- _lastSource=aSourcePast; //NEW
- }
- if (currentRank != previousRank){
- ++_reconfigNumber;
+ _nextTransaction=(aSourceFuture==0)? 0 : aSourceFuture->getNextTransaction(iEndSchedule);;
+ _lastSource=aSourceFuture; //NEW
+ } else{
+ _nextTransaction=aSourcePast->getNextTransaction(iEndSchedule);;
+ _lastSource=aSourcePast; //NEW
+ _reconfigNumber = aSourcePast->getPriority();
}
- previousRank = currentRank;
#ifdef DEBUG_FPGA
std::cout<<"end order scheduler"<<std::endl;
#endif
return _reconfigNumber;
-
-
-
}
ReconfigScheduler::~ReconfigScheduler(){
@@ -173,4 +155,5 @@ ReconfigScheduler::~ReconfigScheduler(){
void ReconfigScheduler::reset(){
WorkloadSource::reset();
_nextTransaction=0;
+ _reconfigNumber = 0;
}
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index 632a8264c7162687e222178314d02cf6ebee76bf..3590da0455d8e087a3940be83902c78ad639a4b4 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -333,8 +333,8 @@ std::map<TMLTask*, std::string> SchedulableDevice::HWTIMELINE2HTML(std::ostrings
bool isBlankTooBig = false;
std::ostringstream tempString;
int tempBlanks;
- if((checkLastTime)->getEndTime() >= 250 && aBlanks > 10) {
- int newBlanks = 10;
+ if((checkLastTime)->getEndTime() >= MIN_RESIZE_THRESHOLD && aBlanks > MIN_RESIZE_TRANS) {
+ int newBlanks = MIN_RESIZE_TRANS;
tempBlanks = aBlanks;
tempReduce += aBlanks - newBlanks;
aBlanks = newBlanks;
@@ -375,9 +375,9 @@ std::map<TMLTask*, std::string> SchedulableDevice::HWTIMELINE2HTML(std::ostrings
if ( aLength != 0 ) {
std::ostringstream title;
listScaleTime.push_back(listScaleTime.back()+aLength);
- if(checkLastTime->getEndTime() >= 250 && aLength >10){
- tempReduce += aLength - 10;
- aLength = 10;
+ if(checkLastTime->getEndTime() >= MIN_RESIZE_THRESHOLD && aLength > MIN_RESIZE_TRANS){
+ tempReduce += aLength - MIN_RESIZE_TRANS;
+ aLength = MIN_RESIZE_TRANS;
}
listScale.push_back(aLength);
title << "idle:" << aCurrTrans->getIdlePenalty() << " switching penalty:" << aCurrTrans->getTaskSwitchingPenalty();
@@ -394,9 +394,9 @@ std::map<TMLTask*, std::string> SchedulableDevice::HWTIMELINE2HTML(std::ostrings
unsigned int indexTrans=aCurrTransName.find_first_of(":");
std::string aCurrContent=aCurrTransName.substr(indexTrans+1,2);
if(!(!(aCurrTrans->getCommand()->getActiveDelay()) && aCurrTrans->getCommand()->isDelayTransaction())){
- if(checkLastTime->getEndTime() >= 250 && aLength >10){
- tempReduce += aLength - 10;
- aLength = 10;
+ if(checkLastTime->getEndTime() >= MIN_RESIZE_THRESHOLD && aLength > MIN_RESIZE_TRANS){
+ tempReduce += aLength - MIN_RESIZE_TRANS;
+ aLength = MIN_RESIZE_TRANS;
}
std::string aCurrFullTransName = aCurrTrans->toString();
unsigned int indexTrans1 = aCurrFullTransName.find("len:");
diff --git a/simulators/c++2/src_simulator/definitions.h b/simulators/c++2/src_simulator/definitions.h
index db56053b3fa2e5567856b07b60eac988d3efb35f..66d990191c452a3b2f6e797d5bb87a013ee2d8b4 100644
--- a/simulators/c++2/src_simulator/definitions.h
+++ b/simulators/c++2/src_simulator/definitions.h
@@ -288,6 +288,8 @@ using std::max;
#define NB_HTML_COLORS 15
#define SHOW_PIE_CHART "ShowPie"
#define BUFFER_SIZE 2000 //maximum length of a command sent to server
+#define MIN_RESIZE_THRESHOLD 250 //if task has more than MIN_RESIZE_THRESHOLD cycles then reduce the length of blanks and transactions
+#define MIN_RESIZE_TRANS 10 // if trans or blank size > MIN_RESIZE_TRANS then reduce to 50
#define SCHED_HTML_JS_FUNCTION "= function() {\n \
var r = Math.floor(Math.random() * 255);\n \
diff --git a/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java b/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java
index b36615ee1179db415610e82b4356f9cbce76546c..e2cd943089b4ba71383b6d8405610567870fc154 100644
--- a/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java
+++ b/ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java
@@ -62,8 +62,8 @@ public class DiplodocusDelayTest extends AbstractUITest {
final String [] MODELS_FPGA_RECONFIG = {"fpga_reconfig1", "fpga_reconfig2", "fpga_reconfig3", "fpga_reconfig4", "fpga_reconfig5"};
final int [] NB_Of_FPGA_STATES = {20, 20, 20, 20, 20};
final int [] NB_Of_FPGA_TRANSTIONS = {19, 19, 19, 19, 19};
- final int [] MIN_FPGA_CYCLES = {143, 102, 107, 87, 102};
- final int [] MAX_FPGA_CYCLES = {143, 102, 107, 87, 102};
+ final int [] MIN_FPGA_CYCLES = {90, 83, 77, 70, 75};
+ final int [] MAX_FPGA_CYCLES = {90, 83, 77, 70, 75};
private String SIM_DIR;
diff --git a/ttool/src/test/java/tmltranslator/HTMLParseTest.java b/ttool/src/test/java/tmltranslator/HTMLParseTest.java
index 67475ef21c1f3fe7c502a32cd8f4d37fe2c12e04..256f3233bb8f98fc5e152bd2bb442b2e4e2cd11b 100644
--- a/ttool/src/test/java/tmltranslator/HTMLParseTest.java
+++ b/ttool/src/test/java/tmltranslator/HTMLParseTest.java
@@ -31,7 +31,7 @@ import static org.junit.Assert.assertTrue;
public class HTMLParseTest extends AbstractUITest {
final String DIR_GEN = "test_diplo_simulator/";
final String [] MODELS_PARSE_HTML = {"parseFPGA_HTML", "parseCPU1_HTML","parseCPU2_HTML"};
- final String [] PARSE_FPGA = {"<- idle 195 ->","<- idle 358 ->", "<- idle 204 ->", "<- idle 351 ->", "<- idle 85 ->"};
+ final String [] PARSE_FPGA = {"<- idle 471 ->","", "", "", ""};
final String [] PARSE_SINGLE_CORE = {"<- idle 366 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->"};
final String [] PARSE_MULTI_CORE = { "", "", "<- idle 374 ->", "<- idle 401 ->", "<- idle 401 ->"};
final static String EXPECTED_FILE_GET_ALL_TRANS = getBaseResourcesDir() + "tmltranslator/expected/expected_get_all_transactions.txt";
diff --git a/ttool/src/test/java/tmltranslator/RemoveAllTransactionsTests.java b/ttool/src/test/java/tmltranslator/RemoveAllTransactionsTests.java
index 402dcff46463c68e61b9e7634401a71e2389e5ab..e29a6acd1d7ff9fc9a7fe88e06e1a8472e29c5db 100644
--- a/ttool/src/test/java/tmltranslator/RemoveAllTransactionsTests.java
+++ b/ttool/src/test/java/tmltranslator/RemoveAllTransactionsTests.java
@@ -28,8 +28,8 @@ public class RemoveAllTransactionsTests extends AbstractUITest {
final String DIR_GEN = "test_diplo_simulator/";
final String [] MODELS_PARSE_HTML = {"parseFPGA_HTML"};
final static String EXPECTED_FILE_REMOVE_ALL_TRANS = getBaseResourcesDir() + "tmltranslator/expected/expected_remove_all_trans.txt";
- final int [] FULL_DATA_TRANSACTION = {21, 20, 1179, 1179};
- final int [] REMOVE_DATA_TRANSACTION = {8, 7, 1179, 1179};
+ final int [] FULL_DATA_TRANSACTION = {20, 19, 476, 476};
+ final int [] REMOVE_DATA_TRANSACTION = {8, 7, 476, 476};
private String SIM_DIR;
@BeforeClass
public static void setUpBeforeClass() throws Exception {
diff --git a/ttool/src/test/resources/tmltranslator/expected/expected_get_all_transactions.txt b/ttool/src/test/resources/tmltranslator/expected/expected_get_all_transactions.txt
index 82a913b3603b3233588c0d5c4e2e0fe3b2df590d..4be21e6d39253242445c349fe8766962131774fa 100644
--- a/ttool/src/test/resources/tmltranslator/expected/expected_get_all_transactions.txt
+++ b/ttool/src/test/resources/tmltranslator/expected/expected_get_all_transactions.txt
@@ -1,10 +1,10 @@
-Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:30"
+Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:24"
Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: Execi 5"
-Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:30"
+Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:24"
Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: Execi 5"
-Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:30"
+Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:24"
Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: Execi 5"
-Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:30"
-Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: Execi 5"
-Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:30"
+Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:24"
Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: Execi 5"
+Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: IdleDL in Application__Task2 len:1 progress:0 ID:24"
+Info transaction: " deviceid="0" devicename="FPGA0" command="Application__Task2: Execi 5"
\ No newline at end of file
diff --git a/ttool/src/test/resources/tmltranslator/expected/expected_remove_all_trans.txt b/ttool/src/test/resources/tmltranslator/expected/expected_remove_all_trans.txt
index b90eda308c92b57b77546e0ddf02ee55275259f5..258ac81a3cb3c9fd776d3af129b340da4f46376c 100644
--- a/ttool/src/test/resources/tmltranslator/expected/expected_remove_all_trans.txt
+++ b/ttool/src/test/resources/tmltranslator/expected/expected_remove_all_trans.txt
@@ -1,4 +1,3 @@
========= Scheduling for device: FPGA0 =========
-Application__Task3: Write 20,Application__ch t:355 l:2 (vl:8) params: Ch: Application__ch
-========= Scheduling for device: Bus0_0 =========
-Application__Task3: Write 20,Application__ch t:355 l:2 (vl:8) params: Ch: Application__ch
+Application__Task4: Read 20,Application__ch t:299 l:8 (vl:8) params: Ch: Application__ch
+========= Scheduling for device: Bus0_0 =========
\ No newline at end of file
diff --git a/ttool/src/test/resources/tmltranslator/simulator/parseFPGA_HTML.xml b/ttool/src/test/resources/tmltranslator/simulator/parseFPGA_HTML.xml
index 5f548cb914cb5d68f415d33f9d4e9c88157805a1..fad425ebd048e73a562d8e501405e3673f70f065 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/parseFPGA_HTML.xml
+++ b/ttool/src/test/resources/tmltranslator/simulator/parseFPGA_HTML.xml
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
-<TURTLEGMODELING version="1.0beta" ANIMATE_INTERACTIVE_SIMULATION="true" ACTIVATE_PENALTIES="false" UPDATE_INFORMATION_DIPLO_SIM="true" ANIMATE_WITH_INFO_DIPLO_SIM="true" OPEN_DIAG_DIPLO_SIM="false" LAST_SELECTED_MAIN_TAB="1" LAST_SELECTED_SUB_TAB="0">
+<TURTLEGMODELING version="1.0beta" ANIMATE_INTERACTIVE_SIMULATION="true" ACTIVATE_PENALTIES="false" UPDATE_INFORMATION_DIPLO_SIM="false" ANIMATE_WITH_INFO_DIPLO_SIM="true" OPEN_DIAG_DIPLO_SIM="false" LAST_SELECTED_MAIN_TAB="1" LAST_SELECTED_SUB_TAB="0">
<Modeling type="TML Component Design" nameTab="Application" tabs="TML Component Task Diagram$Task1$Task2$Task3$Task4$Task5" >
<TMLComponentTaskDiagramPanel name="TML Component Task Diagram" minX="10" maxX="2500" minY="10" maxY="1500" channels="true" events="true" requests="true" zoom="1.0" >
@@ -27,7 +27,7 @@
<TGConnectingPoint num="6" id="8" />
<TGConnectingPoint num="7" id="9" />
<extraparam>
-<Data isAttacker="No" daemon="false" Operation="" />
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="" Operation="" />
</extraparam>
</COMPONENT>
@@ -46,7 +46,7 @@
<TGConnectingPoint num="6" id="19" />
<TGConnectingPoint num="7" id="20" />
<extraparam>
-<Data isAttacker="No" daemon="false" Operation="" />
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="" Operation="" />
</extraparam>
</COMPONENT>
<SUBCOMPONENT type="1203" id="12" >
@@ -58,7 +58,7 @@
<infoparam name="Primitive port" value="Channel ch" />
<TGConnectingPoint num="0" id="11" />
<extraparam>
-<Prop commName="ch" commType="0" origin="false" finite="false" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="-1" />
+<Prop commName="ch" commType="0" origin="false" finite="false" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="1" checkStrongAuthStatus="1" vc="-1" />
<Type type="0" typeOther="" />
<Type type="0" typeOther="" />
<Type type="0" typeOther="" />
@@ -82,7 +82,7 @@
<TGConnectingPoint num="6" id="30" />
<TGConnectingPoint num="7" id="31" />
<extraparam>
-<Data isAttacker="No" daemon="false" Operation="" />
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="" Operation="" />
</extraparam>
</COMPONENT>
<SUBCOMPONENT type="1203" id="23" >
@@ -94,7 +94,7 @@
<infoparam name="Primitive port" value="Channel ch" />
<TGConnectingPoint num="0" id="22" />
<extraparam>
-<Prop commName="ch" commType="0" origin="true" finite="false" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="-1" />
+<Prop commName="ch" commType="0" origin="true" finite="false" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="1" checkStrongAuthStatus="1" vc="-1" />
<Type type="0" typeOther="" />
<Type type="0" typeOther="" />
<Type type="0" typeOther="" />
@@ -118,7 +118,7 @@
<TGConnectingPoint num="6" id="39" />
<TGConnectingPoint num="7" id="40" />
<extraparam>
-<Data isAttacker="No" daemon="false" Operation="" />
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="" Operation="" />
</extraparam>
</COMPONENT>
@@ -137,7 +137,7 @@
<TGConnectingPoint num="6" id="48" />
<TGConnectingPoint num="7" id="49" />
<extraparam>
-<Data isAttacker="No" daemon="false" Operation="" />
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="" Operation="" />
</extraparam>
</COMPONENT>
@@ -525,16 +525,16 @@
<TGConnectingPoint num="23" id="180" />
<extraparam>
<info stereotype="FPGA" nodeName="FPGA0" />
-<attributes capacity="100" byteDataSize="4" mappingPenalty="0" reconfigurationTime="50" goIdleTime="10" maxConsecutiveIdleCycles="10" execiTime="1" execcTime="1" clockRatio="1" operation ="" scheduling ="Task1,Task2;Task4;Task3;Task5" />
+<attributes capacity="100" byteDataSize="4" mappingPenalty="0" reconfigurationTime="50" goIdleTime="10" maxConsecutiveIdleCycles="10" execiTime="1" execcTime="1" clockRatio="1" operation ="" scheduling ="Task1; Task2;Task3 Task4;Task5" />
</extraparam>
</COMPONENT>
<SUBCOMPONENT type="1101" id="120" >
<father id="181" num="0" />
-<cdparam x="329" y="277" />
-<sizeparam width="149" height="39" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<cdparam x="116" y="276" />
+<sizeparam width="149" height="40" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="213" minY="0" maxY="216" />
-<infoparam name="TGComponent" value="Application::Task5" />
+<cdrectangleparam minX="0" maxX="213" minY="0" maxY="215" />
+<infoparam name="TGComponent" value="Application::Task4" />
<TGConnectingPoint num="0" id="112" />
<TGConnectingPoint num="1" id="113" />
<TGConnectingPoint num="2" id="114" />
@@ -544,16 +544,16 @@
<TGConnectingPoint num="6" id="118" />
<TGConnectingPoint num="7" id="119" />
<extraparam>
-<info value="Application::Task5" taskName="Task5" referenceTaskName="Application" priority="0" operationMEC="Task5" fatherComponentMECType="0" />
+<info value="Application::Task4" taskName="Task4" referenceTaskName="Application" priority="0" operationMEC="Task4" fatherComponentMECType="0" />
</extraparam>
</SUBCOMPONENT>
<SUBCOMPONENT type="1101" id="129" >
<father id="181" num="1" />
-<cdparam x="329" y="120" />
+<cdparam x="219" y="189" />
<sizeparam width="149" height="40" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="0" maxX="213" minY="0" maxY="215" />
-<infoparam name="TGComponent" value="Application::Task2" />
+<infoparam name="TGComponent" value="Application::Task3" />
<TGConnectingPoint num="0" id="121" />
<TGConnectingPoint num="1" id="122" />
<TGConnectingPoint num="2" id="123" />
@@ -563,7 +563,7 @@
<TGConnectingPoint num="6" id="127" />
<TGConnectingPoint num="7" id="128" />
<extraparam>
-<info value="Application::Task2" taskName="Task2" referenceTaskName="Application" priority="0" operationMEC="Task2" fatherComponentMECType="0" />
+<info value="Application::Task3" taskName="Task3" referenceTaskName="Application" priority="0" operationMEC="Task3" fatherComponentMECType="0" />
</extraparam>
</SUBCOMPONENT>
<SUBCOMPONENT type="1101" id="138" >
@@ -587,11 +587,11 @@
</SUBCOMPONENT>
<SUBCOMPONENT type="1101" id="147" >
<father id="181" num="3" />
-<cdparam x="219" y="189" />
+<cdparam x="329" y="120" />
<sizeparam width="149" height="40" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
<cdrectangleparam minX="0" maxX="213" minY="0" maxY="215" />
-<infoparam name="TGComponent" value="Application::Task3" />
+<infoparam name="TGComponent" value="Application::Task2" />
<TGConnectingPoint num="0" id="139" />
<TGConnectingPoint num="1" id="140" />
<TGConnectingPoint num="2" id="141" />
@@ -601,16 +601,16 @@
<TGConnectingPoint num="6" id="145" />
<TGConnectingPoint num="7" id="146" />
<extraparam>
-<info value="Application::Task3" taskName="Task3" referenceTaskName="Application" priority="0" operationMEC="Task3" fatherComponentMECType="0" />
+<info value="Application::Task2" taskName="Task2" referenceTaskName="Application" priority="0" operationMEC="Task2" fatherComponentMECType="0" />
</extraparam>
</SUBCOMPONENT>
<SUBCOMPONENT type="1101" id="156" >
<father id="181" num="4" />
-<cdparam x="116" y="276" />
-<sizeparam width="149" height="40" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<cdparam x="329" y="277" />
+<sizeparam width="149" height="39" minWidth="100" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
<hidden value="false" />
-<cdrectangleparam minX="0" maxX="213" minY="0" maxY="215" />
-<infoparam name="TGComponent" value="Application::Task4" />
+<cdrectangleparam minX="0" maxX="213" minY="0" maxY="216" />
+<infoparam name="TGComponent" value="Application::Task5" />
<TGConnectingPoint num="0" id="148" />
<TGConnectingPoint num="1" id="149" />
<TGConnectingPoint num="2" id="150" />
@@ -620,7 +620,7 @@
<TGConnectingPoint num="6" id="154" />
<TGConnectingPoint num="7" id="155" />
<extraparam>
-<info value="Application::Task4" taskName="Task4" referenceTaskName="Application" priority="0" operationMEC="Task4" fatherComponentMECType="0" />
+<info value="Application::Task5" taskName="Task5" referenceTaskName="Application" priority="0" operationMEC="Task5" fatherComponentMECType="0" />
</extraparam>
</SUBCOMPONENT>