diff --git a/simulators/c++2/src_simulator/app/TMLChannel.cpp b/simulators/c++2/src_simulator/app/TMLChannel.cpp
index 1b1b2b0a16d5788ee628672fd7e723c3975147fd..0f2bb5bafd489365fcb12cee6dd3c2f40bc99552 100755
--- a/simulators/c++2/src_simulator/app/TMLChannel.cpp
+++ b/simulators/c++2/src_simulator/app/TMLChannel.cpp
@@ -70,21 +70,16 @@ BusMaster* TMLChannel::getFirstMaster(TMLTransaction* iTrans){
   std::cout<<"get First master"<<std::endl;
   //if (iTrans->getCommand()->getTask()==_writeTask){
   //std::cout << "fima 1\n";
-  if(iTrans==0) std::cout<<"iTrans==0"<<std::endl;
-  else std::cout<<"iTrans is: "<<iTrans->toString()<<std::endl;
-  if (_masters==0 || _slaves==0 || _numberOfHops==0 ) { std::cout<<"case 1"<<std::endl; return 0;}
+  if (_masters==0 || _slaves==0 || _numberOfHops==0 ) {return 0;}
   //std::cout << "fima 2\n";
-  std::cout<<"test11111"<<std::endl;
   if (iTrans==_writeTrans){
     //if (iTrans->getCommand()->getTask()==_writeTask){
     //std::cout << "fima 3\n";
-    std::cout<<"case 2"<<std::endl;
     _writeTransCurrHop=0;
     return _masters[_writeTransCurrHop];
   }else{
-    std::cout<<"case 4"<<std::endl;
     //std::cout << "fima 4\n";
-    if (_slaves[(_numberOfHops/2)]==0) { std::cout<<"case 3"<<std::endl; return 0;}        //NEW!!!
+    if (_slaves[(_numberOfHops/2)]==0) {return 0;}        //NEW!!!
     //std::cout << "fima 5\n";
     _readTransCurrHop=_numberOfHops-1;
     
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index 5b5ebeca4c16ef499b312a58c8e49b0f101c53bf..883382c2cfae104cfc130b4cbc82d5fc083570a6 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -118,7 +118,7 @@ TMLTime MultiCoreCPU::getMinEndSchedule(){
 }
     
 TMLTransaction* MultiCoreCPU::getNextTransaction(){
-std::cout<<"getNextTransaction"<<std::endl;
+std::cout<<"getNextTransaction"<<_name<<std::endl;
 #ifdef BUS_ENABLED
   if (_masterNextTransaction == 0 || _nextTransaction == 0){
     return _nextTransaction;
@@ -128,7 +128,6 @@ std::cout<<"getNextTransaction"<<std::endl;
 #endif
     std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
     BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
-    std::cout<<"getNextTransaction getfirstmaster ok"<<std::endl;
     //std::cout << "1  aTempMaster: " << aTempMaster << std::endl;
     bool aResult = aTempMaster->accessGranted();
     //std::cout << "2" << std::endl;
@@ -147,7 +146,7 @@ std::cout<<"getNextTransaction"<<std::endl;
 }
 
 void MultiCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
-std::cout<<"calcStartTimeLength"<<std::endl;
+std::cout<<"calcStartTimeLength"<<_name<<std::endl;
 #ifdef DEBUG_CPU
   std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
 #endif
@@ -174,7 +173,7 @@ std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nex
   TMLTime aStartTime = max(_endSchedule,_nextTransaction->getRunnableTime());
   TMLTime aReminder = aStartTime % _timePerCycle;
   if (aReminder!=0) aStartTime+=_timePerCycle - aReminder;
-  std::cout << "CPU: set starttime in CPU=" << aStartTime << "\n";
+  std::cout << _name << "CPU: set starttime in CPU=" << aStartTime << "\n";
 
   _nextTransaction->setStartTime(aStartTime);
 
@@ -267,7 +266,7 @@ TMLTime MultiCoreCPU::truncateNextTransAt(TMLTime iTime){
       _nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
     }
 #else
-    if (iTime <= _nextTransaction->getStartTime()) return 0;  //before: <=
+    if (iTime <= _nextTransaction->getStartTime()) return 0;  //before
     TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
     _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration /_timePerExeci), (TMLTime)1));
     _nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
@@ -281,7 +280,7 @@ TMLTime MultiCoreCPU::truncateNextTransAt(TMLTime iTime){
 }
 
 bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
-std::cout<<"addTransaction"<<std::endl;
+std::cout<<"addTransaction"<<_name<<std::endl;
   bool aFinish;
   //TMLTransaction* aTransCopy=0;
   if (_masterNextTransaction==0){
@@ -332,22 +331,24 @@ std::cout<<"addTransaction"<<std::endl;
 #endif
     //_nextTransaction->getCommand()->execute();  //NEW!!!!
     std::cout << "CPU:addt: to be started" << std::endl;
+std::cout << "CPU:calcSTL: addtransaction of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
     _endSchedule=_nextTransaction->getEndTime();
     ////test///
    // unsigned int iCoreNumber=getCoreNumber();
-    unsigned static time=0;
+    std::cout<<"multicore number "<<coreNumber<<" end schedule "<<_endSchedule<<std::endl;
     multiCore[coreNumber]=_endSchedule;
-    if (time < amountOfCore -1){
+    if (_cycleTime < amountOfCore -1){
       _endSchedule=0;
        _nextTransaction->setTransactCoreNumber(coreNumber);
       ++coreNumber;
+      std::cout<<"haha1"<<std::endl;
     }
     else {
       _endSchedule=getMinEndSchedule();
        _nextTransaction->setTransactCoreNumber(coreNumber);
+	std::cout<<"haha2"<<std::endl;
       //initCore();
     }
-    time++;
     std::cout <<"test transaction core number !!!! "<<_nextTransaction->getTransactCoreNumber()<<std::endl;
     std::cout << "set end schedule CPU: " << _endSchedule << "\n";
     _simulatedTime=max(_simulatedTime,_endSchedule);
@@ -371,9 +372,8 @@ std::cout<<"addTransaction"<<std::endl;
 }
 
 void MultiCoreCPU::schedule(){
-std::cout<<"schedule"<<std::endl;
   //std::cout <<"Hello\n";
-  //std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+  std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
   TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
   //_schedulingNeeded=false;  05/05/11
   //std::cout << "1\n";
@@ -392,11 +392,10 @@ std::cout<<"schedule"<<std::endl;
     if (_masterNextTransaction!=0) _masterNextTransaction->registerTransaction(0);
   }
   //std::cout << "5\n";
-  if (_nextTransaction ==0) std::cout<<"in schedule nextTransaction is 0"<<std::endl;
-  if (aOldTransaction != _nextTransaction) std::cout<<"in schedule aOldTransaction = nextTransaction"<<std::endl;
   if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
   //std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
   else std::cout<<"no need calcStartTimeLength"<<std::endl;
+ std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
 }
 
 //std::string MultiCoreCPU::toString() const{
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index dc7fac968ede4fbcf081a7a2c09d7df83fcc02d8..93667963643af69694341522fbb12cf279f72cb0 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -51,7 +51,8 @@ SchedulableDevice::SchedulableDevice(	ID iID,
 						_deleteScheduler(true),
 						_busyCycles(0),
 						_static_consumPerCycle (15),
-						_dynamic_consumPerCycle (35) {
+						_dynamic_consumPerCycle (35),
+						_cycleTime(0) {
 	_transactList.reserve( BLOCK_SIZE_TRANS );
 }
 
@@ -184,7 +185,7 @@ std::string SchedulableDevice::determineHTMLCellClass( 	std::map<TMLTask*, std::
 }
 
 void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
-        static unsigned int time=0;
+        
 	myfile << "<h2><span>Scheduling for device: "<< _name << "</span></h2>" << std::endl;
 
 	if ( _transactList.size() == 0 ) {
@@ -198,7 +199,10 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
 		TMLTime aCurrTime = 0;
 
 		for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
-		  if( (*i)->getTransactCoreNumber() == time ){
+		  std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
+		  std::cout<<"time : "<<_cycleTime<<std::endl;
+		  std::cout << "CPU:calcSTL: html of CPU " << _name << ": " << (*i)->toString() << std::endl;
+		  if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
 			TMLTransaction* aCurrTrans = *i;
 			unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
 
@@ -225,7 +229,7 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
 			aCurrTime = aCurrTrans->getEndTime();
 		  }
 		}
-		++time;
+		
 
 		myfile << "</tr>" << std::endl << "<tr>";
 
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.h b/simulators/c++2/src_simulator/arch/SchedulableDevice.h
index 0d37a9f56491125b30ef1fb2f96603a99c5c9f8d..022937405b5c494b16c40609ddf7388c1a002d1c 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.h
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.h
@@ -148,6 +148,8 @@ public:
 	static TMLTime getOverallTransNo() { return _overallTransNo; }
 	
 	static TMLTime getOverallTransSize() { return _overallTransSize; }
+	inline void setCycleTime (unsigned int t) { _cycleTime =t; }
+        inline unsigned int getCycleTime() { return _cycleTime; }
 	
 protected:
 	///Unique ID of the device
@@ -171,9 +173,10 @@ protected:
 	///Busy cycles since simulation start
 	TMLTime _busyCycles;
 	unsigned int _static_consumPerCycle; 
-    unsigned int _dynamic_consumPerCycle;
+   	unsigned int _dynamic_consumPerCycle;
 	static TMLTime _overallTransNo;
 	static TMLTime _overallTransSize;
+	unsigned int _cycleTime;
 
 	static void writeHTMLColumn(	std::ofstream& myfile,
 									const unsigned int colSpan,
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index 99bd1bd0b433d3ea646d05b5ab181e9a43aba742..177b6971c009d18f1695883aba68fe05dcf357f3 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -81,9 +81,7 @@ TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevi
   //for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
   for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
     aTempDevice=*i;
-    std::cout<<"test888!!!"<<std::endl;
     aTempTrans=aTempDevice->getNextTransaction();
-    std::cout<<"test999!!!"<<std::endl;
     if (aTempTrans!=0 && aTempTrans->getVirtualLength()>0){
 #ifdef DEBUG_KERNEL
       std::cout << "kernel:getTLET: transaction found on " << aTempDevice->toString() << ": " << aTempTrans->toString() << std::endl;
@@ -291,6 +289,7 @@ void Simulator::latencies2XML(std::ostringstream& glob, int id1, int id2) {
 }
 
 void Simulator::schedule2HTML(std::string& iTraceFileName) const {
+std::cout<<"schedule2HTML--------------------------------------"<<std::endl;
   struct timeval aBegin,aEnd;
   gettimeofday(&aBegin,NULL);
 
@@ -347,8 +346,14 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
 
     //for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
     for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
-      for(unsigned int j = 0; j < (*i)->getAmoutOfCore(); j++) 
+      for(unsigned int j = 0; j < (*i)->getAmoutOfCore(); j++) {
+        std::cout<<"core number is "<<(*i)->getAmoutOfCore()<<std::endl;
 	(*i)->schedule2HTML(myfile);
+	(*i)->setCycleTime((*i)->getCycleTime()+1);
+	std::cout<<"~~~~~~~~~~~~~~~~~~"<<std::endl;
+	}
+        if((*i)->getAmoutOfCore() == 1)
+	   (*i)->setCycleTime(0);
     }
     //for(BusList::const_iterator j=_simComp->getBusIterator(false); j != _simComp->getBusIterator(true); ++j){
     for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
@@ -495,12 +500,10 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
   //std::cout << "after loop2" << std::endl;
   //for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::setRescheduleFlag));
   //for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::schedule));
-  std::cout<<"test666!!!"<<std::endl;
+  std::cout<<"simulate"<<std::endl;
   for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
-  std::cout<<"test777!!!"<<std::endl;
   //std::cout << "after schedule" << std::endl;
-  transLET=getTransLowestEndTime(cpuLET);
-  std::cout<<"test000!!!"<<std::endl;	      
+  transLET=getTransLowestEndTime(cpuLET);	      
   //std::cout << "after getTLET" << std::endl;
 #ifdef LISTENERS_ENABLED
   if (_wasReset) NOTIFY_SIM_STARTED();
@@ -520,6 +523,7 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
     std::cout << "kernel:simulate:cpuLET printed" << std::endl;
 #endif
         bool x = cpuLET->addTransaction(0);
+        cpuLET->setCycleTime(0);
 	//std::cout << "kernel:simulate: x=" << x << std::endl;
   #ifdef DEBUG_KERNEL
     std::cout << "kernel:simulate: AFTER add trans: " << x << std::endl;