diff --git a/src/main/java/ddtranslatorSoclib/AvatarCPU.java b/src/main/java/ddtranslatorSoclib/AvatarCPU.java
index 6fa2f518b42e635e710c74f1049b320a07e29def..b78c2abeca85623320249a3fce98b83894c424b1 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarCPU.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarCPU.java
@@ -63,11 +63,12 @@ public class AvatarCPU extends AvatarComponent{
private int dCacheWords;
private int nb_init;
private int no_proc;
+ private int clusterIndex;
public int monitored;
private LinkedList<AvatarTask> tasksMapped;
- public AvatarCPU(String _cpuName, int _nbOfIRQs,int _ICacheWays, int _ICacheSets, int _ICacheWords, int _DCacheWays, int _DCacheSets, int _DCacheWords , int _nb_init , int _no_proc, int _monitored){
+ public AvatarCPU(String _cpuName, int _nbOfIRQs,int _ICacheWays, int _ICacheSets, int _ICacheWords, int _DCacheWays, int _DCacheSets, int _DCacheWords , int _nb_init , int _no_proc, int _clusterIndex, int _monitored){
cpuName = _cpuName;
nbOfIRQs = _nbOfIRQs;
@@ -79,6 +80,7 @@ public class AvatarCPU extends AvatarComponent{
dCacheWords = _DCacheWords;
nb_init = _nb_init;
no_proc = _no_proc;
+ clusterIndex = _clusterIndex;//DG 2.7.
tasksMapped = new LinkedList<AvatarTask>();
monitored=_monitored;
}
@@ -89,8 +91,13 @@ public class AvatarCPU extends AvatarComponent{
public int getNo_proc(){
return no_proc;
- }
+ }
+ public int getClusterIndex(){
+
+ return clusterIndex;
+ }
+
public String getCpuName(){
return cpuName;
}
diff --git a/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java b/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java
index a83c39db86e20fb02120efd58920fc025ea9e345..7c5f5891abf2f0a2d0355378c7a9487a3fd1597c 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java
@@ -61,14 +61,14 @@ public class AvatarCoproMWMR extends AvatarComponent{
private int nStatus;
private boolean useLLSC;
private int coprocType;
-
+ private int cluster_address;
private AvatarConnectingPoint[] connectingsPoints;
private int nbConnectingPoint = 16 ;
private LinkedList<AvatarTask> tasksMapped;// DG 21.09.
- public AvatarCoproMWMR(String _coprocName,int srcid, int _srcid, int _tgtid, int _plaps, int _fifoToCoprocDepth,int _fifoFromCoprocDepth, int _nToCopro, int _nFromCopro, int _nConfig, int _nStatus, boolean _useLLSC, int _coprocType)
+ public AvatarCoproMWMR(String _coprocName,int srcid, int _srcid, int _tgtid, int _plaps, int _fifoToCoprocDepth,int _fifoFromCoprocDepth, int _nToCopro, int _nFromCopro, int _nConfig, int _nStatus, boolean _useLLSC, int _coprocType, int _cluster_address)
{
coprocName = _coprocName;
srcid = _srcid;
@@ -82,7 +82,8 @@ public class AvatarCoproMWMR extends AvatarComponent{
nStatus = _nStatus;
useLLSC = _useLLSC;
coprocType = _coprocType;
-
+ cluster_address = _cluster_address ;
+
connectingsPoints = new AvatarConnectingPoint[nbConnectingPoint] ;
tasksMapped = new LinkedList<AvatarTask>(); //DG 21.09.
}
@@ -112,6 +113,11 @@ public class AvatarCoproMWMR extends AvatarComponent{
return srcid;
}
+
+ public int getNo_cluster(){
+ return cluster_address;
+ }
+
public int getTgtid(){
return tgtid;
}
diff --git a/src/main/java/ddtranslatorSoclib/AvatarCrossbar.java b/src/main/java/ddtranslatorSoclib/AvatarCrossbar.java
index 0584e84183c77d53c8b76b1e4025e808508d842e..c1fcc6206d6a1f3e5bfdb54c940df9b14f4c08f0 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarCrossbar.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarCrossbar.java
@@ -71,7 +71,7 @@ public class AvatarCrossbar extends AvatarComponent{
public int getNbOfAttachedInitiators(){
return nbOfAttachedInitiators;
}
-
+
public int getNbOfAttachedTargets(){
return nbOfAttachedTargets;
}
diff --git a/src/main/java/ddtranslatorSoclib/AvatarRAM.java b/src/main/java/ddtranslatorSoclib/AvatarRAM.java
index ac9470dad56bdc31fce959eb4ff4f9e1e0488d66..6307ec8212761830b3c7b8f534d953984b33856d 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarRAM.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarRAM.java
@@ -64,12 +64,11 @@ public class AvatarRAM extends AvatarComponent{
LinkedList<AvatarChannel> channelMapped ;
- public AvatarRAM(String _memoryName, int _index, int _dataSize, int _no_ram, int _no_cluster, int _monitored) {
+ public AvatarRAM(String _memoryName, int _dataSize, int _no_cluster, int _no_ram, int _monitored) {
memoryName = _memoryName;
- index = _index;
dataSize = _dataSize;
- no_ram = _no_ram;
no_cluster=_no_cluster;
+ no_ram = _no_ram;
monitored=_monitored;
channelMapped = new LinkedList<AvatarChannel>();
}
@@ -88,7 +87,7 @@ public class AvatarRAM extends AvatarComponent{
public int getNo_cluster(){
return no_cluster;
- }
+ }
public void setNo_ram(int _no_ram){
no_ram = _no_ram;
diff --git a/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java b/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java
index d8126780f286a6f817938041e00f99f4d6c8fb64..77c977257eff894ae3822a5d8e267d82980ddf23 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java
@@ -74,7 +74,7 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
*/
/* initialization of counters, there are at least 6 targets */
- int nb_target = 6;
+ int nb_target;// = 6;
int nb_mwmr_segments = 0;
public AvatarddSpecification( List<AvatarComponent> _components, List<AvatarConnector> _connectors, List<AvatarMappedObject> _mappedObjects, int _nb_target, int _nb_init){
@@ -126,8 +126,10 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
{
if (tty instanceof AvatarTTY){
ttys.add((AvatarTTY)tty);
+ nb_target++;
}
}
+
return ttys;
}
@@ -148,7 +150,8 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
for (AvatarComponent ram : components ) {
if (ram instanceof AvatarRAM){
- rams.add((AvatarRAM)ram);
+ rams.add((AvatarRAM)ram);
+ nb_target++;
}
}
@@ -179,15 +182,14 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
public LinkedList<AvatarCrossbar> getAllCrossbar(){
LinkedList<AvatarCrossbar> crossbars = new LinkedList<AvatarCrossbar>();
- //int i=0;
+
for (AvatarComponent crossbar : components )
{
- //Currently, at least one crossbar -> clustered
+
if (crossbar instanceof AvatarCrossbar){
crossbars.add((AvatarCrossbar)crossbar);
- //crossbar.setClusterIndex(i);
- //i++;
+ nb_target++;
}
}
@@ -206,44 +208,26 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
}*/
- //Currently, we define 1 crossbar = 1 cluster
+
public int getNbClusters(){
return getAllCrossbar().size();
}
- /* DG 23.08. les hardware accelerators proviennent en fait de la specification DIPLODOCUS */
- // copro= new AvatarCoproMWMR("test",0,0,0,10,8,8,1,1,1,1,false);
-
public List<AvatarCoproMWMR> getAllCoproMWMR(){
List<AvatarCoproMWMR> copros = new LinkedList<AvatarCoproMWMR>();
for (AvatarComponent copro : components )
{
if (copro instanceof AvatarCoproMWMR){
-
- //DG 19.09. associate HW task name
- //copro.putName(blockname);
+
copros.add((AvatarCoproMWMR)copro);
+ nb_target++;//DG 9.7. attention not all are target
}
}
return copros;
}
- /* to do, actuellement c'est un hwa generique */
- /* the hardware accelerators must be taken from DIPLODOCUS specification */
- /* public List<DiploHWA> getAllHWA(){
- List<DiploHWA> hwas = new LinkedList<DiploHWA>();
- for (DiploComponent hwa : diplocomponents )
- {
- if (hwa instanceof DiploHWA){
-
-
- hwas.add((DiploHWA)hwa);
- }
- }
- return hwas;
- }*/
-
+
public int getNbCPU(){
return (getAllCPU()).size();
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
index b30cd441329d2284bb4e9420938c033ddea27b14..9bc3c34c0dbd0724ce2fca83d512cae75ca9bda1 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
@@ -51,6 +51,11 @@ import avatartranslator.AvatarRelation;
import avatartranslator.AvatarBlock;
import avatartranslator.AvatarSignal;
import avatartranslator.AvatarSpecification;
+//import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+import ddtranslatorSoclib.AvatarCrossbar;
+
import myutil.TraceManager;
public class Declaration
@@ -58,7 +63,8 @@ public class Declaration
public static AvatarSpecification avspec;
private static String CR = "\n";
private static String CR2 = "\n\n";
-
+ public static AvatarddSpecification avatardd;
+
public static String generateName (AvatarRelation _ar, int _index)
{
return _ar.block1.getName () + "_" +
@@ -66,10 +72,49 @@ public class Declaration
_ar.block2.getName () + "_" + _ar.getSignal2 (_index).getName ();
}
- public static String getDeclarations (AvatarSpecification _avspec)
+
+ public static int cpus_in_cluster(AvatarddSpecification dd,int cluster_no){
+ avatardd = dd;
+ int cpus=0;
+ for (AvatarConnector connector : avatardd.getConnectors()){
+ AvatarConnectingPoint my_p1= connector.get_p1();
+ AvatarConnectingPoint my_p2= connector.get_p2();
+
+ AvatarComponent comp1 = my_p1.getComponent();
+ AvatarComponent comp2 = my_p2.getComponent();
+ if (comp1 instanceof AvatarCPU){
+ AvatarCPU comp1cpu = (AvatarCPU)comp1;
+ cpus++;
+ }
+
+ }
+ return cpus;
+ }
+
+public static int rams_in_cluster(AvatarddSpecification dd,int cluster_no){
+ avatardd = dd;
+ int rams=0;
+ for (AvatarConnector connector : avatardd.getConnectors()){
+ AvatarConnectingPoint my_p1= connector.get_p1();
+ AvatarConnectingPoint my_p2= connector.get_p2();
+
+ AvatarComponent comp1 = my_p1.getComponent();
+ AvatarComponent comp2 = my_p2.getComponent();
+ if (comp1 instanceof AvatarRAM){
+ AvatarRAM comp1cpu = (AvatarRAM)comp1;
+ rams++;
+ }
+
+ }
+ return rams;
+ }
+
+
+
+ public static String getDeclarations (AvatarddSpecification _dd, AvatarSpecification _avspec)
{
avspec = _avspec;
-
+ avatardd = _dd;
String declaration =
"//----------------------------Instantiation-------------------------------"
+ CR2;
@@ -130,7 +175,7 @@ public class Declaration
{
declaration =
declaration +
- "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,5), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ CR;
}
@@ -145,20 +190,20 @@ public class Declaration
{
declaration =
declaration +
- "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);"
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,4), maptab, 1, true);"
+ CR2;
}
if (nb_clusters == 0)
{
declaration +=
- "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);"
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(7), maptab);"
+ CR;
}
else
{
declaration +=
- "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);"
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,7), maptab);"
+ CR;
}
@@ -171,25 +216,16 @@ public class Declaration
{
declaration +=
"caba::VciMultiTty<vci_param> " + tty.getTTYName () +
- "(\"" + tty.getTTYName () + "\", IntTab(" +
- tty.getNo_target () + "), maptab, \"vci_multi_tty" +
+ "(\"" + tty.getTTYName () + "\", IntTab(" + 8
+ //tty.getNo_target () + "),
+ + "), maptab, \"vci_multi_tty" +
i + "\", NULL);" + CR;
i++;
last_tty = tty.getNo_target () + 1;
}
//target address depends on number of TTYs and RAMs
-
- if (nb_clusters == 0)
- {
- // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
- // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(last_tty+3)+"), maptab);" + CR;
- }
- else
- {
- // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
- }
-
+
for (AvatarRAM ram:TopCellGenerator.avatardd.
getAllRAM ())
if (ram.getIndex () == 0)
@@ -211,16 +247,28 @@ public class Declaration
}
else
{
- int i = 0;
- for (AvatarTTY tty:TopCellGenerator.avatardd.
- getAllTTY ())
- {
+
+ for (AvatarTTY tty:TopCellGenerator.avatardd.getAllTTY ())
+
+ { int cluster_no=tty.getNo_cluster();
+ int nb_ram =
+ rams_in_cluster(avatardd, cluster_no);
+
+ if(cluster_no==0){
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_cluster () + "," + (nb_ram+10) +
+ "), maptab, \"vci_multi_tty" + cluster_no + "\", NULL);" + CR;
+ }
+ else{
declaration +=
"caba::VciMultiTty<vci_param> " + tty.getTTYName () +
"(\"" + tty.getTTYName () + "\", IntTab(" +
- tty.getNo_cluster () + "," + tty.getNo_target () +
- "), maptab, \"vci_multi_tty" + i + "\", NULL);" + CR;
- i++;
+ tty.getNo_cluster () + "," + nb_ram +
+ "), maptab, \"vci_multi_tty" + cluster_no + "\", NULL);" + CR;
+ }
+
}
for (AvatarRAM ram:TopCellGenerator.avatardd.
@@ -236,13 +284,13 @@ public class Declaration
declaration +=
"caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
- + last_tty + "));" + CR;
+ + 8 + "));" + CR;
declaration +=
"caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
- + (last_tty + 1) + "), \"soclib0\");" + CR;
+ + 9 + "), \"soclib0\");" + CR;
declaration +=
"caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
- + (last_tty + 2) + "),\"block0.iso\", 2048);" + CR;
+ + 10 + "),\"block0.iso\", 2048);" + CR;
//non-clustered version
int hwa_no = 0;
@@ -252,7 +300,8 @@ public class Declaration
for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
getAllCoproMWMR ())
{
-
+ nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();// DG 6.7. ne marche pas encire (IntTab(i) instead of (i,j) for clustered
+ if(nb_clusters==0){
declaration +=
"caba::VciMwmrController<vci_param> " +
copro.getCoprocName () + "_wrapper(\"" +
@@ -265,7 +314,24 @@ public class Declaration
"," + copro.getNConfig () + "," +
copro.getNStatus () + "," + copro.getUseLLSC () +
");" + CR2;
+ }
+ else{
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", IntTab(" + copro.getNo_cluster () + "," +
+ (init_no - 1) +" ,IntTab(" + copro.getNo_cluster () + "," +
+ target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+}
+
//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
if (copro.getCoprocType () == 0)
@@ -305,13 +371,13 @@ public class Declaration
else
{
declaration +=
- "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));"
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,8));"
+ CR;
declaration +=
- "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");"
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,9), \"soclib0\");"
+ CR;
declaration +=
- "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);"
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,10),\"block0.iso\", 2048);"
+ CR;
int hwa_no = 0;
@@ -433,7 +499,7 @@ public class Declaration
{
/***************************************/
- /* clustered interconnect architecture */
+ /* clustered interconnect architecture */
/***************************************/
@@ -441,6 +507,13 @@ public class Declaration
getAllBus ())
{
+ TraceManager.addDev ("VGSB initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("VGSB targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
declaration +=
"soclib::caba::VciVgsb<vci_param> vgsb(\"" +
bus.getBusName () + "\"" + " , maptab, " +
@@ -453,12 +526,8 @@ public class Declaration
for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
getAllVgmn ())
{
- TraceManager.addDev ("initiators: " +
- TopCellGenerator.avatardd.
- getNb_init ());
- TraceManager.addDev ("targets: " +
- TopCellGenerator.avatardd.
- getNb_target ());
+ TraceManager.addDev ("VGMN initiators: " + nb_clusters);
+ TraceManager.addDev ("VGMN targets: " +nb_clusters);
declaration +=
"soclib::caba::VciVgmn<vci_param> vgmn (\"" +
@@ -466,52 +535,29 @@ public class Declaration
nb_clusters + "," + nb_clusters + "," +
vgmn.getMinLatency () + "," + vgmn.getFifoDepth () +
");" + CR2;
-
}
- int i = 0;
+
for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.
- getAllCrossbar
- ())
- {
-
- crossbar.setClusterIndex (i);
-
- if (crossbar.getClusterIndex () == 0)
- {
- crossbar.setNbOfAttachedInitiators (nb_clusters);
- crossbar.setNbOfAttachedTargets (13);
- }
- else
- {
-
- crossbar.setNbOfAttachedInitiators (1);
- crossbar.setNbOfAttachedTargets (1);
- }
-
- TraceManager.addDev ("initiators: " +
- crossbar.
- getNbOfAttachedInitiators ());
- TraceManager.addDev ("targets: " +
- crossbar.getNbOfAttachedTargets ());
+ getAllCrossbar())
+ {
+
+ int cluster_no = crossbar.getClusterIndex ();
+ TraceManager.addDev ("CROSSBAR" +cluster_no+" cpus: " +
+ cpus_in_cluster(avatardd, cluster_no) );
+ TraceManager.addDev ("CROSSBAR " +cluster_no+" rams: " +
+ rams_in_cluster(avatardd, cluster_no) );
declaration +=
"soclib::caba::VciLocalCrossbar<vci_param> crossbar" +
crossbar.getClusterIndex () + "(\"" +
crossbar.getCrossbarName () + "\"" +
- " , maptab, IntTab(" + crossbar.getClusterIndex () +
- "),IntTab(" + crossbar.getClusterIndex () + "), " +
- crossbar.getNbOfAttachedInitiators () + ", " +
- crossbar.getNbOfAttachedTargets () + ");" + CR2;
-
- //if CROSSBAR was not last in input file, update here
- crossbar.
- setNbOfAttachedInitiators (TopCellGenerator.avatardd.
- getNb_init ());
- crossbar.
- setNbOfAttachedTargets (TopCellGenerator.avatardd.
- getNb_target ());
- i++;
+ " , maptab, " + crossbar.getClusterIndex () +
+ "," + crossbar.getClusterIndex () + ", " +
+ cpus_in_cluster(avatardd, cluster_no) + ", " +
+ rams_in_cluster(avatardd, cluster_no) + ");" + CR2;
+ //if CROSSBAR was not last in input file, update here
+
}
}
int i = 0;
@@ -580,7 +626,7 @@ public class Declaration
}
}
}
-
+
return declaration;
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java-orig b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java-orig
new file mode 100755
index 0000000000000000000000000000000000000000..313ac6c627dc90a7ca4ac4f2565ee9545a16839c
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java-orig
@@ -0,0 +1,605 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015
+ v2.1 Daniela GENIUS, 2016, 2017 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.*;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarBlock;
+import avatartranslator.AvatarSignal;
+import avatartranslator.AvatarSpecification;
+import myutil.TraceManager;
+
+public class Declaration
+{
+ public static AvatarSpecification avspec;
+ private static String CR = "\n";
+ private static String CR2 = "\n\n";
+
+ public static String generateName (AvatarRelation _ar, int _index)
+ {
+ return _ar.block1.getName () + "_" +
+ _ar.getSignal1 (_index).getName () + "__" +
+ _ar.block2.getName () + "_" + _ar.getSignal2 (_index).getName ();
+ }
+
+ public static String getDeclarations (AvatarSpecification _avspec)
+ {
+ avspec = _avspec;
+
+ String declaration =
+ "//----------------------------Instantiation-------------------------------"
+ + CR2;
+
+
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+
+ boolean trace_caba = true;
+
+ if (nb_clusters == 0)
+ {
+ declaration += CR
+ +
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration += CR
+ +
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);"
+ + CR;
+ }
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);"
+ + CR;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);"
+ + CR;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration =
+ declaration +
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
+ else
+ {
+ declaration =
+ declaration +
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration =
+ declaration +
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);"
+ + CR2;
+ }
+ else
+ {
+ declaration =
+ declaration +
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);"
+ + CR2;
+ }
+
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);"
+ + CR;
+ }
+
+ int last_tty = 0;
+ if (nb_clusters == 0)
+ {
+ int i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_target () + "), maptab, \"vci_multi_tty" +
+ i + "\", NULL);" + CR;
+ i++;
+ last_tty = tty.getNo_target () + 1;
+ }
+
+ //target address depends on number of TTYs and RAMs
+
+ if (nb_clusters == 0)
+ {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(last_tty+3)+"), maptab);" + CR;
+ }
+ else
+ {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
+ }
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ if (ram.getIndex () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" +
+ ram.getMemoryName () + "\"" +
+ ", IntTab(2), maptab);" + CR;
+ }
+ else
+ {
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" +
+ ram.getMemoryName () + "\"" + ", IntTab(" +
+ ram.getNo_target () + "), maptab);" + CR;
+ }
+ }
+ else
+ {
+ int i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_cluster () + "," + tty.getNo_target () +
+ "), maptab, \"vci_multi_tty" + i + "\", NULL);" + CR;
+ i++;
+ }
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" + ram.getMemoryName () +
+ "\"" + ", IntTab(" + ram.getNo_cluster () + "," +
+ ram.getNo_target () + "), maptab);" + CR2;
+ }
+ if (nb_clusters == 0)
+ {
+
+ declaration +=
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
+ + last_tty + "));" + CR;
+ declaration +=
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
+ + (last_tty + 1) + "), \"soclib0\");" + CR;
+ declaration +=
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
+ + (last_tty + 2) + "),\"block0.iso\", 2048);" + CR;
+
+ //non-clustered version
+ int hwa_no = 0;
+ //int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);
+ int init_no = TopCellGenerator.avatardd.getNb_init ();
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+ nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();// DG 6.7. ne marche pas encire (IntTab(i) instead of (i,j) for clustered
+ if(nb_clusters==0){
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", maptab, IntTab(" + (init_no - 1) +
+ "), IntTab(" + target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+ }
+ else{
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", IntTab(" + copro.getNo_cluster () + "," +
+ (init_no - 1) +" ,IntTab(" + copro.getNo_cluster () + "," +
+ target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+}
+
+
+//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+
+ if (copro.getCoprocType () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciInputEngine<vci_param>" +
+ copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,\"input.txt\",1024,1,8);" + CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ declaration +=
+ "soclib::caba::VciOutputEngine<vci_param>"
+ + copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"
+ + CR;
+ }
+
+
+ else
+ {
+ declaration +=
+ // "dsx::caba::MyHWA" + hwa_no + " hwa" +
+ // hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+ "dsx::caba::MyHWA(\""+copro.getCoprocName ()+ "\");" + CR2;
+
+ }
+ }
+ init_no++;
+ target_no++;
+ }
+ }
+ else
+ {
+ declaration +=
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));"
+ + CR;
+ declaration +=
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");"
+ + CR;
+ declaration +=
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);"
+ + CR;
+
+ int hwa_no = 0;
+ //int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);
+ int init_no = TopCellGenerator.avatardd.getNb_init ();
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", maptab, IntTab(" + (init_no - 1) +
+ "), IntTab(" + target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+
+ //one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+ // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
+
+ if (copro.getCoprocType () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciInputEngine<vci_param>" +
+ copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,\"input.txt\",1024,1,8);" + CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ declaration +=
+ "soclib::caba::VciOutputEngine<vci_param>"
+ + copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"
+ + CR;
+ }
+
+
+ else
+ {
+ declaration +=
+ "dsx::caba::MyHWA" + hwa_no + " hwa" +
+ hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+
+ hwa_no++;
+ }
+ }
+ target_no++;
+ init_no++;
+ }
+
+ }
+
+ if (nb_clusters == 0)
+ {
+
+ for (AvatarBus bus:TopCellGenerator.avatardd.
+ getAllBus ())
+ {
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+ declaration +=
+ "soclib::caba::VciVgsb<vci_param> vgsb(\"" +
+ bus.getBusName () + "\"" + " , maptab," + (3 +
+ TopCellGenerator.
+ avatardd.getNb_init
+ ()) + "," +
+ (TopCellGenerator.avatardd.getNb_target () + 3) +
+ ");" + CR2;
+ int i = 0;
+
+ }
+
+ for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
+ getAllVgmn ())
+ {
+ /* set default values */
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+
+ if (vgmn.getMinLatency () < 2)
+ vgmn.setMinLatency (10); //default value; must be > 2
+ if (vgmn.getFifoDepth () < 2)
+ vgmn.setFifoDepth (8); //default value; must be > 2
+
+ declaration +=
+ "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
+ vgmn.getVgmnName () + "\"" + " , maptab, " + (3 +
+ TopCellGenerator.
+ avatardd.
+ getNb_init
+ ()) +
+ "," + (TopCellGenerator.avatardd.getNb_target () +
+ 3) + "," + vgmn.getMinLatency () + "," +
+ vgmn.getFifoDepth () + ");" + CR2;
+ }
+
+ }
+ else
+ {
+
+ /***************************************/
+ /* clustered interconnect architecture */
+ /***************************************/
+
+
+ for (AvatarBus bus:TopCellGenerator.avatardd.
+ getAllBus ())
+ {
+
+ declaration +=
+ "soclib::caba::VciVgsb<vci_param> vgsb(\"" +
+ bus.getBusName () + "\"" + " , maptab, " +
+ +nb_clusters + "," + nb_clusters + ");" + CR2;
+
+ //if BUS was not last in input file, update here
+ int i = 0;
+ }
+
+ for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
+ getAllVgmn ())
+ {
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+ declaration +=
+ "soclib::caba::VciVgmn<vci_param> vgmn (\"" +
+ vgmn.getVgmnName () + "\"" + " , maptab, " +
+ nb_clusters + "," + nb_clusters + "," +
+ vgmn.getMinLatency () + "," + vgmn.getFifoDepth () +
+ ");" + CR2;
+
+ }
+
+ int i = 0;
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.
+ getAllCrossbar
+ ())
+ {
+
+ crossbar.setClusterIndex (i);
+
+ if (crossbar.getClusterIndex () == 0)
+ {
+ crossbar.setNbOfAttachedInitiators (nb_clusters);
+ crossbar.setNbOfAttachedTargets (13);
+ }
+ else
+ {
+
+ crossbar.setNbOfAttachedInitiators (1);
+ crossbar.setNbOfAttachedTargets (1);
+ }
+
+ TraceManager.addDev ("initiators: " +
+ crossbar.
+ getNbOfAttachedInitiators ());
+ TraceManager.addDev ("targets: " +
+ crossbar.getNbOfAttachedTargets ());
+
+ declaration +=
+ "soclib::caba::VciLocalCrossbar<vci_param> crossbar" +
+ crossbar.getClusterIndex () + "(\"" +
+ crossbar.getCrossbarName () + "\"" +
+ " , maptab, " + crossbar.getClusterIndex () +
+ "," + crossbar.getClusterIndex () + ", " +
+ crossbar.getNbOfAttachedInitiators () + ", " +
+ crossbar.getNbOfAttachedTargets () + ");" + CR2;
+
+ //if CROSSBAR was not last in input file, update here
+ crossbar.
+ setNbOfAttachedInitiators (TopCellGenerator.avatardd.
+ getNb_init ());
+ crossbar.
+ setNbOfAttachedTargets (TopCellGenerator.avatardd.
+ getNb_target ());
+ i++;
+ }
+ }
+ int i = 0;
+ //monitoring CPU by logger(1)
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+
+ if (cpu.getMonitored () == 1)
+ {
+
+ declaration +=
+ "soclib::caba::VciLogger<vci_param> logger" + i +
+ "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ }
+
+ int j = 0;
+ //monitoring RAM either by logger(1) or stats (2)
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+
+ }
+ if (ram.getMonitored () == 1)
+ {
+
+ declaration +=
+ "soclib::caba::VciLogger<vci_param> logger" + i +
+ "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ else
+ {
+ if (ram.getMonitored () == 2)
+ {
+
+ String strArray = "";
+
+ for (AvatarRelation ar:avspec.
+ getRelations
+ ())
+ {
+
+ for (i = 0; i < ar.nbOfSignals (); i++)
+ {
+
+ AvatarSignal as1 = ar.getSignal1 (i);
+ AvatarSignal as2 = ar.getSignal2 (i);
+
+ String chname = generateName (ar, i);
+ strArray =
+ strArray + "\"" + chname + "\",";
+ }
+
+ }
+
+ declaration +=
+ "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"
+ + j + "(\"mwmr_stats" + j +
+ "\",maptab, data_ldr, \"mwmr" + j +
+ ".log\",stringArray(" + strArray + "NULL));" +
+ CR2;
+ j++;
+ }
+ }
+ }
+
+ return declaration;
+ }
+
+}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java b/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java
index a57a58bf0d8b00884b6f716dd956ff64dc4eef5a..a54bc628547f30648911d47e0ea8e7e204e32c97 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Deployinfo.java
@@ -1,326 +1,326 @@
-
-
-/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- Daniela Genius, Lip6, UMR 7606
-
- ludovic.apvrille AT enst.fr
- daniela.genius@lip6.fr
-
- This software is a computer program whose purpose is to allow the
- edition of TURTLE analysis, design and deployment diagrams, to
- allow the generation of RT-LOTOS or Java code from this diagram,
- and at last to allow the analysis of formal validation traces
- obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- from INRIA Rhone-Alpes.
-
- This software is governed by the CeCILL license under French law and
- abiding by the rules of distribution of free software. You can use,
- modify and/ or redistribute the software under the terms of the CeCILL
- license as circulated by CEA, CNRS and INRIA at the following URL
- "http://www.cecill.info".
-
- As a counterpart to the access to the source code and rights to copy,
- modify and redistribute granted by the license, users are provided only
- with a limited warranty and the software's author, the holder of the
- economic rights, and the successive licensors have only limited
- liability.
-
- In this respect, the user's attention is drawn to the risks associated
- with loading, using, modifying and/or developing or reproducing the
- software by the user in light of its specific status of free software,
- that may mean that it is complicated to manipulate, and that also
- therefore means that it is reserved for developers and experienced
- professionals having in-depth computer knowledge. Users are therefore
- encouraged to load and test the software's suitability as regards their
- requirements in conditions enabling the security of their systems and/or
- data to be ensured and, more generally, to use and operate it in the
- same conditions as regards security.
-
- The fact that you are presently reading this means that you have had
- knowledge of the CeCILL license and that you accept its terms.
-*/
-
-/* This class generates the deployment info for the ldscript*/
-
-
-/* authors: v1.0 Daniela GENIUS 2015 modified for clustered architecture 08/2016 */
-
-/*
-
-/* here is an example of an ldscript :
-#define CHANNEL_0_NAME channel0
-#define CHANNEL_1_NAME channel1
-
-#define DEPLOY_RAM_0_NAME channel_ram0
-#define DEPLOY_RAM_0_ADDR 0x6f000000
-#define DEPLOY_RAM_0_SIZE 0x01000000
-
-#define DEPLOY_RAM_1_NAME channel_ram1
-#define DEPLOY_RAM_1_ADDR 0x5f000000
-#define DEPLOY_RAM_1_SIZE 0x01000000
-
-#define MAP_A\
- .channel0 : { \
- __channel_0_start = ABSOLUTE(.);\
- *(section_channel0)\
- } > DEPLOY_RAM_0_NAME\
- .channel1 : { \
- __channel_1_start = ABSOLUTE(.);\
- *(section_channel1) \
- } > DEPLOY_RAM_1_NAME
- */
-
-package ddtranslatorSoclib.toTopCell;
-
-import ddtranslatorSoclib.*;
-import ddtranslatorSoclib.toSoclib.*;
-
-import avatartranslator.*;
-import myutil.Conversion;
-import myutil.FileException;
-import myutil.FileUtils;
-import myutil.TraceManager;
-
-import java.io.File;
-import java.util.LinkedList;
-import java.util.List;
-import java.util.Vector;
-
-public class Deployinfo {
-
- private final static String CR = "\n";
- private final static String CR2 = "\n\n";
-
- public static AvatarSpecification avspec;//DG 15.05.2017
- public static AvatarddSpecification avddspec;
- private Vector<?> warnings;
-
- private MainFileSoclib mainFile;
- private Vector<TaskFileSoclib> taskFiles;
- private String makefile_src;
- private String makefile_SocLib;
- //
- /* for the moment, this is specific to PowerPC */
-
- public Deployinfo(AvatarddSpecification _avddspec, AvatarSpecification _avspec) {
- avspec = _avspec;
- avddspec = _avddspec;
- taskFiles = new Vector<TaskFileSoclib>();
- }
-
- public static String getDeployInfo() {
-
- int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
-
- String deployinfo = CR;
-
- /* we will have to dimension the segments according to the number of clusters, number of RAMS etc. */
-
- /* first, determine the "step" between segments dedicated to a cluster */
-
- int CLUSTER_SIZE;
-
- //if the user does not specify the size, take default value
- if(nb_clusters<16) {
- CLUSTER_SIZE = 268435456;
- }
- else {
- CLUSTER_SIZE = 134217728;
- } // to be refined, cf DSX -> dynamically adapt
-
-
- int size;
-
- /* there can be many RAMS, but then must be smaller dimensioned */
-
- int i=0;
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
-
- /* data memory always starts at 0x10000000 */
- int address_start = 268435456;
- String string_adress_start = Integer.toHexString(i*268435456);
-
- /* segment size is either given by the user or a default value is calculated */
- if(ram.getDataSize()==0){
-
- if((nb_clusters<16)||(TopCellGenerator.avatardd.getAllRAM().size()<16)){
- size = 268435456;
-
- }
- else {//smaller segments
- size = 134217728;
- } // to be refined, a la DSX
- }
- else{
- size = ram.getDataSize();
- }
- ram.setDataSize(size);
- //ram.setDataSize(0);
- size = ram.getDataSize(); // this is the hardware RAM size
-
+
+
+/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ Daniela Genius, Lip6, UMR 7606
+
+ ludovic.apvrille AT enst.fr
+ daniela.genius@lip6.fr
+
+ This software is a computer program whose purpose is to allow the
+ edition of TURTLE analysis, design and deployment diagrams, to
+ allow the generation of RT-LOTOS or Java code from this diagram,
+ and at last to allow the analysis of formal validation traces
+ obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ from INRIA Rhone-Alpes.
+
+ This software is governed by the CeCILL license under French law and
+ abiding by the rules of distribution of free software. You can use,
+ modify and/ or redistribute the software under the terms of the CeCILL
+ license as circulated by CEA, CNRS and INRIA at the following URL
+ "http://www.cecill.info".
+
+ As a counterpart to the access to the source code and rights to copy,
+ modify and redistribute granted by the license, users are provided only
+ with a limited warranty and the software's author, the holder of the
+ economic rights, and the successive licensors have only limited
+ liability.
+
+ In this respect, the user's attention is drawn to the risks associated
+ with loading, using, modifying and/or developing or reproducing the
+ software by the user in light of its specific status of free software,
+ that may mean that it is complicated to manipulate, and that also
+ therefore means that it is reserved for developers and experienced
+ professionals having in-depth computer knowledge. Users are therefore
+ encouraged to load and test the software's suitability as regards their
+ requirements in conditions enabling the security of their systems and/or
+ data to be ensured and, more generally, to use and operate it in the
+ same conditions as regards security.
+
+ The fact that you are presently reading this means that you have had
+ knowledge of the CeCILL license and that you accept its terms.
+*/
+
+/* This class generates the deployment info for the ldscript*/
+
+
+/* authors: v1.0 Daniela GENIUS 2015 modified for clustered architecture 08/2016 */
+
+/*
+
+/* here is an example of an ldscript :
+#define CHANNEL_0_NAME channel0
+#define CHANNEL_1_NAME channel1
+
+#define DEPLOY_RAM_0_NAME channel_ram0
+#define DEPLOY_RAM_0_ADDR 0x6f000000
+#define DEPLOY_RAM_0_SIZE 0x01000000
+
+#define DEPLOY_RAM_1_NAME channel_ram1
+#define DEPLOY_RAM_1_ADDR 0x5f000000
+#define DEPLOY_RAM_1_SIZE 0x01000000
+
+#define MAP_A\
+ .channel0 : { \
+ __channel_0_start = ABSOLUTE(.);\
+ *(section_channel0)\
+ } > DEPLOY_RAM_0_NAME\
+ .channel1 : { \
+ __channel_1_start = ABSOLUTE(.);\
+ *(section_channel1) \
+ } > DEPLOY_RAM_1_NAME
+ */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.*;
+import ddtranslatorSoclib.toSoclib.*;
+
+import avatartranslator.*;
+import myutil.Conversion;
+import myutil.FileException;
+import myutil.FileUtils;
+import myutil.TraceManager;
+
+import java.io.File;
+import java.util.LinkedList;
+import java.util.List;
+import java.util.Vector;
+
+public class Deployinfo {
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public static AvatarSpecification avspec;//DG 15.05.2017
+ public static AvatarddSpecification avddspec;
+ private Vector<?> warnings;
+
+ private MainFileSoclib mainFile;
+ private Vector<TaskFileSoclib> taskFiles;
+ private String makefile_src;
+ private String makefile_SocLib;
+ //
+ /* for the moment, this is specific to PowerPC */
+
+ public Deployinfo(AvatarddSpecification _avddspec, AvatarSpecification _avspec) {
+ avspec = _avspec;
+ avddspec = _avddspec;
+ taskFiles = new Vector<TaskFileSoclib>();
+ }
+
+ public static String getDeployInfo() {
+
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
+
+ String deployinfo = CR;
+
+ /* we will have to dimension the segments according to the number of clusters, number of RAMS etc. */
+
+ /* first, determine the "step" between segments dedicated to a cluster */
+
+ int CLUSTER_SIZE;
+
+ //if the user does not specify the size, take default value
+ if(nb_clusters<16) {
+ CLUSTER_SIZE = 268435456;
+ }
+ else {
+ CLUSTER_SIZE = 134217728;
+ } // to be refined, cf DSX -> dynamically adapt
+
+
+ int size;
+
+ /* there can be many RAMS, but then must be smaller dimensioned */
+
+ int i=0;
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+
+ /* data memory always starts at 0x10000000 */
+ int address_start = 268435456;
+ String string_adress_start = Integer.toHexString(i*268435456);
+
+ /* segment size is either given by the user or a default value is calculated */
+ if(ram.getDataSize()==0){
+
+ if((nb_clusters<16)||(TopCellGenerator.avatardd.getAllRAM().size()<16)){
+ size = 268435456;
+
+ }
+ else {//smaller segments
+ size = 134217728;
+ } // to be refined, a la DSX
+ }
+ else{
+ size = ram.getDataSize();
+ }
+ ram.setDataSize(size);
+ //ram.setDataSize(0);
+ size = ram.getDataSize(); // this is the hardware RAM size
-
- String string_size_half = (Integer.toHexString(size/2)); //segments on this are half uram, half cram
-
- deployinfo += "#define CACHED_RAM" + ram.getIndex() + "_NAME cram" + ram.getIndex() + CR;
- deployinfo = deployinfo + "#define CACHED_RAM" + ram.getIndex() + "_ADDR 0x" + Integer.toHexString(address_start+i*CLUSTER_SIZE) + CR;
- // 31.08. simplifie
- deployinfo = deployinfo + "#define CACHED_RAM" + ram.getIndex() + "_SIZE 0x"+ string_size_half + CR;
- deployinfo += "#define DEPLOY_RAM" + ram.getIndex() + "_NAME uram" + ram.getIndex() + CR;
- int cacheability_bit= 2097152; //0x00200000
- deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getIndex() + "_ADDR 0x" + Integer.toHexString(address_start+i*CLUSTER_SIZE+size/2+cacheability_bit) + CR;
- // 31.08. simplifie
- deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getIndex() + "_SIZE 0x"+ (string_size_half) + CR;
-
- i++;
- }
- //Calculate Adresses of MWMR segments, one for each hardware accellerator
- i=0;
-
- for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()) {
- deployinfo = deployinfo + "#define MWMR_RAM" + i + "_NAME mwmr_ram" + i + CR;
- deployinfo = deployinfo + "#define MWMR_RAM" + i + "_ADDR 0xA02" + Integer.toHexString(i*4096) + CR;
- deployinfo = deployinfo + "#define MWMR_RAM" + i + "_SIZE 0x1000"+ CR;
- i++;
- }
-
- return deployinfo;
- }
-
- /* public static String getDeployInfoMap() {
- int i=0;
- String deployinfo_map = CR;
- int nb_signals=0;
- deployinfo_map += "#define MAP_A\\" + CR;
-
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- //if (!(ram.getChannels().isEmpty())){
- // for (AvatarChannel channel : ram.getChannels()) {
-
- //DG 15.05.2017
- for (AvatarRelation relation : avspec.getRelations()) {
- //if (!(ram.getRelations().isEmpty())){
- //
- for(i=0; i<relation.nbOfSignals() ; i++) {//DG 15.05.2017
- deployinfo_map = deployinfo_map +"\n .channel"+nb_signals+" : { \\" + CR;
- deployinfo_map = deployinfo_map + "*(section_channel"+nb_signals+ ")\\"+ CR;
-
- deployinfo_map=deployinfo_map+ "} > uram"+ram.getIndex()+"\\"+ CR;
- i++;nb_signals++;
- }
- }
-
- i=0;nb_signals=0;
-
-// for (AvatarChannel channel : ram.getChannels()) {
- for (AvatarRelation relation : avspec.getRelations()) {
-//DG 15.05.2017
-
- for(i=0; i<relation.nbOfSignals() ; i++) {//DG 15.05.2017
+
+
+ String string_size_half = (Integer.toHexString(size/2)); //segments on this are half uram, half cram
+
+ deployinfo += "#define CACHED_RAM" + ram.getIndex() + "_NAME cram" + ram.getIndex() + CR;
+ deployinfo = deployinfo + "#define CACHED_RAM" + ram.getIndex() + "_ADDR 0x" + Integer.toHexString(address_start+i*CLUSTER_SIZE) + CR;
+ // 31.08. simplifie
+ deployinfo = deployinfo + "#define CACHED_RAM" + ram.getIndex() + "_SIZE 0x"+ string_size_half + CR;
+ deployinfo += "#define DEPLOY_RAM" + ram.getIndex() + "_NAME uram" + ram.getIndex() + CR;
+ int cacheability_bit= 2097152; //0x00200000
+ deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getIndex() + "_ADDR 0x" + Integer.toHexString(address_start+i*CLUSTER_SIZE+size/2+cacheability_bit) + CR;
+ // 31.08. simplifie
+ deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getIndex() + "_SIZE 0x"+ (string_size_half) + CR;
+
+ i++;
+ }
+ //Calculate Adresses of MWMR segments, one for each hardware accellerator
+ i=0;
+
+ for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ deployinfo = deployinfo + "#define MWMR_RAM" + i + "_NAME mwmr_ram" + i + CR;
+ deployinfo = deployinfo + "#define MWMR_RAM" + i + "_ADDR 0xA02" + Integer.toHexString(i*4096) + CR;
+ deployinfo = deployinfo + "#define MWMR_RAM" + i + "_SIZE 0x1000"+ CR;
+ i++;
+ }
+
+ return deployinfo;
+ }
+
+ /* public static String getDeployInfoMap() {
+ int i=0;
+ String deployinfo_map = CR;
+ int nb_signals=0;
+ deployinfo_map += "#define MAP_A\\" + CR;
+
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ //if (!(ram.getChannels().isEmpty())){
+ // for (AvatarChannel channel : ram.getChannels()) {
+
+ //DG 15.05.2017
+ for (AvatarRelation relation : avspec.getRelations()) {
+ //if (!(ram.getRelations().isEmpty())){
+ //
+ for(i=0; i<relation.nbOfSignals() ; i++) {//DG 15.05.2017
+ deployinfo_map = deployinfo_map +"\n .channel"+nb_signals+" : { \\" + CR;
+ deployinfo_map = deployinfo_map + "*(section_channel"+nb_signals+ ")\\"+ CR;
+
+ deployinfo_map=deployinfo_map+ "} > uram"+ram.getIndex()+"\\"+ CR;
+ i++;nb_signals++;
+ }
+ }
+
+ i=0;nb_signals=0;
+
+// for (AvatarChannel channel : ram.getChannels()) {
+ for (AvatarRelation relation : avspec.getRelations()) {
+//DG 15.05.2017
+
+ for(i=0; i<relation.nbOfSignals() ; i++) {//DG 15.05.2017
-
- deployinfo_map = deployinfo_map +"\n .lock"+nb_signals+" : { \\" + CR;
- deployinfo_map = deployinfo_map + "*(section_lock"+nb_signals+ ")\\"+ CR;
- // if(use_vcilocks) deployinfo_map=deployinfo_map+ "} > vci_locks\\"+ CR;
- deployinfo_map=deployinfo_map+ "} > uram0\\"+ CR;//DG 27.06. no ramlocks
- i++; nb_signals++;
- }
-
- }
- }
- return deployinfo_map;
- }*/
-
- public static String getDeployInfoMap(AvatarSpecification _avspec) {
- avspec = _avspec;
- int i=0;
- String deployinfo_map = CR;
- int j;
-
- deployinfo_map += "#define MAP_A\\" + CR;
- try{
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- // if (/*!*/(ram.getChannels().isEmpty())){ //"!" removed because it returned the wrong results. Logic is now incorrect but results are correct (needs further investigating) CD 20.6
- if (!(ram.getChannels().isEmpty())){
- for(AvatarRelation ar: avspec.getRelations()){
- for (j=0;j<ar.nbOfSignals();j++) {
- deployinfo_map = deployinfo_map + "\n .channel"+i+" : {";
- deployinfo_map = deployinfo_map + "*(section_channel"+i+ ")";
- deployinfo_map = deployinfo_map + "} > uram" + ram.getIndex() + CR; //ram n° was incorrect (see above)
- i++;
- }
- }
-
- i=0;
- for(AvatarRelation ar: avspec.getRelations()){
- for (j=0;j<ar.nbOfSignals();j++) { //CD 15.06 dynamic to signal number
- deployinfo_map = deployinfo_map + "\n .lock"+i+" : { " ;
- deployinfo_map = deployinfo_map + "*(section_lock" + i + ")";
- deployinfo_map = deployinfo_map + "} > uram" + ram.getIndex() + CR;
- i++;
- }
- }
- }
- }
- }catch (Exception e){
- e.printStackTrace();
- }
- return deployinfo_map;
- }
-
- //ajout C.D.
- public static String getDeployInfoRam(AvatarSpecification _avspec) {
- avspec =_avspec;
- int i=0;
- int j;
- String deployinfo_ram = CR;
- try{
- for(AvatarRelation ar: avspec.getRelations()){
- for (j=0; j<ar.nbOfSignals();j++){
- deployinfo_ram += "#if defined(DEPLOY_RAM" + i + "_NAME)" + CR;
- deployinfo_ram += "\tDEPLOY_RAM" + i + "_NAME (RWAL) : ORIGIN = DEPLOY_RAM" + i + "_ADDR, LENGTH = DEPLOY_RAM" + i + "_SIZE" + CR;
- deployinfo_ram += "#endif" +CR;
- deployinfo_ram += "#if defined(CACHED_RAM" + i + "_NAME)" + CR;
- deployinfo_ram += "\tCACHED_RAM" + i + "_NAME (RWAL) : ORIGIN = CACHED_RAM" + i + "_ADDR, LENGTH = CACHED_RAM" + i + "_SIZE" + CR;
- deployinfo_ram += "#endif" +CR;
- i++;
- }
- }
- }catch (Exception e){
- e.printStackTrace();
- }
- return deployinfo_ram;
- }
-
- //fin ajout C.D.
-
-
-
-public static String getProcInfo() {
- int i=0;
-
- String procinfo = "SOCLIB_CPU_COUNT = ";
-
- for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
- i++;
- }
-
- procinfo += i + CR;
- return procinfo;
- }
-
-
-public static String getNbProc() {
- int i=0;
-
- String nbproc = "CONFIG_CPU_MAXCOUNT ";
-
- for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
- i++;
- }
-
- nbproc += i + CR;
- return nbproc;
- }
-}
+
+ deployinfo_map = deployinfo_map +"\n .lock"+nb_signals+" : { \\" + CR;
+ deployinfo_map = deployinfo_map + "*(section_lock"+nb_signals+ ")\\"+ CR;
+ // if(use_vcilocks) deployinfo_map=deployinfo_map+ "} > vci_locks\\"+ CR;
+ deployinfo_map=deployinfo_map+ "} > uram0\\"+ CR;//DG 27.06. no ramlocks
+ i++; nb_signals++;
+ }
+
+ }
+ }
+ return deployinfo_map;
+ }*/
+
+ public static String getDeployInfoMap(AvatarSpecification _avspec) {
+ avspec = _avspec;
+ int i=0;
+ String deployinfo_map = CR;
+ int j;
+
+ deployinfo_map += "#define MAP_A\\" + CR;
+ try{
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ // if (/*!*/(ram.getChannels().isEmpty())){ //"!" removed because it returned the wrong results. Logic is now incorrect but results are correct (needs further investigating) CD 20.6
+ if (!(ram.getChannels().isEmpty())){
+ for(AvatarRelation ar: avspec.getRelations()){
+ for (j=0;j<ar.nbOfSignals();j++) {
+ deployinfo_map = deployinfo_map + "\n .channel"+i+" : {";
+ deployinfo_map = deployinfo_map + "*(section_channel"+i+ ")";
+ deployinfo_map = deployinfo_map + "} > uram" + ram.getIndex() + CR; //ram n° was incorrect (see above)
+ i++;
+ }
+ }
+
+ i=0;
+ for(AvatarRelation ar: avspec.getRelations()){
+ for (j=0;j<ar.nbOfSignals();j++) { //CD 15.06 dynamic to signal number
+ deployinfo_map = deployinfo_map + "\n .lock"+i+" : { " ;
+ deployinfo_map = deployinfo_map + "*(section_lock" + i + ")";
+ deployinfo_map = deployinfo_map + "} > uram" + ram.getIndex() + CR;
+ i++;
+ }
+ }
+ }
+ }
+ }catch (Exception e){
+ e.printStackTrace();
+ }
+ return deployinfo_map;
+ }
+
+ //ajout C.D.
+ public static String getDeployInfoRam(AvatarSpecification _avspec) {
+ avspec =_avspec;
+ int i=0;
+ int j;
+ String deployinfo_ram = CR;
+ try{
+ for(AvatarRelation ar: avspec.getRelations()){
+ for (j=0; j<ar.nbOfSignals();j++){
+ deployinfo_ram += "#if defined(DEPLOY_RAM" + i + "_NAME)" + CR;
+ deployinfo_ram += "\tDEPLOY_RAM" + i + "_NAME (RWAL) : ORIGIN = DEPLOY_RAM" + i + "_ADDR, LENGTH = DEPLOY_RAM" + i + "_SIZE" + CR;
+ deployinfo_ram += "#endif" +CR;
+ deployinfo_ram += "#if defined(CACHED_RAM" + i + "_NAME)" + CR;
+ deployinfo_ram += "\tCACHED_RAM" + i + "_NAME (RWAL) : ORIGIN = CACHED_RAM" + i + "_ADDR, LENGTH = CACHED_RAM" + i + "_SIZE" + CR;
+ deployinfo_ram += "#endif" +CR;
+ i++;
+ }
+ }
+ }catch (Exception e){
+ e.printStackTrace();
+ }
+ return deployinfo_ram;
+ }
+
+ //fin ajout C.D.
+
+
+
+public static String getProcInfo() {
+ int i=0;
+
+ String procinfo = "SOCLIB_CPU_COUNT = ";
+
+ for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
+ i++;
+ }
+
+ procinfo += i + CR;
+ return procinfo;
+ }
+
+
+public static String getNbProc() {
+ int i=0;
+
+ String nbproc = "CONFIG_CPU_MAXCOUNT ";
+
+ for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
+ i++;
+ }
+
+ nbproc += i + CR;
+ return nbproc;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Header.java b/src/main/java/ddtranslatorSoclib/toTopCell/Header.java
index c3d304aced44f67f2e32212aae80e0c4fa8513c1..8788b641f0849b7dbf6a06048741ba8e94ef40b0 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Header.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Header.java
@@ -211,6 +211,7 @@ public class Header
header + CR2 +
"static common::MappingTable maptab(32, IntTab(8,4), IntTab(8,4), 0xfff00000);";
}
+
return header;
}
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Loader.java b/src/main/java/ddtranslatorSoclib/toTopCell/Loader.java
index 59926939acb6fee476503e91e24d77bb00cb5a91..df2d8ded6b5f27eda7e92a589ec8dc9503a3a08f 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Loader.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Loader.java
@@ -139,6 +139,7 @@ if(nb_clusters==0){
}else{
loader = loader + " const size_t xicu_n_irq = "+(5*nb_clusters)+";" + CR2 ;
}
+
return loader;
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
index c78a6fd57654a2b142a0bad6959ba630af93b1e8..12b5447c072aa8393027f0e2e7916c51c25d1b8d 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
@@ -52,19 +52,47 @@ package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
import ddtranslatorSoclib.*;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarBlock;
+import avatartranslator.AvatarSignal;
+import avatartranslator.AvatarSpecification;
+//import ddtranslatorSoclib.AvatarCoproMWMR;
+import myutil.TraceManager;
public class MappingTable {
private final static String CR = "\n";
private final static String CR2 = "\n\n";
private static String mapping;
-
- public static String getMappingTable() {
- int l=0;
- int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- int nb_ram =TopCellGenerator.avatardd.getAllRAM().size();
+ public static AvatarddSpecification avatardd;
+
+ public static int rams_in_cluster(AvatarddSpecification dd,int cluster_no){
+ avatardd = dd;
+ int rams=0;
+ for (AvatarConnector connector : avatardd.getConnectors()){
+ AvatarConnectingPoint my_p1= connector.get_p1();
+ AvatarConnectingPoint my_p2= connector.get_p2();
+
+ AvatarComponent comp1 = my_p1.getComponent();
+ AvatarComponent comp2 = my_p2.getComponent();
+ if (comp1 instanceof AvatarRAM){
+ AvatarRAM comp1cpu = (AvatarRAM)comp1;
+ rams++;
+ }
+
+ }
+ TraceManager.addDev (cluster_no+" RAMs in this cluster " +rams);
+ return rams;
+ }
+
+ public static String getMappingTable(AvatarddSpecification dd) {
+
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
+ int nb_rams=TopCellGenerator.avatardd.getAllRAM().size();
+ avatardd = dd;
+
if(nb_clusters == 0){
mapping = CR2 + "//-----------------------mapping table------------------------" + CR2;
mapping = mapping + "// ppc segments" + CR2;
@@ -83,15 +111,15 @@ public class MappingTable {
Other targets :
the simhelper segment (target 3)
- the icu segment (target 4)
- the timer segment (target 5)
- the fdt segment (target 6)
-
- additional RAM segments (target 6+i)
- tty segments (target 6+i+j)
- fd access segment (target 6+i+j+1)
- ethernet segment (target 6+i+j+2)
- block device segment (target 6+i+j+3)
+ the icu segment (target 5)
+ the timer segment (target 4)
+ the dma segment (target 6)
+ the fdt segment (target 7)
+ additional RAM segments (target 7+i)
+ tty segments (target 7+i+j)
+ fd access segment (target 7+i+j+1)
+ ethernet segment (target 7+i+j+2)
+ block device segment (target 7+i+j+3)
*/
mapping += CR2 + "// RAM segments" + CR2;
@@ -102,7 +130,9 @@ public class MappingTable {
mapping = mapping + "maptab.add(Segment(\"simhelper\", 0xd3200000, 0x00000100, IntTab(3), false));" + CR;
mapping = mapping + " maptab.add(Segment(\"vci_xicu\", 0xd2200000, 0x00001000, IntTab(4), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_rttimer\", 0xd6000000, 0x00000100, IntTab(5), false));" + CR2;
- mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0xe0000000, 0x00001000, IntTab(6), false));" + CR2;
+ mapping = mapping + "maptab.add(Segment(\"vci_dma\", 0xf0000000, 0x00001000, IntTab(6), false));" + CR2;
+
+ mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0xe0000000, 0x00001000, IntTab(7), false));" + CR2;
int address_start = 268435456;
@@ -141,8 +171,8 @@ public class MappingTable {
i++;
}
else{
- ram.setNo_target(7+j);
-
+ // ram.setNo_target(7+j);
+ ram.setNo_target(8+j);//DG 9.7. ajoute DMA non-clustered
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*step)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), true));" + CR;
mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*step+ram.getDataSize()/2+cacheability_bit) + " , 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), false));" + CR;
j++;
@@ -151,27 +181,26 @@ public class MappingTable {
}
int m=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
- /* we calculate the target number of one or several (multi-) ttys which come after the j rams and the 7 compulsory targets */
- tty.setNo_target(7+j);
+ /* we calculate the target number of (multi-) ttys which come after the j rams and the 7 compulsory targets */
+ //tty.setNo_target(7+j);
+
+ tty.setNo_target(7+nb_rams);
/* we use a simple formula for calculating the TTY address in case of multiple (multi-) ttys */
/* attention this will not work for more than 10 TTYs */
mapping += "maptab.add(Segment(\"vci_multi_tty"+m+"\" , 0xd"+tty.getNo_tty()+"200000, 0x00000010, IntTab(" +tty.getNo_target() +"), false));" + CR;
-
- j++;
- m++;
- l=tty.getNo_target();
+
}
// }
- mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0xd4200000, 0x00000100, IntTab("+(l+1)+"), false));" + CR;
- mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0xd5000000, 0x00000020, IntTab("+(l+2)+"), false));" + CR;
- mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("+(l+3)+"), false));" + CR2;
+ mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0xd4200000, 0x00000100, IntTab("+(5)+"), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0xd5000000, 0x00000020, IntTab("+(6)+"), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("+(7)+"), false));" + CR2;
//mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0xC0200000, 0x00000100, IntTab("+(l+4)+"), false));" + CR2;
/* Instanciation of the MWMR wrappers for hardware accellerators */
/* The accelerators themselves are specifies on DIPLODOCUS level */
- int count = l+5;
+ int count = 7+nb_rams+1;
int hwa_count=0;
int nb_hwa=0;
int MWMR_SIZE=4096;
@@ -187,7 +216,7 @@ public class MappingTable {
hwa_count++;
count+=1;
}
- hwa_count=0;
+ hwa_count=0;
return mapping;
}
@@ -205,11 +234,10 @@ public class MappingTable {
mapping += "maptab.add(Segment(\"rodata\", 0x80000000, 0x01000000, IntTab(0,1), true));" + CR;
mapping += "maptab.add(Segment(\"data\", 0x7f000000, 0x01000000, IntTab(0,2), false)); " + CR2;
mapping = mapping + "maptab.add(Segment(\"simhelper\", 0x15200000, 0x00000100, IntTab(0,3), false));" + CR;
- mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0x16200000, 0x00001000, IntTab(0,4), false));" + CR2;
- mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0x17200000, 0x00000100, IntTab(0,5), false));" + CR;
- mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0x18200000, 0x00000020, IntTab(0,6), false));" + CR;
- mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0x19200000, 0x00000020, IntTab(0,7), false));" + CR2;
- // mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0x1A200000, 0x00000020, IntTab(0,8), false));" + CR2;
+ mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0x16200000, 0x00001000, IntTab(0,7), false));" + CR2;
+ mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0x17200000, 0x00000100, IntTab(0,8), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0x18200000, 0x00000020, IntTab(0,9), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0x19200000, 0x00000020, IntTab(0,10), false));" + CR2;
int SEG_ICU_BASE = 285212672;
int SEG_ICU_SIZE = 20;
@@ -237,29 +265,16 @@ public class MappingTable {
/* RAM adresses always start at 0x10000000 decimal 268435456*/
int SEG_RAM_BASE = 268435456;
- int cluster = 0;
-
-
- // mapping += "maptab.add(Segment(\"icu" + cluster + "\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,9), false));" + CR;
- mapping += "maptab.add(Segment(\"vci_xicu\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,9), false));" + CR;
- //mapping += "maptab.add(Segment(\"dma" + cluster + "\", 0x"+ Integer.toHexString(SEG_DMA_BASE)+", 0x"+ Integer.toHexString(SEG_DMA_SIZE)+", IntTab(0,10), false));" + CR;
-mapping += "maptab.add(Segment(\"dma\", 0x"+ Integer.toHexString(SEG_DMA_BASE)+", 0x"+ Integer.toHexString(SEG_DMA_SIZE)+", IntTab(0,10), false));" + CR;
- // mapping += "maptab.add(Segment(\"timer" + cluster + "\", 0x"+ Integer.toHexString(SEG_TIM_BASE)+", 0x"+ Integer.toHexString(SEG_TIM_SIZE)+", IntTab(0,11), true));" + CR;
+ int cluster = 0;
-mapping += "maptab.add(Segment(\"vci_rttimer\", 0x"+ Integer.toHexString(SEG_TIM_BASE)+", 0x"+ Integer.toHexString(SEG_TIM_SIZE)+", IntTab(0,11), true));" + CR;
-
-// all other clusters
-// for(cluster=1;cluster<nb_clusters; cluster++){
+ mapping += "maptab.add(Segment(\"vci_rttimer\", 0x"+ Integer.toHexString(SEG_TIM_BASE)+", 0x"+ Integer.toHexString(SEG_TIM_SIZE)+", IntTab(0,4), true));" + CR;
- // mapping += "maptab.add(Segment(\"icu" + cluster + "\", 0x"+ Integer.toHexString(SEG_ICU_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_ICU_SIZE)+", IntTab("+cluster +","+1+"), true));" + CR;
-
-// mapping += "maptab.add(Segment(\"dma" + cluster + "\", 0x"+ Integer.toHexString(SEG_DMA_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_DMA_SIZE)+", IntTab("+cluster +","+2+"), false));" + CR;
-
- // mapping += "maptab.add(Segment(\"timer" + cluster + "\", 0x"+ Integer.toHexString(SEG_TIM_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_TIM_SIZE)+", IntTab("+cluster +","+3+"), true));" + CR;
-
- // }
+ mapping += "maptab.add(Segment(\"vci_xicu\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,5), false));" + CR;
+ mapping += "maptab.add(Segment(\"dma\", 0x"+ Integer.toHexString(SEG_DMA_BASE)+", 0x"+ Integer.toHexString(SEG_DMA_SIZE)+", IntTab(0,6), false));" + CR;
- int cacheability_bit= 2097152; //0x00200000 T
+
+
+ int cacheability_bit= 2097152; //0x00200000
/* RAM base address is SEG_RAM_BASE + CLUSTER_NUMBER * CLUSTER_SIZE;
this is the memory space covered by the RAMs of a cluster */
@@ -277,19 +292,23 @@ mapping += "maptab.add(Segment(\"vci_rttimer\", 0x"+ Integer.toHexString(SEG_TIM
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
/* the number of fixed targets varies depending on if we are on cluster 0 or on other clusters */
- if(tty.getNo_cluster()==0){
- tty.setNo_target(10+nb_ram);
+ int tty_no;
+ int cluster_no=tty.getNo_cluster();
+ int cluster_rams=rams_in_cluster(avatardd,cluster_no);
+
+ if(tty.getNo_cluster()==0){
+ tty_no=6+cluster_rams;
}
- else{
- tty.setNo_target(tty.getNo_cluster()+nb_ram);
- }
- mapping += "maptab.add(Segment(\"vci_multi_tty"+tty.getIndex()+"\" , 0x"+Integer.toHexString(SEG_TTY_BASE + tty.getNo_cluster()* CLUSTER_SIZE)+", 0x00000010, IntTab("+tty.getNo_cluster()+","+(tty.getNo_target())+"), false));" + CR;
+ else{
+ tty_no=cluster_rams;
+ }
+
+ mapping += "maptab.add(Segment(\"vci_multi_tty"+tty.getIndex()+"\" , 0x"+Integer.toHexString(SEG_TTY_BASE + tty.getNo_cluster()* CLUSTER_SIZE)+", 0x00000010, IntTab("+tty.getNo_cluster()+","+tty_no+"), false));" + CR;
}
- /* Add as manin mwmr controllers as there are hardware accelerators */
- //int with_hw_accelerator = 0; //DG 23.08.
-
-// }
+ /* Add as many mwmr controllers as there are hardware accelerators */
+
}
+
return mapping;
}
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java-orig b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java-orig
new file mode 100755
index 0000000000000000000000000000000000000000..60e0d26704250b454d77b418b0f38c0a356f88f9
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java-orig
@@ -0,0 +1,294 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* this class produces the lines pertaining to the segment table. Except the segments containing CHANNEL channels and those corresponding to targets in shared memory, they need not be sepcified by the user of the deployment diagram */
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 - 2016 */
+
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+import ddtranslatorSoclib.*;
+
+public class MappingTable {
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private static String mapping;
+
+ public static String getMappingTable() {
+ int l=0;
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
+ int nb_ram =TopCellGenerator.avatardd.getAllRAM().size();
+
+
+ if(nb_clusters == 0){
+ mapping = CR2 + "//-----------------------mapping table------------------------" + CR2;
+ mapping = mapping + "// ppc segments" + CR2;
+
+ mapping = mapping + "maptab.add(Segment(\"resetppc\", 0xffffff80, 0x0080, IntTab(1), true));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"resetnios\", 0x00802000, 0x1000, IntTab(1), true));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"resetzero\", 0x00000000, 0x1000, IntTab(1), true));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"resetmips\", 0xbfc00000, 0x1000, IntTab(1), true));" + CR;
+
+ /*there are seven targets which are fixed; target 3 to 6 are transparent and do not appear in the TTool deployment diagram:
+
+ Targets on RAM0 :
+ the text segment (target 0)
+ the reset segment (target 1)
+ the data segment (target 2)
+
+ Other targets :
+ the simhelper segment (target 3)
+ the icu segment (target 4)
+ the timer segment (target 5)
+ the fdt segment (target 6)
+
+ additional RAM segments (target 6+i)
+ tty segments (target 6+i+j)
+ fd access segment (target 6+i+j+1)
+ ethernet segment (target 6+i+j+2)
+ block device segment (target 6+i+j+3)
+ */
+
+ mapping += CR2 + "// RAM segments" + CR2;
+ mapping += "maptab.add(Segment(\"text\", 0x60000000, 0x00100000, IntTab(0), true));" + CR;
+ mapping += "maptab.add(Segment(\"rodata\", 0x80000000, 0x01000000, IntTab(1), true));" + CR;
+ mapping += "maptab.add(Segment(\"data\", 0x7f000000, 0x01000000, IntTab(2), false)); " + CR2;
+
+ mapping = mapping + "maptab.add(Segment(\"simhelper\", 0xd3200000, 0x00000100, IntTab(3), false));" + CR;
+ mapping = mapping + " maptab.add(Segment(\"vci_xicu\", 0xd2200000, 0x00001000, IntTab(4), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_rttimer\", 0xd6000000, 0x00000100, IntTab(5), false));" + CR2;
+ mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0xe0000000, 0x00001000, IntTab(6), false));" + CR2;
+
+
+ int address_start = 268435456;
+ int j=0; int i=0;
+ int size;
+ //if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ // if no data size is given calculate default data size
+ if(ram.getDataSize()==0){
+
+ if((nb_clusters<16)||(TopCellGenerator.avatardd.getAllRAM().size()<16)){
+ size = 1073741824;
+ }
+ else {//dimension segments to be smaller
+ size = 268435456;
+ }
+ }
+ else{
+ size = ram.getDataSize();
+ }
+ ram.setDataSize(size);
+
+ size = ram.getDataSize(); // this is the hardware RAM size
+
+ int step = 268435456;// DG 11.10. attention cacheability bit, cannot take any size given in DD, must be checked, toDo
+
+ int cacheability_bit= 2097152; //0x00200000
+
+ /* Boot Ram segments 0,1,2 */
+ if(ram.getNo_ram() ==0){
+ ram.setNo_target(2);//in the following assign target number 2
+
+ mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +Integer.toHexString(address_start+i*step)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*step+cacheability_bit+ram.getDataSize()/2)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), false));" + CR;
+ i++;
+ }
+ else{
+ ram.setNo_target(7+j);
+
+ mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*step)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*step+ram.getDataSize()/2+cacheability_bit) + " , 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), false));" + CR;
+ j++;
+ i++;
+ }
+ }
+ int m=0;
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
+ /* we calculate the target number of one or several (multi-) ttys which come after the j rams and the 7 compulsory targets */
+ tty.setNo_target(7+j);
+ /* we use a simple formula for calculating the TTY address in case of multiple (multi-) ttys */
+
+ /* attention this will not work for more than 10 TTYs */
+ mapping += "maptab.add(Segment(\"vci_multi_tty"+m+"\" , 0xd"+tty.getNo_tty()+"200000, 0x00000010, IntTab(" +tty.getNo_target() +"), false));" + CR;
+
+ j++;
+ m++;
+ l=tty.getNo_target();
+ }
+ // }
+ mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0xd4200000, 0x00000100, IntTab("+(l+1)+"), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0xd5000000, 0x00000020, IntTab("+(l+2)+"), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("+(l+3)+"), false));" + CR2;
+ //mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0xC0200000, 0x00000100, IntTab("+(l+4)+"), false));" + CR2;
+
+
+ /* Instanciation of the MWMR wrappers for hardware accellerators */
+ /* The accelerators themselves are specifies on DIPLODOCUS level */
+ int count = l+5;
+ int hwa_count=0;
+ int nb_hwa=0;
+ int MWMR_SIZE=4096;
+ int MWMRd_SIZE=12288;
+ // int MWMR_BASE=0xA0200000;
+ i=0;
+ for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {nb_hwa++;
+ }
+
+ for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ mapping += "maptab.add(Segment(\"mwmr_ram"+hwa_count+"\", 0xA0"+ Integer.toHexString(2097152+MWMR_SIZE*i)+", 0x00001000, IntTab("+count+"), false));" + CR;
+ mapping += "maptab.add(Segment(\"mwmrd_ram"+hwa_count+"\", 0x20"+ Integer.toHexString(2097152+MWMRd_SIZE*i)+", 0x00003000, IntTab("+(count+nb_hwa)+"), false));" + CR;
+ hwa_count++;
+ count+=1;
+ }
+ hwa_count=0;
+
+ return mapping;
+ }
+
+ else{
+ /* clustered version */
+
+ mapping = CR2 + "maptab.add(Segment(\"resetppc\", 0xffffff80, 0x0080, IntTab(0,1), true));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"resetnios\", 0x00802000, 0x1000, IntTab(0,1), true));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"resetzero\", 0x00000000, 0x1000, IntTab(0,1), true));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"resetmips\", 0xbfc00000, 0x1000, IntTab(0,1), true));" + CR;
+
+ mapping += CR2 + "// RAM shared segments on cluster 0" + CR2;
+ mapping += "maptab.add(Segment(\"text\", 0x60000000, 0x00100000, IntTab(0,0), true));" + CR;
+ mapping += "maptab.add(Segment(\"rodata\", 0x80000000, 0x01000000, IntTab(0,1), true));" + CR;
+ mapping += "maptab.add(Segment(\"data\", 0x7f000000, 0x01000000, IntTab(0,2), false)); " + CR2;
+ mapping = mapping + "maptab.add(Segment(\"simhelper\", 0x15200000, 0x00000100, IntTab(0,3), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0x16200000, 0x00001000, IntTab(0,4), false));" + CR2;
+ mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0x17200000, 0x00000100, IntTab(0,5), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0x18200000, 0x00000020, IntTab(0,6), false));" + CR;
+ mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0x19200000, 0x00000020, IntTab(0,7), false));" + CR2;
+ // mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0x1A200000, 0x00000020, IntTab(0,8), false));" + CR2;
+
+ int SEG_ICU_BASE = 285212672;
+ int SEG_ICU_SIZE = 20;
+
+ int NB_DMAS = 1;
+ int SEG_DMA_BASE = 304087040;
+ int SEG_DMA_SIZE = (NB_DMAS * 20);
+
+ int NB_TIMERS = 1;
+ int SEG_TIM_BASE = 318767104;
+ int SEG_TIM_SIZE = (NB_TIMERS * 16 );
+
+ int SEG_TTY_BASE = 337641472;
+ int SEG_TTY_SIZE = 16;
+
+ int CLUSTER_SIZE;
+
+ //if the user does not specify the size, take default value
+ if(nb_clusters<16) {
+ CLUSTER_SIZE = 268435456;}
+ else {
+ CLUSTER_SIZE = 134217728;
+ }// to be refined, cf DSX -> dynamically adapt
+
+ /* RAM adresses always start at 0x10000000 decimal 268435456*/
+
+ int SEG_RAM_BASE = 268435456;
+ int cluster = 0;
+
+
+ // mapping += "maptab.add(Segment(\"icu" + cluster + "\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,9), false));" + CR;
+ mapping += "maptab.add(Segment(\"vci_xicu\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,9), false));" + CR;
+ //mapping += "maptab.add(Segment(\"dma" + cluster + "\", 0x"+ Integer.toHexString(SEG_DMA_BASE)+", 0x"+ Integer.toHexString(SEG_DMA_SIZE)+", IntTab(0,10), false));" + CR;
+mapping += "maptab.add(Segment(\"dma\", 0x"+ Integer.toHexString(SEG_DMA_BASE)+", 0x"+ Integer.toHexString(SEG_DMA_SIZE)+", IntTab(0,10), false));" + CR;
+ // mapping += "maptab.add(Segment(\"timer" + cluster + "\", 0x"+ Integer.toHexString(SEG_TIM_BASE)+", 0x"+ Integer.toHexString(SEG_TIM_SIZE)+", IntTab(0,11), true));" + CR;
+
+mapping += "maptab.add(Segment(\"vci_rttimer\", 0x"+ Integer.toHexString(SEG_TIM_BASE)+", 0x"+ Integer.toHexString(SEG_TIM_SIZE)+", IntTab(0,11), true));" + CR;
+
+// all other clusters
+// for(cluster=1;cluster<nb_clusters; cluster++){
+
+ // mapping += "maptab.add(Segment(\"icu" + cluster + "\", 0x"+ Integer.toHexString(SEG_ICU_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_ICU_SIZE)+", IntTab("+cluster +","+1+"), true));" + CR;
+
+// mapping += "maptab.add(Segment(\"dma" + cluster + "\", 0x"+ Integer.toHexString(SEG_DMA_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_DMA_SIZE)+", IntTab("+cluster +","+2+"), false));" + CR;
+
+ // mapping += "maptab.add(Segment(\"timer" + cluster + "\", 0x"+ Integer.toHexString(SEG_TIM_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_TIM_SIZE)+", IntTab("+cluster +","+3+"), true));" + CR;
+
+ // }
+
+ int cacheability_bit= 2097152; //0x00200000 T
+
+ /* RAM base address is SEG_RAM_BASE + CLUSTER_NUMBER * CLUSTER_SIZE;
+ this is the memory space covered by the RAMs of a cluster */
+
+ //we want to identify the RAMS on this cluster (not RAMs in total)
+
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x"+Integer.toHexString(SEG_RAM_BASE+ ram.getNo_cluster()*CLUSTER_SIZE)+", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), true));" + CR;
+
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x"+Integer.toHexString(SEG_RAM_BASE + ram.getNo_cluster()*CLUSTER_SIZE+cacheability_bit)+", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), false));" + CR;
+ }
+
+ //we want to identify the TTYS on this cluster (not TTYs in total)
+ //currently one tty per cluster
+
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
+ /* the number of fixed targets varies depending on if we are on cluster 0 or on other clusters */
+ if(tty.getNo_cluster()==0){
+ tty.setNo_target(10+nb_ram);
+ }
+ else{
+ tty.setNo_target(tty.getNo_cluster()+nb_ram);
+ }
+ mapping += "maptab.add(Segment(\"vci_multi_tty"+tty.getIndex()+"\" , 0x"+Integer.toHexString(SEG_TTY_BASE + tty.getNo_cluster()* CLUSTER_SIZE)+", 0x00000010, IntTab("+tty.getNo_cluster()+","+(tty.getNo_target())+"), false));" + CR;
+ }
+ /* Add as many mwmr controllers as there are hardware accelerators */
+
+ }
+
+ return mapping;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
index 5c2b98e11913c8f413b904ac5e2e307277eaa8a9..926532713ea989ac6eeb2e495d890eb61c2ad831 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
@@ -39,141 +39,222 @@
*/
-
-
/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarSpecification;
+import ddtranslatorSoclib.*;
import ddtranslatorSoclib.AvatarCPU;
import ddtranslatorSoclib.AvatarCoproMWMR;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
+import ddtranslatorSoclib.AvatarCrossbar;
+
public class NetList
{
+ public static AvatarddSpecification avatardd;
public static final String NAME_CLK = "signal_clk";
public static final String CR = "\n";
public static final String CR2 = "\n\n";
private static final String NAME_RST = "signal_resetn";
private static boolean tracing;
- public static String getNetlist (String icn, boolean _tracing)
+
+ public static int cpus_in_cluster(AvatarddSpecification dd,int cluster_no){
+ int cpus=0;
+ avatardd = dd;
+ for (AvatarConnector connector : avatardd.getConnectors()){
+ AvatarConnectingPoint my_p1= connector.get_p1();
+ AvatarConnectingPoint my_p2= connector.get_p2();
+
+ AvatarComponent comp1 = my_p1.getComponent();
+ AvatarComponent comp2 = my_p2.getComponent();
+ if (comp1 instanceof AvatarCPU){
+ AvatarCPU comp1cpu = (AvatarCPU)comp1;
+ cpus++;
+ }
+ }
+ return cpus;
+ }
+
+
+ public static String getNetlist (AvatarddSpecification dd,String icn, boolean _tracing)
{
- int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar().size ();
int coproc_count = 0;
-
- tracing = _tracing;
+ avatardd = dd;
+ tracing = _tracing;
String netlist;
- netlist =
+ netlist =
CR2 +
"//------------------------------Netlist---------------------------------"
+ CR2;
- netlist = netlist + "// icu" + CR2;
- netlist =
+ netlist = netlist + "// icu" + CR2;
+ netlist =
netlist +
" vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));"
+ CR2;
- netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
- netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
+ netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
+ netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
- netlist =
+ netlist =
netlist +
" vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");"
+ CR;
- netlist =
+ netlist =
netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
- netlist =
+ netlist =
netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
- netlist =
+ netlist =
netlist +
" vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");"
+ CR2;
- netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
- netlist =
+ netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
+ netlist =
netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
- netlist = netlist + " {" + CR;
- netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
- netlist =
+ netlist = netlist + " {" + CR;
+ netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
+ netlist =
netlist +
" irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
- netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
- netlist = netlist + " }" + CR2;
- netlist =
+ netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
+ netlist = netlist + " }" + CR2;
+ netlist =
netlist +
" vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);"
+ CR;
- netlist =
+ netlist =
netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
CR2;
- netlist =
+ netlist =
netlist +
" vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
- netlist =
+ netlist =
netlist +
" vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" +
CR;
- netlist =
+ netlist =
netlist +
" vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());"
+ CR;
- netlist =
+ netlist =
netlist +
" vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());"
+ CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
- netlist =
+ netlist =
netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
- netlist =
+ netlist =
netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
- netlist = netlist + "///////////////// cpus" + CR2;
+ netlist = netlist + "///////////////// cpus" + CR2;
- netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
- netlist =
+ netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
+ netlist =
netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
- netlist = netlist + " // configure het_rom" + CR;
- netlist =
- netlist +
- " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
-
- netlist = netlist + " // add cpu node to device tree" + CR;
- netlist =
- netlist +
- " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
- + CR;
- netlist =
- netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + "// connect cpu" + CR;
- netlist =
- netlist +
- " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);"
- + CR;
- if (icn == "vgmn")
- {
- netlist =
- netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
- }
- else
- {
- netlist =
- netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
- }
-
+ netlist = netlist + " // configure het_rom" + CR;
+
+ int i=0;
+ if(nb_clusters==0){
+ netlist =
+ netlist +
+ " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
+
+ netlist = netlist + " // add cpu node to device tree" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+ netlist =netlist + " }"+ CR;
+
+ }
+ else{
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar ()){
+
+ netlist =netlist + "for ( size_t j = 0; j < " +cpus_in_cluster(avatardd,i)+"; ++j ){" + CR;
+ netlist = netlist +
+ " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab("+crossbar.getClusterIndex() +",j));" + CR;
+ netlist = netlist + " // add cpu node to device tree" + CR;
+
+ netlist = netlist +
+ " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+
+ netlist =netlist + " }"+ CR;
+
+ netlist =netlist + "crossbar"+crossbar.getClusterIndex()+".p_initiator_to_up(signal_down"+crossbar.getClusterIndex()+");"+ CR;
+ netlist =netlist + "crossbar"+crossbar.getClusterIndex()+".p_target_to_up(signal_up"+crossbar.getClusterIndex()+");"+ CR;
+ if (icn == "vgmn"){
+ netlist =netlist + "vgmn.p_to_initiator["+0+"](signal_down"+crossbar.getClusterIndex()+");"+ CR;
+ netlist =netlist + "vgmn.p_to_target["+0+"](signal_up"+crossbar.getClusterIndex()+");"+ CR;
+ }
+ else{
+ netlist =netlist + "vgsb.p_to_initiator["+0+"](signal_down"+crossbar.getClusterIndex()+");"+ CR;
+ netlist =netlist + "vgsb.p_to_target["+0+"](signal_up"+crossbar.getClusterIndex()+");"+ CR;
+ }
+ netlist =netlist + "for ( size_t j = 0; j < " + cpus_in_cluster(avatardd,i) +"; ++j ){" + CR;
+ netlist =
+ netlist +
+ " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m"+crossbar.getClusterIndex()+"[j]);"+ CR;
+ netlist =
+ netlist +"}" + CR;
+ netlist = netlist + "// connected cluster" + +crossbar.getClusterIndex()+"."+CR2;
+ i++;
+ }
+ }
+
+ if(nb_clusters==0){
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ }
+ else{
+ int j;
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar ()){
+ i=0;
+ for (j=0;j< cpus_in_cluster(avatardd,i) ;j++){
+ netlist =
+ netlist = netlist + "for ( size_t j = 0; j < " + cpus_in_cluster(avatardd,i) +"; ++j ){" + CR;
+ netlist = netlist + "crossbar"+crossbar.getClusterIndex()+".p_to_initiator[i](signal_vci_m"+crossbar.getClusterIndex()+"[j]);" + CR;
+ netlist = netlist + "}"+CR;
+ i++;
+ }
+ }
+ }
+
+
netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
netlist = netlist + " }" + CR;
netlist = netlist + " vcifdtrom.end_node();" + CR2;
@@ -198,297 +279,321 @@ public class NetList
netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
netlist =
netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
-
- if (icn == "vgmn")
- {
- netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
- netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" +
- CR;
- netlist =
- netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
- netlist =
- netlist +
- " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
- netlist =
- netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
- netlist =
- netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" +
- CR2;
- netlist =
- netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" +
- CR2;
- netlist =
- netlist +
- " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
- netlist =
- netlist +
- " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
- + CR;
- netlist =
- netlist +
- " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
- + CR2;
- }
- else
- {
- netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
- netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" +
- CR;
- netlist =
- netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
- netlist =
- netlist +
- " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
- netlist =
- netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
- netlist =
- netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" +
- CR2;
- netlist =
- netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" +
- CR2;
- netlist =
- netlist +
- " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
- netlist =
- netlist +
- " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
- + CR;
- netlist =
- netlist +
- " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
- + CR2;
- }
-
- if (nb_clusters == 0)
- {
- netlist = netlist + "// RAM netlist" + CR2;
- for (AvatarRAM ram:TopCellGenerator.avatardd.
- getAllRAM ())
+
+ if(nb_clusters==0){
+ if (icn == "vgmn")
{
-
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
netlist =
- netlist + ram.getMemoryName () + ".p_clk(" +
- NAME_CLK + ");" + CR;
+ netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
netlist =
- netlist + ram.getMemoryName () + ".p_resetn(" +
- NAME_RST + ");" + CR;
+ netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
netlist =
- netlist + ram.getMemoryName () +
- ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
- CR2;
- if (icn == "vgmn")
- {
- netlist =
- netlist + "vgmn.p_to_target[" +
- (ram.getNo_target ()) + "](signal_vci_vciram" +
- ram.getIndex () + ");" + CR2;
- }
- else
- {
- netlist =
- netlist + "vgsb.p_to_target[" +
- (ram.getNo_target ()) + "](signal_vci_vciram" +
- ram.getIndex () + ");" + CR2;
- }
- }
- }
-
- /* clustered version */
- /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster */
- else
- {
- int i;
- netlist = netlist + "// RAM netlist" + CR2;
- for (AvatarRAM ram:TopCellGenerator.avatardd.
- getAllRAM ())
- {
-
+ netlist +
+ " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
netlist =
- netlist + ram.getMemoryName () + ".p_clk(" +
- NAME_CLK + ");" + CR;
+ netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
netlist =
- netlist + ram.getMemoryName () + ".p_resetn(" +
- NAME_RST + ");" + CR;
+ netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
netlist =
- netlist + ram.getMemoryName () +
- ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" +
CR2;
- //target number for local cluster: this is set at avatardd creation
netlist =
- netlist + "crossbar" + ram.getNo_cluster () +
- ".p_to_target[" + ram.getNo_target () +
- "](signal_vci_vciram" + ram.getIndex () + ");" + CR2;
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
}
-
- /*convention for local target ids on cluster :
- channel: 0
- mwmr_ram: 1
- mwmrd_ram: 2
- locks: 3
- ram: 4
- tty: 5
- */
-
- }
-
- if (nb_clusters == 0)
- {
-
- int l = 8; //number of last tty
- if (icn == "vgmn")
+ else
{
+ netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
netlist =
- netlist + "vgmn.p_to_target[" + (l) +
- "](signal_vci_vcifdaccesst);" + CR;
+ netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
netlist =
- netlist + "vgmn.p_to_target[" + (l + 1) +
- "](signal_vci_ethernett);" + CR;
+ netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
netlist =
- netlist + "vgmn.p_to_target[" + (l + 2) +
- "](signal_vci_bdt);" + CR;
-
- int i;
-
- for (i = 0; i < coproc_count; i++)
- {
-
- netlist =
- netlist + "vgmn.p_to_target[" + (l + 4 + i) +
- "](signal_mwmr_" + i + "_target);" + CR;
- }
- }
- else
- { //vgsb
+ netlist +
+ " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
netlist =
- netlist + "vgsb.p_to_target[" + (l) +
- "](signal_vci_vcifdaccesst);" + CR;
+ netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
netlist =
- netlist + "vgsb.p_to_target[" + (l + 1) +
- "](signal_vci_ethernett);" + CR;
+ netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
netlist =
- netlist + "vgsb.p_to_target[" + (l + 2) +
- "](signal_vci_bdt);" + CR;
-
- int i;
- for (i = 0; i < coproc_count; i++)
- {
- netlist =
- netlist + "vgmn.p_to_target[" + (l + 4 + i) +
- "](signal_mwmr_" + i + "_target);" + CR;
- }
- }
-
- }
- else
- {
- /* cluster */
- if (icn == "vgmn")
- {
+ netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
netlist =
- netlist + "vgmn.p_to_target[" + 5 +
- "](signal_vci_vcifdaccesst);" + CR;
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
netlist =
- netlist + "vgmn.p_to_target[" + 6 +
- "](signal_vci_ethernett);" + CR;
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
netlist =
- netlist + "vgmn.p_to_target[" + 7 +
- "](signal_vci_bdt);" + CR;
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+ }
+ else{//clustered
+ if (icn == "vgmn")
+ {
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
}
- else
+ else{
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ }
+ //in any case for clustered, initiators and targets are attached to crossbar
+
+ if (nb_clusters == 0){
+ netlist = netlist + " crossbar.p_clk(signal_clk);" + CR;
+ netlist = netlist + " crossbar.p_resetn(signal_resetn);" + CR;
+ }
+ else{
+ for ( i = 0; i < nb_clusters; ++i ){
+ netlist = netlist + " crossbar"+i+".p_clk(signal_clk);" + CR;
+ netlist = netlist + " crossbar"+i+".p_resetn(signal_resetn);" + CR;
+ }
+ }
+ }
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar ()){
+ i=0;
+ netlist = netlist + "crossbar"+crossbar.getClusterIndex()+".p_to_initiator["+crossbar.getClusterIndex()+"](signal_vci_m"+crossbar.getClusterIndex()+"["+ cpus_in_cluster(avatardd,i) +"]);" + CR;
+ }
+
+
+ if (nb_clusters == 0){
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
{
+
netlist =
- netlist + "vgsb.p_to_target[" + 5 +
- "](signal_vci_vcifdaccesst);" + CR;
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
netlist =
- netlist + "vgsb.p_to_target[" + 6 +
- "](signal_vci_ethernett);" + CR;
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
netlist =
- netlist + "vgsb.p_to_target[" + 7 +
- "](signal_vci_bdt);" + CR;
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
}
- }
+ }
+
+ /* clustered version */
+ /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster */
+ else
+ {
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ //target number for local cluster: this is set at avatardd creation
+ netlist =
+ netlist + "crossbar" + ram.getNo_cluster () +
+ ".p_to_target[" + ram.getNo_target () +
+ "](signal_vci_vciram" + ram.getIndex () + ");" + CR2;
+ }
+
+ /*convention for local target ids on cluster :
+ channel: 0
+ mwmr_ram: 1
+ mwmrd_ram: 2
+ locks: 3
+ ram: 4
+ tty: 5
+ */
+
+ }
+
+ if (nb_clusters == 0)
+ {
+
+ int l = 8; //number of last tty
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ for (i = 0; i < coproc_count; i++)
+ {
+
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+ else
+ { //vgsb
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ for (i = 0; i < coproc_count; i++)
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+
+ }
+ else
+ {
+ /* cluster */
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ }
netlist =
netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
netlist = netlist + "vcifdtrom.end_node();;" + CR2;
netlist = netlist + "// TTY netlist" + CR2;
- int i = 0;
-
- for (AvatarTTY tty:TopCellGenerator.avatardd.getAllTTY ())
- {
- netlist =
- netlist + tty.getTTYName () + ".p_clk(signal_clk);" + CR;
- netlist =
- netlist + tty.getTTYName () + ".p_resetn(signal_resetn);" +
- CR;
- netlist =
- netlist + tty.getTTYName () + ".p_vci(signal_vci_tty" + i +
- ");" + CR2;
- int no_irq_tty = 0;
- if (nb_clusters == 0)
- {
-
- if (icn == "vgmn")
- {
- netlist =
- netlist +
- "vcifdtrom.begin_device_node(\"vci_multi_tty" +
- i + "\",\"soclib:vci_multi_tty" + i + "\");" +
- CR2;
- netlist =
- netlist + "vgmn.p_to_target[" +
- tty.getNo_target () + "](signal_vci_tty" + i +
- ");" + CR2;
- netlist =
- netlist + tty.getTTYName () +
- ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
- "]);" + CR2;
- }
- else
- {
- netlist =
- netlist +
- "vcifdtrom.begin_device_node(\"vci_multi_tty" +
- i + "\",\"soclib:vci_multi_tty" +
- tty.getNo_tty () + "\");" + CR2;
- netlist =
- netlist + "vgsb.p_to_target[" +
- tty.getNo_target () + "](signal_vci_tty" + i +
- ");" + CR2;
- netlist =
- netlist + tty.getTTYName () +
- ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
- "]);" + CR2;
- }
- }
-
- //we have a clustered architecture: identify local crossbar
- else
- {
- int j;
- for (j = 0; j < nb_clusters; j++)
- {
- netlist =
- netlist + "crossbar" + j + ".p_to_target[" +
- tty.getNo_target () + "](signal_vci_tty" + j +
- ");" + CR2;
- //recalculate irq addresses, 5 devices generating irq per cluster
- netlist =
- netlist + tty.getTTYName () +
- ".p_irq[0](signal_xicu_irq[" +
- (tty.getNo_cluster () * 5) + "]);" + CR2;
- }
- }
- i++;
- //One ICU per cluster per default
- no_irq_tty += 6; //if there is more than one tty, irq >5
- }
+ i=0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.getAllTTY ())
+ {
+ netlist =
+ netlist + tty.getTTYName () + ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_vci(signal_vci_tty" + i +
+ ");" + CR2;
+ int no_irq_tty = 0;
+ if (nb_clusters == 0)
+ {
+
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" + i + "\");" +
+ CR2;
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" +
+ tty.getNo_tty () + "\");" + CR2;
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ }
+
+ //we have a clustered architecture: identify local crossbar
+ else
+ {
+ int j;
+ for (j = 0; j < nb_clusters; j++)
+ {
+ netlist =
+ netlist + "crossbar" + j + ".p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + j +
+ ");" + CR2;
+ //recalculate irq addresses, 5 devices generating irq per cluster
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" +
+ (tty.getNo_cluster () * 5) + "]);" + CR2;
+ }
+ }
+ i++;
+ //One ICU per cluster per default
+ no_irq_tty += 6; //if there is more than one tty, irq >5
+ }
//////////////// fdrom
@@ -557,224 +662,218 @@ public class NetList
i = 0;
int j = 0;
- for (AvatarCoproMWMR copro:TopCellGenerator.
- avatardd.getAllCoproMWMR ())
- {
-
- //IE and OE are special cases as they have VCI an fifo initiator interface
-
- if (copro.getCoprocType () == 0)
- {
- i = 0;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_clk(signal_clk);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_vci(signal_vci_IE);" + CR;
-
- netlist =
- netlist + copro.getCoprocName () +
- ".p_pktdesc[0](signal_fifo_" + j + "_" + i +
- "_to_ctrl);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_slin(signal_fifo_" + j + "_" + i +
- "_from_ctrl);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
- "_from_ctrl);" + CR;
-
- netlist =
- netlist + copro.getCoprocName () +
- ".p_running(signal_IE_from_ctrl);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_status(signal_IE_to_ctrl);" + CR2;
- i = 0;
- }
- else if (copro.getCoprocType () == 1)
- {
- netlist =
- netlist + copro.getCoprocName () +
- ".p_clk(signal_clk);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_vci(signal_vci_OE);" + CR;
-
- netlist =
- netlist + copro.getCoprocName () +
- ".p_desc(signal_fifo_" + j + "_" + i +
- "_from_ctrl);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_slin(signal_fifo_" + j + "_" + i + "_to_ctrl);" +
- CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
- "_to_ctrl);" + CR;
-
- netlist =
- netlist + copro.getCoprocName () +
- ".p_running(signal_OE_from_ctrl);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_status(signal_OE_to_ctrl);" + CR2;
- i = 0;
- }
- else
- {
- netlist =
- netlist + copro.getCoprocName () +
- ".p_clk(signal_clk);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- ".p_resetn(signal_resetn);" + CR;
- netlist =
- // netlist + "hwa" + i + ".p_from_ctrl[" + i +
- // "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
- netlist + copro.getCoprocName ()+ ".p_from_ctrl[" + i +
- "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
- netlist =
- // netlist + "hwa" + i + ".p_to_ctrl[" + i +
- // "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
- netlist + copro.getCoprocName () + ".p_to_ctrl[" + i +
- "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
- }
-
-
- //additional interfaces for IE and OE
-
- if (copro.getCoprocType () == 0)
- {
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_clk(signal_clk);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_vci_initiator(signal_mwmr_" + i +
- "_initiator);" + CR;
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //pktdesc
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_from_ctrl);" + CR; //running
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_IE_to_ctrl);" + CR; //status
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //slin
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_IE_from_ctrl);" + CR; //slext
- }
- else
- {
- if (copro.getCoprocType () == 1)
- {
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_clk(signal_clk);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_vci_initiator(signal_mwmr_" + i +
- "_initiator);" + CR;
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //desc
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_OE_to_ctrl);" + CR; //running
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //status
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_to_ctrl);" + CR; //slin
- netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_OE_from_ctrl);" + CR; //slext
- }
- else
- {
-
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_clk(signal_clk);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_resetn(signal_resetn);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_vci_initiator(signal_mwmr_" + i +
- "_initiator);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_vci_target(signal_mwmr_" + i +
- "_target);" + CR2;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_from_coproc[" + i +
- "](signal_fifo_" + j + "_" + i +
- "_from_ctrl);" + CR;
- netlist =
- netlist + copro.getCoprocName () +
- "_wrapper.p_to_coproc[" + i + "](signal_fifo_" +
- j + "_" + i + "_to_ctrl);" + CR;
- }
- i++;
- }
- j++;
- coproc_count++;
- }
-
-
+ for (AvatarCoproMWMR copro:TopCellGenerator.
+ avatardd.getAllCoproMWMR ())
+ {
+ //IE and OE packet engines are special cases as they have VCI an fifo initiator interface
+ if (copro.getCoprocType () == 0)
+ {
+ i = 0;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_IE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_pktdesc[0](signal_fifo_" + j + "_" + i +
+ "_to_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_from_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_IE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_IE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_OE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_desc(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i + "_to_ctrl);" +
+ CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_to_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_OE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_OE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName ()+ ".p_from_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () + ".p_to_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
+ }
+
+
+ //additional interfaces for IE and OE
+
+ if (copro.getCoprocType () == 0)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //pktdesc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_from_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_IE_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_IE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //desc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_OE_to_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_OE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_target(signal_mwmr_" + i +
+ "_target);" + CR2;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_from_coproc[" + i +
+ "](signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_to_coproc[" + i + "](signal_fifo_" +
+ j + "_" + i + "_to_ctrl);" + CR;
+ }
+ i++;
+ }
+ j++;
+ coproc_count++;
+ }
+
+
//If there is a spy, add logger or stats to vci interface
i = 0;
- for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
- {
- int number = cpu.getNo_proc ();
- if (cpu.getMonitored () == 1)
- {
- netlist = netlist + CR +
- "logger" + i + ".p_clk(signal_clk);" + CR +
- "logger" + i + ".p_resetn(signal_resetn);" + CR +
- "logger" + i + ".p_vci(signal_vci_m[" + number +
- "]);" + CR2;
- i++;
- }
-
- }
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+ int number = cpu.getNo_proc ();
+ if (cpu.getMonitored () == 1)
+ {
+ netlist = netlist + CR +
+ "logger" + i + ".p_clk(signal_clk);" + CR +
+ "logger" + i + ".p_resetn(signal_resetn);" + CR +
+ "logger" + i + ".p_vci(signal_vci_m[" + number +
+ "]);" + CR2;
+ i++;
+ }
+
+ }
j = 0;
- for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
- {
- if (ram.getMonitored () == 1)
- {
- int number = number = ram.getIndex ();
- netlist += "logger" + i + ".p_clk(signal_clk);" + CR;
- netlist +=
- "logger" + i + ".p_resetn(signal_resetn);" + CR;
- netlist +=
- "logger" + i + ".p_vci(signal_vci_vciram" + number +
- ");" + CR2;
- i++;
- }
- else
- {
-
- if (ram.getMonitored () == 2)
- {
- int number = number = ram.getIndex ();
- netlist +=
- "mwmr_stats" + j + ".p_clk(signal_clk);" + CR;
- netlist +=
- "mwmr_stats" + j + ".p_resetn(signal_resetn);" +
- CR;
- netlist +=
- "mwmr_stats" + j + ".p_vci(signal_vci_vciram" +
- number + ");" + CR2;
- j++;
- }
- }
- }
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 1)
+ {
+ int number = number = ram.getIndex ();
+ netlist += "logger" + i + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "logger" + i + ".p_resetn(signal_resetn);" + CR;
+ netlist +=
+ "logger" + i + ".p_vci(signal_vci_vciram" + number +
+ ");" + CR2;
+ i++;
+ }
+ else
+ {
+
+ if (ram.getMonitored () == 2)
+ {
+ int number = number = ram.getIndex ();
+ netlist +=
+ "mwmr_stats" + j + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_vci(signal_vci_vciram" +
+ number + ");" + CR2;
+ j++;
+ }
+ }
+ }
int p = 0;
@@ -782,89 +881,88 @@ public class NetList
//generate trace file if marked trace option
if (tracing)
- {
- netlist += "sc_trace_file *tf;" + CR;
- netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
- netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
- netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
-
- netlist +=
- "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
- netlist +=
- "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");"
- + CR;
- netlist +=
- "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");"
- + CR;
- netlist +=
- "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" +
- CR;
- netlist +=
- "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");"
- + CR;
- netlist +=
- "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");"
- + CR;
- netlist +=
- "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");"
- + CR;
- netlist +=
- "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");"
- + CR;
- netlist +=
- "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
- netlist +=
- "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
- netlist +=
- "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");"
- + CR;
- netlist +=
- "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");"
- + CR;
-
- for (i = 0; i < TopCellGenerator.avatardd.getNb_init (); i++)
- {
- netlist +=
- "sc_trace(tf,signal_vci_m[" + i +
- "] ,\"signal_vci_m[" + i + "]\");" + CR;
- }
-
- i = 0;
- for (AvatarTTY tty:TopCellGenerator.avatardd.
- getAllTTY ())
- {
-
- netlist +=
- "sc_trace(tf,signal_vci_tty" + tty.getNo_tty () +
- ",\"TTY" + tty.getNo_tty () + "\");" + CR;
- netlist +=
- "sc_trace(tf,signal_xicu_irq[" + i +
- "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
- i++;
- }
-
- netlist +=
- "sc_trace(tf,signal_xicu_irq[" + i +
- "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
- netlist +=
- "sc_trace(tf,signal_xicu_irq[" + i +
- "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
- netlist +=
- "sc_trace(tf,signal_xicu_irq[" + i +
- "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
-
- for (AvatarRAM ram:TopCellGenerator.avatardd.
- getAllRAM ())
- {
- if (ram.getMonitored () == 0)
- {
- netlist +=
- "sc_trace(tf,signal_vci_vciram" +
- ram.getIndex () + ",\"Memory" +
- ram.getIndex () + "\");" + CR;
- }
- }
- }
+ {
+ netlist += "sc_trace_file *tf;" + CR;
+ netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
+ netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
+ netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
+
+ netlist +=
+ "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" +
+ CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");"
+ + CR;
+
+ for (i = 0; i < TopCellGenerator.avatardd.getNb_init (); i++)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_m[" + i +
+ "] ,\"signal_vci_m[" + i + "]\");" + CR;
+ }
+
+ i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ netlist +=
+ "sc_trace(tf,signal_vci_tty" + tty.getNo_tty () +
+ ",\"TTY" + tty.getNo_tty () + "\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ i++;
+ }
+
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_vciram" +
+ ram.getIndex () + ",\"Memory" +
+ ram.getIndex () + "\");" + CR;
+ }
+ }
+ }
netlist =
netlist +
" sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
@@ -875,11 +973,12 @@ public class NetList
netlist = netlist + " signal_resetn = true;" + CR;
netlist = netlist + " sc_core::sc_start();" + CR;
if (tracing)
- {
- netlist += "sc_close_vcd_trace_file(tf);" + CR;
- }
+ {
+ netlist += "sc_close_vcd_trace_file(tf);" + CR;
+ }
netlist = netlist + CR + " return EXIT_SUCCESS;" + CR;
netlist = netlist + "}" + CR;
+
return netlist;
}
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java-bak b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java-bak
new file mode 100755
index 0000000000000000000000000000000000000000..181c39049caa228ecee8b43571c7ee46144bd50b
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java-bak
@@ -0,0 +1,958 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCPU;
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+import ddtranslatorSoclib.AvatarCrossbar;
+
+public class NetList
+{
+ public static final String NAME_CLK = "signal_clk";
+ public static final String CR = "\n";
+ public static final String CR2 = "\n\n";
+ private static final String NAME_RST = "signal_resetn";
+ private static boolean tracing;
+
+
+ public static int cpus_in_cluster(int cluster_no){
+ int cpus=1;
+ return cpus;
+ }
+
+ public static String getNetlist (String icn, boolean _tracing)
+ {
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar().size ();
+ int coproc_count = 0;
+
+ tracing = _tracing;
+
+ String netlist;
+
+ netlist =
+ CR2 +
+ "//------------------------------Netlist---------------------------------"
+ + CR2;
+
+ netlist = netlist + "// icu" + CR2;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));"
+ + CR2;
+
+ netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
+ netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");"
+ + CR;
+
+ netlist =
+ netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
+ CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");"
+ + CR2;
+ netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
+ netlist =
+ netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
+ netlist = netlist + " {" + CR;
+ netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
+ netlist =
+ netlist +
+ " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
+ netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
+ netlist = netlist + " }" + CR2;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
+ CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" +
+ CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());"
+ + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());"
+ + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist =
+ netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
+ netlist =
+ netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
+
+ netlist = netlist + "///////////////// cpus" + CR2;
+
+ netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
+ netlist =
+ netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
+ netlist = netlist + " // configure het_rom" + CR;
+
+ int i=0;
+ if(nb_clusters==0){
+ netlist =
+ netlist +
+ " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
+
+ netlist = netlist + " // add cpu node to device tree" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+ netlist =netlist + " }"+ CR;
+
+ }
+ else{
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar ()){
+
+ netlist =netlist + "for ( size_t j = 0; j < " +cpus_in_cluster(i)+"; ++j ){" + CR;
+ netlist = netlist +
+ " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab("+crossbar.getClusterIndex() +",j));" + CR;
+ netlist = netlist + " // add cpu node to device tree" + CR;
+
+ netlist = netlist +
+ " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+
+ netlist =netlist + " }"+ CR;
+
+ netlist =netlist + "crossbar"+crossbar.getClusterIndex()+".p_initiator_to_up(signal_down"+crossbar.getClusterIndex()+");"+ CR;
+ netlist =netlist + "crossbar"+crossbar.getClusterIndex()+".p_target_to_up(signal_up"+crossbar.getClusterIndex()+");"+ CR;
+ if (icn == "vgmn"){
+ netlist =netlist + "vgmn.p_to_initiator["+0+"](signal_down"+crossbar.getClusterIndex()+");"+ CR;
+ netlist =netlist + "vgmn.p_to_target["+0+"](signal_up"+crossbar.getClusterIndex()+");"+ CR;
+ }
+ else{
+ netlist =netlist + "vgsb.p_to_initiator["+0+"](signal_down"+crossbar.getClusterIndex()+");"+ CR;
+ netlist =netlist + "vgsb.p_to_target["+0+"](signal_up"+crossbar.getClusterIndex()+");"+ CR;
+ }
+ netlist =netlist + "for ( size_t j = 0; j < " + cpus_in_cluster(i) +"; ++j ){" + CR;
+ netlist =
+ netlist +
+ " cpus[i]->connect(cpus["+crossbar.getClusterIndex()+"], signal_clk, signal_resetn, signal_vci_m"+crossbar.getClusterIndex()+"[j]);"+ CR;
+ netlist =
+ netlist +"}" + CR;
+ netlist = netlist + "// connected cluster" + +crossbar.getClusterIndex()+"."+CR2;
+ i++;
+ }
+ }
+
+ if(nb_clusters==0){
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ }
+ else{
+ int j;
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar ())
+ {
+ i=0;
+
+ for (j=0;j< cpus_in_cluster(i) ;j++){
+ netlist =
+ netlist + "crossbar"+crossbar.getClusterIndex()+".p_to_initiator[i](signal_vci_m"+crossbar.getClusterIndex()+"[j]);" + CR;
+ i++;
+ }
+ }
+ }
+
+
+ netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
+ netlist = netlist + " }" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " vcihetrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcifdtrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcisimhelper.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirttimer.p_clk(signal_clk);" + CR;
+
+ netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcifdtrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcisimhelper.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirttimer.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
+
+ netlist = netlist + " vcifdtrom.p_vci(signal_vci_vcifdtrom);" + CR;
+ netlist = netlist + " vcirom.p_vci(signal_vci_vcirom);" + CR;
+ netlist =
+ netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
+ netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
+ netlist =
+ netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
+
+ if(nb_clusters==0){
+ if (icn == "vgmn")
+ {
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
+ netlist =
+ netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist =
+ netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist =
+ netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
+ netlist =
+ netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+ else
+ {
+ netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
+ netlist =
+ netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist =
+ netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist =
+ netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
+ netlist =
+ netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+ }
+ else{//clustered
+ if (icn == "vgmn")
+ {
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ }
+ else{
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ }
+ //in any case for clustered, initiators and targets are attached to crossbar
+ netlist = netlist + " crossbar.p_clk(signal_clk);" + CR;
+ netlist = netlist + " crossbar.p_resetn(signal_resetn);" + CR;
+
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar ()){
+ i=0;
+ netlist = netlist + "crossbar"+crossbar.getClusterIndex()+".p_to_initiator["+crossbar.getClusterIndex()+"](signal_vci_m"+crossbar.getClusterIndex()+"["+ cpus_in_cluster(i) +"]);" + CR;
+ }
+
+
+ if (nb_clusters == 0){
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
+ }
+ }
+
+ /* clustered version */
+ /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster */
+ else
+ {
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ //target number for local cluster: this is set at avatardd creation
+ netlist =
+ netlist + "crossbar" + ram.getNo_cluster () +
+ ".p_to_target[" + ram.getNo_target () +
+ "](signal_vci_vciram" + ram.getIndex () + ");" + CR2;
+ }
+
+ /*convention for local target ids on cluster :
+ channel: 0
+ mwmr_ram: 1
+ mwmrd_ram: 2
+ locks: 3
+ ram: 4
+ tty: 5
+ */
+
+ }
+
+ if (nb_clusters == 0)
+ {
+
+ int l = 8; //number of last tty
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ for (i = 0; i < coproc_count; i++)
+ {
+
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+ else
+ { //vgsb
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ for (i = 0; i < coproc_count; i++)
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+
+ }
+ else
+ {
+ /* cluster */
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ }
+
+ netlist =
+ netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
+ netlist = netlist + "vcifdtrom.end_node();;" + CR2;
+
+ netlist = netlist + "// TTY netlist" + CR2;
+ i=0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.getAllTTY ())
+ {
+ netlist =
+ netlist + tty.getTTYName () + ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_vci(signal_vci_tty" + i +
+ ");" + CR2;
+ int no_irq_tty = 0;
+ if (nb_clusters == 0)
+ {
+
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" + i + "\");" +
+ CR2;
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" +
+ tty.getNo_tty () + "\");" + CR2;
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ }
+
+ //we have a clustered architecture: identify local crossbar
+ else
+ {
+ int j;
+ for (j = 0; j < nb_clusters; j++)
+ {
+ netlist =
+ netlist + "crossbar" + j + ".p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + j +
+ ");" + CR2;
+ //recalculate irq addresses, 5 devices generating irq per cluster
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" +
+ (tty.getNo_cluster () * 5) + "]);" + CR2;
+ }
+ }
+ i++;
+ //One ICU per cluster per default
+ no_irq_tty += 6; //if there is more than one tty, irq >5
+ }
+
+ //////////////// fdrom
+
+ netlist = netlist + "{" + CR2;
+ netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");"
+ + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");"
+ + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR;
+ netlist = netlist + "}" + CR2;
+
+ //////////////// ethernet
+
+ netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
+ netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// block device
+
+ netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
+ netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
+ netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// fd access
+ netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
+
+ netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
+ netlist =
+ netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR2;
+
+ i = 0;
+ int j = 0;
+
+ for (AvatarCoproMWMR copro:TopCellGenerator.
+ avatardd.getAllCoproMWMR ())
+ {
+ //IE and OE packet engines are special cases as they have VCI an fifo initiator interface
+ if (copro.getCoprocType () == 0)
+ {
+ i = 0;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_IE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_pktdesc[0](signal_fifo_" + j + "_" + i +
+ "_to_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_from_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_IE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_IE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_OE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_desc(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i + "_to_ctrl);" +
+ CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_to_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_OE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_OE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName ()+ ".p_from_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () + ".p_to_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
+ }
+
+
+ //additional interfaces for IE and OE
+
+ if (copro.getCoprocType () == 0)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //pktdesc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_from_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_IE_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_IE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //desc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_OE_to_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_OE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_target(signal_mwmr_" + i +
+ "_target);" + CR2;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_from_coproc[" + i +
+ "](signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_to_coproc[" + i + "](signal_fifo_" +
+ j + "_" + i + "_to_ctrl);" + CR;
+ }
+ i++;
+ }
+ j++;
+ coproc_count++;
+ }
+
+
+ //If there is a spy, add logger or stats to vci interface
+
+ i = 0;
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+ int number = cpu.getNo_proc ();
+ if (cpu.getMonitored () == 1)
+ {
+ netlist = netlist + CR +
+ "logger" + i + ".p_clk(signal_clk);" + CR +
+ "logger" + i + ".p_resetn(signal_resetn);" + CR +
+ "logger" + i + ".p_vci(signal_vci_m[" + number +
+ "]);" + CR2;
+ i++;
+ }
+
+ }
+ j = 0;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 1)
+ {
+ int number = number = ram.getIndex ();
+ netlist += "logger" + i + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "logger" + i + ".p_resetn(signal_resetn);" + CR;
+ netlist +=
+ "logger" + i + ".p_vci(signal_vci_vciram" + number +
+ ");" + CR2;
+ i++;
+ }
+ else
+ {
+
+ if (ram.getMonitored () == 2)
+ {
+ int number = number = ram.getIndex ();
+ netlist +=
+ "mwmr_stats" + j + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_vci(signal_vci_vciram" +
+ number + ");" + CR2;
+ j++;
+ }
+ }
+ }
+
+
+ int p = 0;
+
+ //generate trace file if marked trace option
+
+ if (tracing)
+ {
+ netlist += "sc_trace_file *tf;" + CR;
+ netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
+ netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
+ netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
+
+ netlist +=
+ "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" +
+ CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");"
+ + CR;
+
+ for (i = 0; i < TopCellGenerator.avatardd.getNb_init (); i++)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_m[" + i +
+ "] ,\"signal_vci_m[" + i + "]\");" + CR;
+ }
+
+ i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ netlist +=
+ "sc_trace(tf,signal_vci_tty" + tty.getNo_tty () +
+ ",\"TTY" + tty.getNo_tty () + "\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ i++;
+ }
+
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_vciram" +
+ ram.getIndex () + ",\"Memory" +
+ ram.getIndex () + "\");" + CR;
+ }
+ }
+ }
+ netlist =
+ netlist +
+ " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = false;" + CR;
+ netlist =
+ netlist +
+ " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = true;" + CR;
+ netlist = netlist + " sc_core::sc_start();" + CR;
+ if (tracing)
+ {
+ netlist += "sc_close_vcd_trace_file(tf);" + CR;
+ }
+ netlist = netlist + CR + " return EXIT_SUCCESS;" + CR;
+ netlist = netlist + "}" + CR;
+ return netlist;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java b/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java
index a233537b4ed1887b13fb28883d0fc3f34ac03fb6..794b41528f5ad5db0814b3cc713d512e880aef58 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java
@@ -38,142 +38,167 @@
* knowledge of the CeCILL license and that you accept its terms.
*/
-
-
-
/* This class generates the lines of the topcell where the signals are declared*/
/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarSpecification;
+import ddtranslatorSoclib.*;
import ddtranslatorSoclib.AvatarCoproMWMR;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
+import ddtranslatorSoclib.AvatarCrossbar;
-public class Signal {
+public class Signal {
+ public static AvatarddSpecification avatardd;
private final static String CR = "\n";
private final static String CR2 = "\n\n";
private final static String NAME_CLK = "signal_clk";
private static final String NAME_RST = "signal_resetn";
- public static String getSignal() {
- int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- //nb_clusters=2;
- String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
-
- signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];"+ CR;
- signal = signal + "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");"+ CR;
- signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");"+ CR;
- signal = signal +" caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");"+ CR;
- signal = signal +" caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");"+ CR;
- signal = signal +" caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");"+ CR;
- //signal = signal +"caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");"+ CR;
-//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
-//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccessi;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccesst;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_bdi;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_bdt;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_etherneti;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_vci_ethernett;"+ CR;
- signal = signal +""+ CR;
- signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
- signal = signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" + CR2;
- int i=0;
+public static int cpus_in_cluster(AvatarddSpecification dd,int cluster_no){
+ avatardd = dd;
+ int cpus=0;
+ for (AvatarConnector connector : avatardd.getConnectors()){
+ AvatarConnectingPoint my_p1= connector.get_p1();
+ AvatarConnectingPoint my_p2= connector.get_p2();
+
+ AvatarComponent comp1 = my_p1.getComponent();
+ AvatarComponent comp2 = my_p2.getComponent();
+ if (comp1 instanceof AvatarCPU){
+ AvatarCPU comp1cpu = (AvatarCPU)comp1;
+ cpus++;
+ }
+
+ }
+ return cpus;
+ }
+
-for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()) {
-
- //DG 27.04. additional VCI signals for IE and OE
- if(copro.getCoprocType()==0){
- signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_IE(\"signal_vci_IE\");"+CR;
+
+ public static String getSignal(AvatarddSpecification dd) {
+ avatardd = dd;
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
+
+ int i;
+ String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
+ if (nb_clusters==0){
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];"+ CR;
+ }
+ else{
+ for(i=0;i<nb_clusters;i++){
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_m"+i+"["+ (cpus_in_cluster(avatardd,i)+ 1)+"];"+ CR;
+ }
+ }
+
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");"+ CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");"+ CR;
+ signal = signal +" caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");"+ CR;
+ signal = signal +" caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");"+ CR;
+ signal = signal +" caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");"+ CR;
+ //signal = signal +"caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");"+ CR;
+ //signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
+ //signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccessi;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccesst;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_bdi;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_bdt;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_etherneti;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_vci_ethernett;"+ CR;
+ signal = signal +""+ CR;
+ signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
+ signal = signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" + CR2;
+
+
+ for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ i=0;
+ if(copro.getCoprocType()==0){
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_IE(\"signal_vci_IE\");"+CR;
signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
- signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_from_ctrl;"+ CR;
- signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_1_from_ctrl;"+ CR;
- signal = signal +"sc_core::sc_signal<uint32_t> signal_IE_from_ctrl;"+ CR;
- signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_to_ctrl;"+ CR;
- signal = signal +"sc_core::sc_signal<uint32_t> signal_IE_to_ctrl;"+ CR;
- }
- else { if(copro.getCoprocType()==1){
- signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_OE(\"signal_vci_OE\");"+CR;
- signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
- signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_from_ctrl;"+ CR;
- signal = signal +"sc_core::sc_signal<uint32_t> signal_OE_from_ctrl;"+ CR;
- signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_to_ctrl;"+ CR;
- signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_1_to_ctrl;"+ CR;
- signal = signal +"sc_core::sc_signal<uint32_t> signal_OE_to_ctrl;"+ CR;
- }
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
+ signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_from_ctrl;"+ CR;
+ signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_1_from_ctrl;"+ CR;
+ signal = signal +"sc_core::sc_signal<uint32_t> signal_IE_from_ctrl;"+ CR;
+ signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_to_ctrl;"+ CR;
+ signal = signal +"sc_core::sc_signal<uint32_t> signal_IE_to_ctrl;"+ CR;
+ }
+ else {
+ if(copro.getCoprocType()==1){
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_OE(\"signal_vci_OE\");"+CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
+ signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_from_ctrl;"+ CR;
+ signal = signal +"sc_core::sc_signal<uint32_t> signal_OE_from_ctrl;"+ CR;
+ signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_0_to_ctrl;"+ CR;
+ signal = signal +"soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_1_to_ctrl;"+ CR;
+ signal = signal +"sc_core::sc_signal<uint32_t> signal_OE_to_ctrl;"+ CR;
+ }
- else{
- signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
- signal = signal +" soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_from_ctrl;"+ CR;
- signal = signal +" soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_to_ctrl;"+ CR;
- }
+ else{
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
+ signal = signal +" soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_from_ctrl;"+ CR;
+ signal = signal +" soclib::caba::FifoSignals<uint32_t> signal_fifo_"+i+"_to_ctrl;"+ CR;
+ }
- }
- i++;
+ }
+ i++;
- /* signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+p+"_target(\"signal_mwmr"+p+"_target\""+CR;
- signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+p+"_initiator(\"signal_mwmr"+p+"_initiator\"" +CR;
-
- signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_to_ctrl"+p+"(\"signal_fifo_to_ctrl"+p+"\");"+CR;
- signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_from_ctrl"+p+"(\"signal_fifo_from_ctrl"+p+"\");"+CR;
- p++;*/
-}
-
- signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
-
- //System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
- // System.out.print("number of clusters : " + TopCellGenerator.avatardd.getNbClusters()+"\n");
-
- i = 0;
- if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()){
- // signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
- // + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
- signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + i
- + "(\"signal_vci_vciram" + i + "\");" + CR2;
- i++;
- }
- i = 0;
+ /* signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+p+"_target(\"signal_mwmr"+p+"_target\""+CR;
+ signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+p+"_initiator(\"signal_mwmr"+p+"_initiator\"" +CR;
+ signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_to_ctrl"+p+"(\"signal_fifo_to_ctrl"+p+"\");"+CR;
+ signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_from_ctrl"+p+"(\"signal_fifo_from_ctrl"+p+"\");"+CR;
+ p++;*/
+ }
+ signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+
+ i = 0;
+ if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()){
+ // signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ // + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + i
+ + "(\"signal_vci_vciram" + i + "\");" + CR2;
+ i++;
+ }
+ i = 0;
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
- //signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
-signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
-i++;
- }
-
- // signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
- // System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
-
-
- }
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ //signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
+ i++;
+ }
+ // signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+ // System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
+ }
-else{
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
- signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
- + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2; i=0;
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
- // signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
-signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
+ else{
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2; i=0;
+ for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
+ // signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
i++;
- }
- int p=0;
- // if (with_hw_accellerator>0){ //DG 23.08.
-
+ }
+ int p=0;
+ }
-
-}
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.getAllCrossbar()){
-return signal;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_up"+crossbar.getClusterIndex()+"(\"signal_up"+crossbar.getClusterIndex()+"\");"+CR;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_down"+crossbar.getClusterIndex()+"(\"signal_down"+crossbar.getClusterIndex()+"\");"+CR;
}
+
+ return signal;
+ }
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Simulation.java b/src/main/java/ddtranslatorSoclib/toTopCell/Simulation.java
index d7f606f3cd306c6b7cbf09f0bf6514fae7b09ebb..fbe5d1514c57de2c205b46ca6b6605689c8ea0bf 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Simulation.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Simulation.java
@@ -92,6 +92,7 @@ public class Simulation {
simulation = simulation+ CR +" return 1;"+ CR + "}" ;
//return simulation;
}
+
return simulation;
}
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/TopCellGenerator.java b/src/main/java/ddtranslatorSoclib/toTopCell/TopCellGenerator.java
index 8651231b834c49bf0fca3e793ed9a92da34fccbe..c10743c12180836285d3728e47b403ae3f82c118 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/TopCellGenerator.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/TopCellGenerator.java
@@ -181,11 +181,11 @@ public class TopCellGenerator
VCIparameters +
config +
Code.getCode() +
- MappingTable.getMappingTable() +
- Loader.getLoader(avspec) + //DG 23.06.
- Declaration.getDeclarations(avspec) + //DG 27.06.
- Signal.getSignal() +
- NetList.getNetlist(icn,tracing) +
+ MappingTable.getMappingTable(avatardd) +
+ Loader.getLoader(avspec) +
+ Declaration.getDeclarations(avatardd,avspec) +
+ Signal.getSignal(avatardd) +
+ NetList.getNetlist(avatardd,icn,tracing) +
Simulation.getSimulation();
return (top);
}
diff --git a/src/main/java/ui/AvatarDeploymentPanelTranslator.java b/src/main/java/ui/AvatarDeploymentPanelTranslator.java
index b386c6dc8e3a632a52e4781719a5081b13d2c900..dd1e8445bada6e79340b7fe6260003000a26e5ed 100644
--- a/src/main/java/ui/AvatarDeploymentPanelTranslator.java
+++ b/src/main/java/ui/AvatarDeploymentPanelTranslator.java
@@ -68,15 +68,15 @@ public class AvatarDeploymentPanelTranslator
*
* Other targets :
* the simhelper segment (target 3)
- * the icu segment (target 4)
- * the timer segment (target 5)
- * the fdt segment (target 6)
+ * the timer segment (target 4)
+ * the ICU segment (target 5)
+ * the DMA segment (target 6)
*
* There always is a RAM0
*/
- private int nb_target = 6;
-
+
+ private int nb_target = 0;
private int no_tty = 0;
private int nb_clusters = 0;
@@ -126,6 +126,7 @@ public class AvatarDeploymentPanelTranslator
ICacheSets, ICacheWords, dCacheWays,
dCacheSets, dCacheWords, nb_init,
addCPUNode.getIndex (),
+ addCPUNode.getClusterIndex (),
addCPUNode.getMonitored ());
@@ -160,7 +161,7 @@ public class AvatarDeploymentPanelTranslator
int index = tty.getIndex ();
String ttyName = tty.getNodeName ();
- AvatarTTY avtty = new AvatarTTY (ttyName, index, index, index); //DG 3.7.
+ AvatarTTY avtty = new AvatarTTY (ttyName, index, index, index);
nb_target++;
avatarMap.put (dp, avtty);
@@ -292,8 +293,10 @@ public class AvatarDeploymentPanelTranslator
int nStatus = addCoproMWMRNode.getNStatus (); // nb of status registers
boolean useLLSC = addCoproMWMRNode.getUseLLSC (); // more efficient protocol. 0: not used. 1 or more -> used
int coprocType = addCoproMWMRNode.getCoprocType (); //virtual or real?
+ int cluster_address = addCoproMWMRNode.getClusterAddress ();
+
nb_init++;
- nb_target += 2; //DG 28.08. two targets as two segments of memory are created mwmr and mwmrd
+ nb_target += 2;
AvatarCoproMWMR acpMWMR;
//DG 19.09. map tasks to coproc
@@ -302,7 +305,7 @@ public class AvatarDeploymentPanelTranslator
plaps, fifoToCoprocDepth,
fifoFromCoprocDepth, nToCopro,
nFromCopro, nConfig, nStatus,
- useLLSC, coprocType);
+ useLLSC, coprocType, cluster_address);
// DG 27.04. : pourquoi deux fois new coproc? Bien: on peut mapper les tasks :)
Vector < ADDBlockArtifact > tasks =
@@ -331,7 +334,7 @@ public class AvatarDeploymentPanelTranslator
plaps, fifoToCoprocDepth,
fifoFromCoprocDepth, nToCopro,
nFromCopro, nConfig, nStatus,
- useLLSC, coprocType);
+ useLLSC, coprocType,cluster_address);
avatarMap.put (dp, acpMWMR);
avatarComponents.add (acpMWMR);
@@ -346,16 +349,18 @@ public class AvatarDeploymentPanelTranslator
ADDRAMNode addRamNode = (ADDRAMNode) dp;
String name = addRamNode.getNodeName ();
int index = addRamNode.getIndex ();
+ int cluster_index = addRamNode.getClusterIndex ();
int byteDataSize = addRamNode.getDataSize ();
//int monitored = addRamNode.getMonitored();
AvatarRAM avram =
- new AvatarRAM (name, index, byteDataSize, index,
+ new AvatarRAM (name, byteDataSize,
+ cluster_index,
index,
addRamNode.getMonitored ());
avram.setNo_ram (index);
- int cluster_index = avram.getIndex ();
+
nb_target++;
@@ -369,7 +374,7 @@ public class AvatarDeploymentPanelTranslator
String referenceDiagram =
c.getReferenceDiagram ();
String channelName = c.getChannelName ();
- //channel is inevitably on same cluster as RAM it is mapped on :)
+
AvatarChannel avcl =
new AvatarChannel (referenceDiagram,
channelName, avram,
@@ -439,7 +444,7 @@ public class AvatarDeploymentPanelTranslator
if ((((AvatarRAM) avowner_p1).getMonitored () == 2)
|| (spy == true))
- //if (((AvatarRAM)avowner_p1).getMonitored() == 2)
+
{
monitored = 2;
diff --git a/src/main/java/ui/avatardd/ADDCPUNode.java b/src/main/java/ui/avatardd/ADDCPUNode.java
index 03b3e788cfd32bd74e897debc35d9f06eac277c0..4993a955f80b3c05b51cbebe047a9b38c822f19e 100755
--- a/src/main/java/ui/avatardd/ADDCPUNode.java
+++ b/src/main/java/ui/avatardd/ADDCPUNode.java
@@ -76,6 +76,7 @@ public class ADDCPUNode extends ADDNode implements SwallowTGComponent, WithAttri
private int dCacheWords = 0;
protected int index = 0;
+ protected int cluster_index = 0;
protected int monitored = 0;
@@ -346,6 +347,22 @@ public class ADDCPUNode extends ADDNode implements SwallowTGComponent, WithAttri
}
}
+ if (dialog.getIndex().length() != 0) {
+ try {
+ tmp = cluster_index;
+ cluster_index = Integer.decode(dialog.getIndex()).intValue();
+ if (cluster_index < 0) {
+ cluster_index = tmp;
+ error = true;
+ errors += "cluster index ";
+ }
+ } catch (Exception e) {
+ error = true;
+ errors += "cluster index ";
+ }
+ }
+
+
if (dialog.getMonitored() != 0) {
try {
@@ -547,6 +564,10 @@ public class ADDCPUNode extends ADDNode implements SwallowTGComponent, WithAttri
return index;
}
+ public int getClusterIndex() {
+ return cluster_index;
+ }
+
public int getMonitored() {
return monitored;
}
diff --git a/src/main/java/ui/avatardd/ADDCoproMWMRNode.java b/src/main/java/ui/avatardd/ADDCoproMWMRNode.java
index 5b0396078b7b954751cd1b34e983d18a7ccd01d4..734e7028eefa0e94b725073283736a605e5a91ba 100755
--- a/src/main/java/ui/avatardd/ADDCoproMWMRNode.java
+++ b/src/main/java/ui/avatardd/ADDCoproMWMRNode.java
@@ -513,7 +513,11 @@ public class ADDCoproMWMRNode extends ADDCommunicationNode implements WithAttrib
return coprocType;
}
- //DG 19.09.
+ public int getClusterAddress() {
+ return 2;//ToDo find crossbar to which coproc is attached
+ }
+
+
public Vector<ADDBlockArtifact> getArtifactList() {
Vector<ADDBlockArtifact> v = new Vector<ADDBlockArtifact>();
diff --git a/src/main/java/ui/avatardd/ADDMemoryNode.java b/src/main/java/ui/avatardd/ADDMemoryNode.java
index b04130d39127d20139875a4726c941891338431d..8ee0b58e0f475e0218d7722c6c64fa7593aad5d6 100755
--- a/src/main/java/ui/avatardd/ADDMemoryNode.java
+++ b/src/main/java/ui/avatardd/ADDMemoryNode.java
@@ -66,6 +66,7 @@ public abstract class ADDMemoryNode extends ADDCommunicationNode implements With
protected String stereotype = "RAM";
protected int index = 0;
+ protected int cluster_index = 0;
protected int monitored = 0;
protected int byteDataSize = HwMemory.DEFAULT_BYTE_DATA_SIZE;
@@ -137,6 +138,10 @@ public abstract class ADDMemoryNode extends ADDCommunicationNode implements With
return index;
}
+ public int getClusterIndex() {
+ return cluster_index;
+ }
+
public int getDataSize() {
return byteDataSize;
}
@@ -186,6 +191,23 @@ public abstract class ADDMemoryNode extends ADDCommunicationNode implements With
}
}
+ if (dialog.getClusterIndex().length() != 0) {
+ try {
+ tmp = cluster_index;
+ index = Integer.decode(dialog.getClusterIndex()).intValue();
+ if (index < 0) {
+ index = tmp;
+ error = true;
+ errors += "cluster index ";
+ }
+ } catch (Exception e) {
+ error = true;
+ errors += "cluster index ";
+ }
+ }
+
+
+
if (dialog.getDataSize().length() != 0) {
try {
tmp = byteDataSize;
diff --git a/src/main/java/ui/window/JDialogADDCPUNode.java b/src/main/java/ui/window/JDialogADDCPUNode.java
index 8536888e6f8c56188388ff805fe51517211caadc..d640923aa58f549fdf13801a3ad518a64ac9e3b2 100755
--- a/src/main/java/ui/window/JDialogADDCPUNode.java
+++ b/src/main/java/ui/window/JDialogADDCPUNode.java
@@ -79,6 +79,7 @@ public class JDialogADDCPUNode extends JDialogBase implements ActionListener {
// Panel2
protected JTextField nbOfIrq, iCacheWays, iCacheSets, iCacheWords, dCacheWays, dCacheSets, dCacheWords;
protected JTextField index;
+ protected JTextField cluster_index;
protected JTextField monitored;
/** Creates new form */
@@ -177,11 +178,17 @@ public class JDialogADDCPUNode extends JDialogBase implements ActionListener {
panel2.add(dCacheWords, c2);
c2.gridwidth = 1;
- panel2.add(new JLabel("Index:"), c2);
+ panel2.add(new JLabel("Index:"), c2);//DG 2.7.
c2.gridwidth = GridBagConstraints.REMAINDER; //end row
index = new JTextField(""+node.getIndex(), 15);
panel2.add(index, c2);
+ c2.gridwidth = 1;
+ panel2.add(new JLabel("Cluster Index:"), c2);//DG 2.7.
+ c2.gridwidth = GridBagConstraints.REMAINDER; //end row
+ cluster_index = new JTextField(""+node.getIndex(), 15);
+ panel2.add(cluster_index, c2);
+
c2.gridwidth = 1;
panel2.add(new JLabel("Monitored:"), c2);
//c2.gridwidth = GridBagConstraints.REMAINDER; //end row
diff --git a/src/main/java/ui/window/JDialogADDMemoryNode.java b/src/main/java/ui/window/JDialogADDMemoryNode.java
index 28108c461f7417fa464ae672260728270c9388dc..d8c7aaaece5c8878e7bf0b357d14e3b1fbc2f7e9 100755
--- a/src/main/java/ui/window/JDialogADDMemoryNode.java
+++ b/src/main/java/ui/window/JDialogADDMemoryNode.java
@@ -76,6 +76,7 @@ public class JDialogADDMemoryNode extends JDialogBase implements ActionListener
// Panel2
protected JTextField index;
+ protected JTextField cluster_index;
protected JTextField dataSize;
protected JTextField monitored;
@@ -221,7 +222,14 @@ public class JDialogADDMemoryNode extends JDialogBase implements ActionListener
c2.gridwidth = GridBagConstraints.REMAINDER; //end row
index = new JTextField(""+node.getIndex(), 15);
panel2.add(index, c2);
+
+ c2.gridwidth = 1;
+ panel2.add(new JLabel("Cluster Index:"), c2);
+ c2.gridwidth = GridBagConstraints.REMAINDER; //end row
+ cluster_index = new JTextField(""+node.getIndex(), 15);
+ panel2.add(cluster_index, c2);
+
c2.gridwidth = 1;
panel2.add(new JLabel("Data size (in byte):"), c2);
c2.gridwidth = GridBagConstraints.REMAINDER; //end row
@@ -328,6 +336,10 @@ public class JDialogADDMemoryNode extends JDialogBase implements ActionListener
public String getIndex() {
return index.getText();
}
+
+ public String getClusterIndex() {
+ return cluster_index.getText();
+ }
public String getDataSize() {
return dataSize.getText();