diff --git a/MPSoC/mutekh/arch/soclib/ldscript.cpp b/MPSoC/mutekh/arch/soclib/ldscript.cpp
index af21628dbc0b4a3af509c2f219c1a3dadf80d93d..cb874fee26a63d320682de6282996324906def6f 100644
--- a/MPSoC/mutekh/arch/soclib/ldscript.cpp
+++ b/MPSoC/mutekh/arch/soclib/ldscript.cpp
@@ -118,26 +118,104 @@ vci_locks (RWAL): ORIGIN = 0xC0200000, LENGTH = 0x100
#if defined(DEPLOY_RAM9_NAME)
DEPLOY_RAM9_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
#endif
-#if defined(CACHED_RAM3_NAME)
- CACHED_RAM3_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
+#if defined(DEPLOY_RAM10_NAME)
+ DEPLOY_RAM10_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
#endif
-#if defined(CACHED_RAM4_NAME)
+#if defined(CACHED_RAM10_NAME)
+ CACHED_RAM10_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
+#endif
+#if defined(DEPLOY_RAM11_NAME)
+ DEPLOY_RAM11_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
+#endif
+#if defined(CACHED_RAM11_NAME)
+ CACHED_RAM1_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
+#endif
+#if defined(DEPLOY_RAM12_NAME)
+ DEPLOY_RAM12_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
+#endif
+#if defined(CACHED_RAM12_NAME)
+ CACHED_RAM12_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
+#endif
+#if defined(DEPLOY_RAM13_NAME)
+ DEPLOY_RAM13_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
+#endif
+#if defined(CACHED_RAM13_NAME)
+ CACHED_RAM13_NAME (RWAL): ORIGIN = CACHED_RAM3_ADDR, LENGTH = CACHED_RAM3_SIZE
+#endif
+#if defined(DEPLOY_RAM14_NAME)
+ DEPLOY_RAM13_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
+#endif
+#if defined(CACHED_RAM14_NAME)
CACHED_RAM4_NAME (RWAL): ORIGIN = CACHED_RAM4_ADDR, LENGTH = CACHED_RAM4_SIZE
#endif
-#if defined(CACHED_RAM5_NAME)
- CACHED_RAM5_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
+#if defined(DEPLOY_RAM15_NAME)
+ DEPLOY_RAM15_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
+#endif
+#if defined(CACHED_RAM15_NAME)
+ CACHED_RAM15_NAME (RWAL): ORIGIN = CACHED_RAM5_ADDR, LENGTH = CACHED_RAM5_SIZE
+#endif
+#if defined(DEPLOY_RAM16_NAME)
+ DEPLOY_RAM16_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
#endif
-#if defined(CACHED_RAM6_NAME)
- CACHED_RAM6_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
+#if defined(CACHED_RAM16_NAME)
+ CACHED_RAM16_NAME (RWAL): ORIGIN = CACHED_RAM6_ADDR, LENGTH = CACHED_RAM6_SIZE
#endif
-#if defined(CACHED_RAM7_NAME)
- CACHED_RAM7_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
+#if defined(DEPLOY_RAM17_NAME)
+ DEPLOY_RAM17_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
#endif
-#if defined(CACHED_RAM8_NAME)
+#if defined(CACHED_RAM17_NAME)
+ CACHED_RAM17_NAME (RWAL): ORIGIN = CACHED_RAM7_ADDR, LENGTH = CACHED_RAM7_SIZE
+#endif
+#if defined(DEPLOY_RAM18_NAME)
+ DEPLOY_RAM18_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
+#endif
+#if defined(CACHED_RAM18_NAME)
CACHED_RAM8_NAME (RWAL): ORIGIN = CACHED_RAM8_ADDR, LENGTH = CACHED_RAM8_SIZE
#endif
-#if defined(CACHED_RAM9_NAME)
- CACHED_RAM9_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
+#if defined(DEPLOY_RAM19_NAME)
+ DEPLOY_RAM19_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
+#endif
+#if defined(CACHED_RAM19_NAME)
+ CACHED_RAM19_NAME (RWAL): ORIGIN = CACHED_RAM9_ADDR, LENGTH = CACHED_RAM9_SIZE
+#endif
+#if defined(DEPLOY_RAM20_NAME)
+ DEPLOY_RAM20_NAME (RWAL): ORIGIN = DEPLOY_RAM0_ADDR, LENGTH = DEPLOY_RAM0_SIZE
+#endif
+#if defined(CACHED_RAM20_NAME)
+ CACHED_RAM20_NAME (RWAL): ORIGIN = CACHED_RAM0_ADDR, LENGTH = CACHED_RAM0_SIZE
+#endif
+#if defined(DEPLOY_RAM21_NAME)
+ DEPLOY_RAM21_NAME (RWAL): ORIGIN = DEPLOY_RAM1_ADDR, LENGTH = DEPLOY_RAM1_SIZE
+#endif
+#if defined(CACHED_RAM21_NAME)
+ CACHED_RAM21_NAME (RWAL): ORIGIN = CACHED_RAM1_ADDR, LENGTH = CACHED_RAM1_SIZE
+#endif
+#if defined(DEPLOY_RAM22_NAME)
+ DEPLOY_RAM22_NAME (RWAL): ORIGIN = DEPLOY_RAM2_ADDR, LENGTH = DEPLOY_RAM2_SIZE
+#endif
+#if defined(CACHED_RAM22_NAME)
+ CACHED_RAM22_NAME (RWAL): ORIGIN = CACHED_RAM2_ADDR, LENGTH = CACHED_RAM2_SIZE
+#endif
+#if defined(DEPLOY_RAM23_NAME)
+ DEPLOY_RAM23_NAME (RWAL): ORIGIN = DEPLOY_RAM3_ADDR, LENGTH = DEPLOY_RAM3_SIZE
+#endif
+#if defined(DEPLOY_RAM24_NAME)
+ DEPLOY_RAM24_NAME (RWAL): ORIGIN = DEPLOY_RAM4_ADDR, LENGTH = DEPLOY_RAM4_SIZE
+#endif
+#if defined(DEPLOY_RAM25_NAME)
+ DEPLOY_RAM25_NAME (RWAL): ORIGIN = DEPLOY_RAM5_ADDR, LENGTH = DEPLOY_RAM5_SIZE
+#endif
+#if defined(DEPLOY_RAM26_NAME)
+ DEPLOY_RAM26_NAME (RWAL): ORIGIN = DEPLOY_RAM6_ADDR, LENGTH = DEPLOY_RAM6_SIZE
+#endif
+#if defined(DEPLOY_RAM27_NAME)
+ DEPLOY_RAM27_NAME (RWAL): ORIGIN = DEPLOY_RAM7_ADDR, LENGTH = DEPLOY_RAM7_SIZE
+#endif
+#if defined(DEPLOY_RAM28_NAME)
+ DEPLOY_RAM28_NAME (RWAL): ORIGIN = DEPLOY_RAM8_ADDR, LENGTH = DEPLOY_RAM8_SIZE
+#endif
+#if defined(DEPLOY_RAM29_NAME)
+ DEPLOY_RAM29_NAME (RWAL): ORIGIN = DEPLOY_RAM9_ADDR, LENGTH = DEPLOY_RAM9_SIZE
#endif
//fin ajoute DG
}
diff --git a/src/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java b/src/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java
index a26fda217d75ede732ae5593b56637e67408503b..863b8e7dc2541c4187c7d6d09097b78eb7de982b 100755
--- a/src/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java
+++ b/src/ddtranslatorSoclib/toSoclib/TasksAndMainGenerator.java
@@ -201,12 +201,14 @@ public class TasksAndMainGenerator {
//for(AvatarChannel ar: avspec.getChannels()) {
//for(AvatarChannel channel: ram.getChannels()){
for(AvatarRelation ar: avspec.getRelations()) {//DG 15.05.2017
+
+ for(int i=0; i<ar.nbOfSignals() ; i++) {//DG 15.05.2017
+
mainFile.appendToBeforeMainCode("#define CHANNEL"+d+" __attribute__((section(\"section_channel"+d+"\")))" + CR );
mainFile.appendToBeforeMainCode("#define LOCK"+d+" __attribute__((section(\"section_lock"+d+"\")))" + CR );//one lock per channel
- d++;
-
-
-
+ d++;
+ }
+ }
mainFile.appendToBeforeMainCode("#define base(arg) arg" + CR2 );
mainFile.appendToBeforeMainCode("typedef struct mwmr_s mwmr_t;" + CR2);
@@ -216,7 +218,7 @@ public class TasksAndMainGenerator {
mainFile.appendToMainCode("pthread_attr_t *attr_t = malloc(sizeof(pthread_attr_t));" +CR);
mainFile.appendToMainCode("pthread_attr_init(attr_t);" + CR );
mainFile.appendToMainCode("pthread_mutex_init(&__mainMutex, NULL);" +CR2);
- }
+
}
}
@@ -227,13 +229,19 @@ public class TasksAndMainGenerator {
mainFile.appendToHCode("/* Synchronous channels */" + CR);
mainFile.appendToBeforeMainCode("/* Synchronous channels */" + CR);
mainFile.appendToMainCode("/* Synchronous channels */" + CR);
+
for(AvatarRelation ar: avspec.getRelations()) {
if (!ar.isAsynchronous()) {
//ar.setId(j);
- ar.setId(i);//DG 15.05.2017
- j++;
- for(i=0; i<ar.nbOfSignals() ; i++) {
+ // ar.setId(i);//DG 15.05.2017
+ //j++;
+ //i++;
+ for(i=0; i<ar.nbOfSignals() ; i++) {
+ar.setId(i);//DG 15.05.2017
+//i++;
+ ar.setId(i);//DG 15.05.2017
+
mainFile.appendToHCode("extern syncchannel __" + getChannelName(ar, i) + ";" + CR);
mainFile.appendToBeforeMainCode("syncchannel __" +getChannelName(ar, i) + ";" + CR);
@@ -280,22 +288,23 @@ public class TasksAndMainGenerator {
mainFile.appendToBeforeMainCode("struct mwmr_s "+getChannelName(ar, i) +" CHANNEL"+ar.getId()+";" + CR2);
- }
+ }
}
}
}
public void makeAsynchronousChannels() {
if (avspec.ASynchronousExist()){
- // Create a synchronous channel per relation/signal
+ // Create an asynchronous channel per relation/signal
mainFile.appendToHCode("/* Asynchronous channels */" + CR);
mainFile.appendToBeforeMainCode("/* Asynchronous channels */" + CR);
mainFile.appendToMainCode("/* Asynchronous channels */" + CR);
int j=0;
for(AvatarRelation ar: avspec.getRelations()) {
- ar.setId(j); j++;//DG
+ //ar.setId(j); j++;//DG
if (ar.isAsynchronous()) {
for(int i=0; i<ar.nbOfSignals() ; i++) {
+ar.setId(i); i++;//DG 15.05.2017
mainFile.appendToHCode("extern asyncchannel __" + getChannelName(ar, i) + ";" + CR);
mainFile.appendToBeforeMainCode("asyncchannel __" +getChannelName(ar, i) + ";" + CR);
diff --git a/src/ddtranslatorSoclib/toTopCell/Deployinfo.java b/src/ddtranslatorSoclib/toTopCell/Deployinfo.java
index e7ed91391c2280a28d7f7677ba9d688d09d2b0b9..3f341d044007a16825a67f4efe327c471d8648d4 100755
--- a/src/ddtranslatorSoclib/toTopCell/Deployinfo.java
+++ b/src/ddtranslatorSoclib/toTopCell/Deployinfo.java
@@ -179,21 +179,25 @@ deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_ADDR 0x" +
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
//if (!(ram.getChannels().isEmpty())){
// for (AvatarChannel channel : ram.getChannels()) {
- //DG 15.05.2017
-
+
+ //DG 15.05.2017
for (AvatarRelation relation : avspec.getRelations()) {
//if (!(ram.getRelations().isEmpty())){
+ //
+ for(int i=0; i<ar.nbOfSignals() ; i++) {//DG 15.05.2017
deployinfo_map = deployinfo_map +"\n .channel"+i+" : { \\" + CR;
deployinfo_map = deployinfo_map + "*(section_channel"+i+ ")\\"+ CR;
deployinfo_map=deployinfo_map+ "} > uram"+ram.getNo_ram()+"\\"+ CR;
i++;
}
+ }
i=0;
// for (AvatarChannel channel : ram.getChannels()) {
for (AvatarRelation relation : avspec.getRelations()) {
//DG 15.05.2017
+ for(int i=0; i<ar.nbOfSignals() ; i++) {//DG 15.05.2017
deployinfo_map = deployinfo_map +"\n .lock"+i+" : { \\" + CR;
deployinfo_map = deployinfo_map + "*(section_lock"+i+ ")\\"+ CR;
// if(use_vcilocks) deployinfo_map=deployinfo_map+ "} > vci_locks\\"+ CR;
@@ -201,9 +205,10 @@ deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_ADDR 0x" +
i++;
}
- }
+ }
+ }
return deployinfo_map;
- }
+ }
public static String getProcInfo() {