<p>The simulator of DIPLODOCUS intends to simulate a DIPLODOCUS mapping, taking into account functional tasks, the system architectures (CPU, buses, etc.) and the allocations of tasks and their communucations to the system architecture</p> \n\
<p>The simulator of DIPLODOCUS intends to simulate a DIPLODOCUS mapping, taking into account functional tasks, the system architectures (CPU, buses, etc.) and the allocations of tasks and their communucations to the system architecture</p> \n\
<h2 id=\"generating-simulation-code-and-commiling-it\">Generating simulation code and commiling it?</h2> \n\
<h2 id=\"generating-simulation-code-and-commiling-it\">Generating simulation code and commiling it?</h2> \n\
<p>The first step is to create a DIPLODOCUS mapping. Once the mapping model has been checked against syntax errors <img src=\"file:../ui/util/checkmodel.gif\" alt=\"syntax checking icon\" />, it is possible to generate a C++ code <img src=\"file:../ui/util/gensystc.gif\" alt=\"simulation code generation icon\" /> that represents the mapping model. If you are using a model in TTool, then the code is generated by default in TTool/simulators/c++2 for models. If your model has been made in a project, then the code is generated into the \"c++_code\" subdirectory of your project.</p> \n\
<p>The first step is to create a DIPLODOCUS mapping. Once the mapping model has been checked against syntax errors <img src=\"file:../ui/util/checkmodel.gif\" alt=\"syntax checking icon\" />, it is possible to generate a C++ code <img src=\"file:../ui/util/gensystc.gif\" alt=\"simulation code generation icon\" /> that represents the mapping model. If you are using a model in TTool, then the code is generated by default in TTool/simulators/c++2 for models. If your model has been made in a project, then the code is generated into the “c++_code” subdirectory of your project.</p> \n\
<p>The second step is to compile the code. You can directly do it from TTool with the code generation window, second tab. Another option is to open a terminal, and to enter the following command:</p> \n\
<p>The second step is to compile the code. You can directly do it from TTool with the code generation window, second tab. Another option is to open a terminal, and to enter the following command:</p> \n\
<pre><code>$ make</code></pre> \n\
<pre><code>$ make</code></pre> \n\
<h2 id=\"using-the-simulator-from-ttool\">Using the simulator from TTool</h2> \n\
<h2 id=\"using-the-simulator-from-ttool\">Using the simulator from TTool</h2> \n\
...
@@ -482,7 +483,7 @@ Not defined: <unknow param></code></pre> \n\
...
@@ -482,7 +483,7 @@ Not defined: <unknow param></code></pre> \n\
<p>The simulator of DIPLODOCUS intends to simulate a DIPLODOCUS mapping, taking into account functional tasks, the system architectures (CPU, buses, etc.) and the allocations of tasks and their communucations to the system architecture</p>
<p>The simulator of DIPLODOCUS intends to simulate a DIPLODOCUS mapping, taking into account functional tasks, the system architectures (CPU, buses, etc.) and the allocations of tasks and their communucations to the system architecture</p>
<h2id="generating-simulation-code-and-commiling-it">Generating simulation code and commiling it?</h2>
<h2id="generating-simulation-code-and-commiling-it">Generating simulation code and commiling it?</h2>
<p>The first step is to create a DIPLODOCUS mapping. Once the mapping model has been checked against syntax errors <imgsrc="file:../ui/util/checkmodel.gif"alt="syntax checking icon"/>, it is possible to generate a C++ code <imgsrc="file:../ui/util/gensystc.gif"alt="simulation code generation icon"/> that represents the mapping model. If you are using a model in TTool, then the code is generated by default in TTool/simulators/c++2 for models. If your model has been made in a project, then the code is generated into the "c++_code" subdirectory of your project.</p>
<p>The first step is to create a DIPLODOCUS mapping. Once the mapping model has been checked against syntax errors <imgsrc="file:../ui/util/checkmodel.gif"alt="syntax checking icon"/>, it is possible to generate a C++ code <imgsrc="file:../ui/util/gensystc.gif"alt="simulation code generation icon"/> that represents the mapping model. If you are using a model in TTool, then the code is generated by default in TTool/simulators/c++2 for models. If your model has been made in a project, then the code is generated into the “c++_code” subdirectory of your project.</p>
<p>The second step is to compile the code. You can directly do it from TTool with the code generation window, second tab. Another option is to open a terminal, and to enter the following command:</p>
<p>The second step is to compile the code. You can directly do it from TTool with the code generation window, second tab. Another option is to open a terminal, and to enter the following command:</p>
<pre><code>$ make</code></pre>
<pre><code>$ make</code></pre>
<h2id="using-the-simulator-from-ttool">Using the simulator from TTool</h2>
<h2id="using-the-simulator-from-ttool">Using the simulator from TTool</h2>
...
@@ -481,7 +482,7 @@ Not defined: <unknow param></code></pre>
...
@@ -481,7 +482,7 @@ Not defined: <unknow param></code></pre>
@@ -86,7 +86,7 @@ run-x-time-units | rxtu | 1 6 | Runs the simulation for x units of time | [Type:
...
@@ -86,7 +86,7 @@ run-x-time-units | rxtu | 1 6 | Runs the simulation for x units of time | [Type:
run-x-transactions | rxtr | 1 2 | Runs the simulation for x transactions | [Type: 1] nb of transactions | - | - | - | -
run-x-transactions | rxtr | 1 2 | Runs the simulation for x transactions | [Type: 1] nb of transactions | - | - | - | -
save-simulation-state-in-file | sssif | 8 | Saves the current simulation state into a file | [Type: 2] File name | - | - | - | -
save-simulation-state-in-file | sssif | 8 | Saves the current simulation state into a file | [Type: 2] File name | - | - | - | -
save-trace-in-file | stif | 7 | Saves the current trace of the simulation in a VCD, HTML, TXT or XML file | [Type: 1] File format: 0-> VCD, 1->HTML, 2->TXT, 3->XML | [Type: 2] File name | - | - | -
save-trace-in-file | stif | 7 | Saves the current trace of the simulation in a VCD, HTML, TXT or XML file | [Type: 1] File format: 0-> VCD, 1->HTML, 2->TXT, 3->XML | [Type: 2] File name | - | - | -
show-timeline-trace | stlt | 7 4 | Show the current timeline diagram tracein HTML format | [Type: 2] Task List | [Type: 1] Scale idle time: 0 -> no, 1 -> yes | [Type: 2] Start Time | [Type: 2] End Time | -
show-timeline-trace | stlt | 7 4 | Show the current timeline diagram tracein HTML format | [Type: 2] Task List | [Type: 1] Scale idle time: 0 -> no, 1 -> yes | [Type: 2] Start Time | [Type: 2] End Time | -
set-variable | sv | 5 | Set the value of a variable | [Type: 1] task ID | [Type: 1] variable ID | [Type: 1] variable value | - | -
set-variable | sv | 5 | Set the value of a variable | [Type: 1] task ID | [Type: 1] variable ID | [Type: 1] variable value | - | -