From 94fbace22b2373db0381076b4b4674ea440f72ce Mon Sep 17 00:00:00 2001
From: Daniela Genius <genius@debussy.soc.lip6.fr>
Date: Tue, 5 Sep 2017 14:14:09 +0200
Subject: [PATCH] Virtual Coprocessors added for I/O
---
.../my_hwa0/caba/metadata/my_hwa0.sd | 25 +
.../my_hwa0/caba/source/include/my_hwa0.h | 25 +
.../caba/source/src/anoc_copro_wrapper.cpp | 658 ++++++++++++++++++
.../my_hwa0/caba/source/src/my_hwa0.cpp | 32 +
.../my_hwa1/caba/metadata/my_hwa0.sd | 25 +
.../my_hwa1/caba/metadata/my_hwa1.sd | 25 +
.../my_hwa1/caba/source/include/my_hwa0.h | 25 +
.../my_hwa1/caba/source/include/my_hwa1.h | 26 +
.../caba/source/src/anoc_copro_wrapper.cpp | 658 ++++++++++++++++++
.../my_hwa1/caba/source/src/my_hwa0.cpp | 32 +
.../my_hwa1/caba/source/src/my_hwa1.cpp | 31 +
.../ddtranslatorSoclib/AvatarCoproMWMR.java | 12 +-
.../java/ddtranslatorSoclib/AvatarDMA.java | 99 +++
.../java/ddtranslatorSoclib/AvatarTask.java | 4 +-
.../AvatarddSpecification.java | 17 +-
.../toTopCell/Declaration.java | 73 +-
.../ddtranslatorSoclib/toTopCell/Header.java | 15 +-
.../toTopCell/MappingTable.java | 35 +-
.../ddtranslatorSoclib/toTopCell/NetList.java | 37 +-
.../toTopCell/Platforminfo.java | 12 +-
.../ddtranslatorSoclib/toTopCell/Signal.java | 4 +-
.../ui/AvatarDeploymentPanelTranslator.java | 5 +-
22 files changed, 1800 insertions(+), 75 deletions(-)
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/anoc_copro_wrapper.cpp
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp
create mode 100644 MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp
create mode 100755 src/main/java/ddtranslatorSoclib/AvatarDMA.java
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd
new file mode 100644
index 0000000000..dfcbdc2e04
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd
@@ -0,0 +1,25 @@
+Module('caba:MyHWA0',
+ classname = 'dsx::caba::MyHWA0',
+ header_files = [
+ "my_hwa0.h",
+
+ ],
+ interface_files = [
+ ],
+ implementation_files = [
+ "my_hwa0.cpp",
+
+ ],
+ ports = [
+ ],
+ uses = [
+ Uses('caba:fifo_virtual_copro_wrapper'),
+ ],
+ instance_parameters = [
+ ],
+ tmpl_parameters = [
+ ],
+ extensions = [
+ ],
+)
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h
new file mode 100644
index 0000000000..4e1d1a14ed
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h
@@ -0,0 +1,25 @@
+#ifndef _HWA0_H
+#define _HWA0_H
+
+#include <systemc>
+
+#include "fifo_virtual_copro_wrapper.h"
+
+namespace dsx { namespace caba {
+
+class MyHWA0
+ : public dsx::caba::FifoVirtualCoprocessorWrapper
+{
+
+ public:
+ ~MyHWA0();
+ MyHWA0(sc_core::sc_module_name insname);
+
+
+ private:
+ void * task_func(); // Task code
+
+};
+
+}}
+#endif
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/anoc_copro_wrapper.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/anoc_copro_wrapper.cpp
new file mode 100644
index 0000000000..b4c4efdd6e
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/anoc_copro_wrapper.cpp
@@ -0,0 +1,658 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ *
+ * Copyright (c) CEA-LETI, MINATEC, 2008
+ *
+ * Authors :
+ *
+ * History :
+ *
+ * Comment :
+ *
+ */
+
+#include "anoc_copro_wrapper.h"
+namespace soclib { namespace caba {
+using soclib::common::alloc_elems;
+using soclib::common::dealloc_elems;
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Constructor
+anoc_copro_wrapper::anoc_copro_wrapper(sc_module_name module_name_,
+ t_uint16 nb_cores_,
+ t_uint16 nb_fifo_in_,
+ t_uint16 nb_fifo_out_,
+ t_uint16 n_config_,
+ t_uint16 n_status_,
+ t_uint32 clk_period_) :
+ sc_module(module_name_),
+ p_from_MWMR(alloc_elems<FifoInput<uint32_t> >("p_from_MWMR", nb_fifo_in_)),
+ p_to_MWMR(alloc_elems<FifoOutput<uint32_t> >("p_to_MWMR", nb_fifo_out_ )),
+ p_config(alloc_elems<sc_in<uint32_t> >("p_config", n_config_)),
+ p_status(alloc_elems<sc_out<uint32_t> >("p_status", n_status_)),
+ nb_cores(nb_cores_),
+ nb_fifo_in(nb_fifo_in_),
+ nb_fifo_out(nb_fifo_out_),
+ clk_period(clk_period_)
+{
+ core_fifo_in = new t_uint16[nb_fifo_in];
+ for(int i=0; i<nb_fifo_in; i++) {
+ if(nb_cores>1) {
+// core_fifo_in[i] = core_fifo_in_[i];
+ } else {
+ core_fifo_in[i] = 0; // monocore, core_fifo_in_=NULL
+ }
+ }
+ core_fifo_out = new t_uint16[nb_fifo_out];
+ for(int i=0; i<nb_fifo_out; i++) {
+ if(nb_cores>1) {
+// core_fifo_out[i] = core_fifo_out_[i];
+ } else {
+ core_fifo_out[i] = 0; // monocore, core_fifo_out_=NULL
+ }
+ }
+
+ cfg_flag_core_finished = new bool [nb_cores];
+ for(int i = 0; i < nb_cores; i++) {
+ cfg_flag_core_finished[i]=true;
+ }
+
+
+ // create ni => core ports
+#ifdef TLM_TRANS_RECORD
+ char port_in[80];
+ char port_out[80];
+ char port_debug[80];
+#endif
+ char port_out_name[80];
+ char port_in_name[80];
+
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_IN", basename());
+ sprintf(port_out,"%s_OUT", basename());
+ sprintf(port_debug,"%s_DEBUG", basename());
+#endif // TLM_TRANS_RECORD
+
+ ni_exec_out = new ni_exec_out_port*[nb_cores];
+ for(int i=0;i<nb_cores;i++) {
+ sprintf(port_out_name,"ni_exec_out_port_%i", i);
+ ni_exec_out[i] = new ni_exec_out_port((char *) port_out_name, "exec", "eoc");
+ ni_exec_out[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_cfg_dump_out = new ni_cfg_dump_out_port("ni_cfg_dump_out_port", "cfg_dump", "dump_data");
+ ni_cfg_dump_out->put_if_bind(*this); // for the status target sub-port
+
+
+ t_uint16 fifo_id[nb_cores];
+ for (int i=0; i<nb_cores; i++) {
+ fifo_id[i]=0;
+ }
+ ni_input_fifo_out = new ni_data_out_port*[nb_fifo_in];
+ for(int i=0;i<nb_fifo_in;i++) {
+ sprintf(port_out_name,"ni_input_fifo_out_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_out,"%s_input_fifo_out_%i", basename(), i);
+ ni_input_fifo_out[i] = new ni_data_out_port((char *) port_out_name, (char *)port_out, fifo_id[core_fifo_in[i]]);
+#else
+ ni_input_fifo_out[i] = new ni_data_out_port((char *) port_out_name, fifo_id[core_fifo_in[i]]);
+#endif // TLM_TRANS_RECORD
+ fifo_id[core_fifo_in[i]]++;
+ ni_input_fifo_out[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ // create core => ni ports
+ for (int i=0; i<nb_cores; i++) {
+ fifo_id[i]=0;
+ }
+ ni_output_fifo_in = new ni_data_in_port*[nb_fifo_out];
+ for(int i=0;i<nb_fifo_out;i++) {
+ sprintf(port_in_name,"ni_output_fifo_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_output_fifo_in_%i", basename(), i);
+ ni_output_fifo_in[i] = new ni_data_in_port((char *) port_in_name, (char *)port_in, fifo_id[core_fifo_out[i]]);
+#else
+ ni_output_fifo_in[i] = new ni_data_in_port((char *) port_in_name, fifo_id[core_fifo_out[i]]);
+#endif // TLM_TRANS_RECORD
+ fifo_id[core_fifo_out[i]]++;
+ ni_output_fifo_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_released_in = new ni_released_in_port*[nb_fifo_in];
+ for(int i=0;i<nb_fifo_in;i++) {
+ sprintf(port_in_name,"ni_released_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_released_in_%i", basename(), i);
+ ni_released_in[i] = new ni_released_in_port((char *) port_in_name, (char *)port_in);
+#else
+ ni_released_in[i] = new ni_released_in_port((char *) port_in_name);
+#endif // TLM_TRANS_RECORD
+ ni_released_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_available_in = new ni_available_in_port*[nb_fifo_out];
+ for(int i=0;i<nb_fifo_out;i++) {
+ sprintf(port_in_name,"ni_available_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_available_in_%i", basename(), i);
+ ni_available_in[i] = new ni_available_in_port((char *) port_in_name, (char *)port_in);
+#else
+ ni_available_in[i] = new ni_available_in_port((char *) port_in_name);
+#endif // TLM_TRANS_RECORD
+ ni_available_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_status_in = new ni_status_in_port*[nb_cores];
+ for(int i=0;i<nb_cores;i++) {
+ sprintf(port_in_name,"ni_status_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_status_in_%i", basename(), i);
+ ni_status_in[i] = new ni_status_in_port((char *) port_in_name, (char *)port_in);
+#else
+ ni_status_in[i] = new ni_status_in_port((char *) port_in_name);
+#endif // TLM_TRANS_RECORD
+ ni_status_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+
+ /***********************************************/
+ // internal programmation
+
+ /***********************************************/
+ // internal state variables
+
+ last_status = new t_uint32[nb_cores];
+ for(int i=0; i<nb_cores; i++) {
+ last_status[i] = 0;
+ }
+
+ tab_out_data_fifo_out = new t_uint32[nb_fifo_out];
+ flag_tab_out_data_fifo_out = new bool[nb_fifo_out];
+ tab_available_data_fifo_out = new t_uint32[nb_fifo_out];
+ for (int i = 0; i < nb_fifo_out; i++) {
+ tab_out_data_fifo_out[i] = 0;
+ flag_tab_out_data_fifo_out[i] = false;
+ tab_available_data_fifo_out[i]=0;
+ }
+ tab_fifo_in_accept = new bool[nb_fifo_in];
+ for (int i = 0; i < nb_fifo_in; i++) {
+ // fifo accept is initialised to true: ready to accept a new value
+ tab_fifo_in_accept[i] = true;
+ }
+
+
+ /***********************************************/
+ // threads & methods
+ SC_METHOD(rtl_to_tlm);
+ sensitive << rtl_to_tlm_event;
+ dont_initialize();
+
+ SC_METHOD(tlm_to_rtl);
+ sensitive << p_clk.neg();
+ dont_initialize();
+
+ EXPRINT(ni, 2,"anoc_copro_wrapper CREATED");
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Destructor
+anoc_copro_wrapper::~anoc_copro_wrapper() {
+
+ cout << "-------------- DELETE " << name() << " -------------- " << endl;
+
+
+
+ delete core_fifo_in;
+ delete core_fifo_out;
+ for(int i=0;i<nb_cores;i++) {
+ delete ni_exec_out[i];
+ }
+ delete ni_exec_out;
+ delete ni_cfg_dump_out;
+ for(int i=0;i<nb_fifo_in;i++) {
+ delete ni_input_fifo_out[i];
+ }
+ delete ni_input_fifo_out;
+ for(int i=0;i<nb_fifo_out;i++) {
+ delete ni_output_fifo_in[i];
+ }
+ delete ni_output_fifo_in;
+ for(int i=0;i<nb_fifo_in;i++) {
+ delete ni_released_in[i];
+ }
+ delete ni_released_in;
+ for(int i=0;i<nb_fifo_out;i++) {
+ delete ni_available_in[i];
+ }
+ delete ni_available_in;
+ for(int i=0;i<nb_cores;i++) {
+ delete ni_status_in[i];
+ }
+ delete ni_status_in;
+
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive DUMP DATA transaction (remote call)
+void anoc_copro_wrapper::put(const ni_dump_data_transaction &transaction) {
+ //Not yet implemented
+#ifdef _ANOC_COPRO_DEBUG
+ printf("DUMP DATA transaction\n");
+#endif
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive RELEASED transaction (remote call)
+void anoc_copro_wrapper::put(const ni_released_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("RELEASED transaction\n");
+#endif
+ t_uint16 fifo_id = 0;
+ t_uint16 source_id;
+ t_uint16 core_id;
+ t_uint32 size_released;
+ bool fifo_ok = false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+ size_released = transaction.get_data();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_in; i++) {
+ if(core_fifo_in[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive released ("<< size_released <<") from fifo: " << fifo_id);
+// tab_available_size_fifo_in[fifo_id]+=size_released;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for released from CORE " << core_id);
+ exit(0);
+ }
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive AVAILABLE transaction (remote call)
+void anoc_copro_wrapper::put(const ni_available_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("AVAILABLE transaction\n");
+#endif
+ t_uint16 fifo_id = 0;
+ t_uint16 source_id;
+ t_uint16 core_id;
+ t_uint32 available_data;
+ bool fifo_ok = false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+ available_data = transaction.get_data();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_out; i++) {
+ if(core_fifo_out[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive available (" << available_data << ") from fifo: " << fifo_id);
+ tab_available_data_fifo_out[fifo_id] = available_data;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for avaivable from CORE " << core_id);
+ exit(0);
+ }
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive WRITE DATA transaction (remote call)
+void anoc_copro_wrapper::put(const ni_write_data_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("Received DATA transaction\n");
+#endif
+
+ t_uint16 fifo_id = 0;
+ t_uint16 source_id;
+ t_uint16 core_id;
+ t_uint32 data;
+ bool fifo_ok = false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+ data = transaction.get_data();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_out; i++) {
+ if(core_fifo_out[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive write data: " << data << " from fifo: " << fifo_id);
+ tab_out_data_fifo_out[fifo_id] = data;
+ flag_tab_out_data_fifo_out[fifo_id] = true;
+ //Requires a data update on the RTL ports
+ write_data_update = true;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for write data from CORE " << core_id);
+ exit(0);
+ }
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Write DATA ACCEPT transaction for fifo out
+void anoc_copro_wrapper::write_data_accept_fifo_out(int num_fifo) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("DATA ACCEPT transaction\n");
+#endif
+ ni_accept_data_transaction accept_trans;
+ ni_output_fifo_in[num_fifo]->put(&accept_trans);
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive ACCEPT DATA transaction (remote call)
+void anoc_copro_wrapper::put(const ni_accept_data_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("ACCEPT DATA transaction\n");
+#endif
+ t_uint16 source_id;
+ t_uint16 fifo_id = 0;
+ t_uint16 core_id;
+ bool fifo_ok=false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_in; i++) {
+ if(core_fifo_in[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive accept data from fifo: " << fifo_id); //FIXPRINT
+ tab_fifo_in_accept[fifo_id] = true;
+ //Requires to update the accept_data (Ivan)
+ accept_data_update = true;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for accept data from CORE " << core_id );
+ exit(0);
+ }
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Write WRITE DATA transaction for fifo in
+void anoc_copro_wrapper::write_data_fifo_in(int num_fifo, t_uint32 data) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("WRITE DATA transaction\n");
+#endif
+
+ ni_write_data_transaction data_trans;
+ data_trans.set_data(data);
+ EXPRINT(ni, 1,"Write data " << data << " in fifo_in[" << num_fifo << "]"); //FIXPRINT
+ ni_input_fifo_out[num_fifo]->put(&data_trans);
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive STATUS transaction (remote call)
+void anoc_copro_wrapper::put(const ni_status_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("STATUS transaction\n");
+#endif
+
+ t_uint16 core_id;
+ core_id = transaction.get_core_id();
+ if(core_id>=nb_cores) {
+ EXPRINT(ni, 0,"ERROR : Invalid core id for status");
+ exit(0);
+ }
+
+ last_status[core_id] = transaction.get_status();
+ //Requires to update the status port
+ status_update = true;
+
+ EXPRINT(ni, 0,"New status from CORE " << core_id <<" : " << last_status[core_id]); //FIXPRINT
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive EOC transaction (remote call)
+void anoc_copro_wrapper::put(const ni_eoc_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("EOC transaction\n");
+#endif
+
+ t_uint16 core_id;
+ core_id = transaction.get_core_id();
+ if(core_id>=nb_cores) {
+ EXPRINT(ni, 0,"ERROR : Invalid core_id for eoc");
+ exit(0);
+ }
+
+ EXPRINT(ni, 0,"CORE " << core_id << " has finished"); //FIXPRINT
+ cfg_flag_core_finished[core_id] = true;
+ //Requires to update the eoc
+ eoc_update = true;
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+// Update the RTL signals when a TLM transcation arrive
+/// Sensitive_neg << p_clk
+void anoc_copro_wrapper::tlm_to_rtl() {
+ //Output FIFOs
+ //////////////
+ // The Data port need to be updated ?
+// if (write_data_update == true) {
+// printf("write_data_update, %i\n",(int)flag_tab_out_data_fifo_out[0]);
+// for(int i=0; i<nb_fifo_out; i++) {
+// p_to_MWMR[i].w = flag_tab_out_data_fifo_out[i];
+// p_to_MWMR[i].data = tab_out_data_fifo_out[i];
+// }
+// //the Data is correctly updated
+// write_data_update = false;
+// }
+ //Input FIFOs
+ /////////////
+ // The Accept port need to be updated ?
+// if (accept_data_update == true) {
+// for(int i=0; i<nb_fifo_in; i++) {
+// p_from_MWMR[i].r = tab_fifo_in_accept[i];
+// }
+// //the Data is correctly updated
+// accept_data_update = false;
+// }
+ //Status port
+ /////////////
+ // The Accept port need to be updated ?
+ if (status_update == true) {
+ for (int i=0; i<nb_cores; i++) {
+ p_status[i+1] = last_status[i];
+ }
+ status_update = false;
+ }
+ //EOC port
+ /////////////
+ if (eoc_update == true) {
+ uint32_t value = 0;
+ for (int i=0; i<nb_cores; i++) {
+ if (cfg_flag_core_finished[i] == true) {
+ value += 1 << i;
+ }
+ }
+ p_status[0] = value;
+ eoc_update = false;
+ }
+
+ //Core configuration
+ ////////////////////
+ p_core_config.r = true;
+
+ //Start the rtl_to_tlm process
+ rtl_to_tlm_event.notify(clk_period/4,SC_PS);
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+// Generate a TLM transaction when the RTL signals change
+/// Sensitive_pos << 3/4*p_clk
+void anoc_copro_wrapper::rtl_to_tlm() {
+
+ //Output FIFOs
+ //////////////
+ //Test if a Send signal is active
+ for(int i=0; i<nb_fifo_out; i++) {
+ //A FIFO was ready to send data ?
+ p_to_MWMR[i].w = false;
+ if (flag_tab_out_data_fifo_out[i]) {
+ //Chech if the accept signal is High
+ if (p_to_MWMR[i].wok.read() == true) {
+ //The FIFO data is correcly transfered
+ p_to_MWMR[i].w = true;
+ p_to_MWMR[i].data = tab_out_data_fifo_out[i];
+
+ //Invalidate the send signal
+ flag_tab_out_data_fifo_out[i] = false;
+ //Requires to update the Data port
+ write_data_update = true;
+ //Send the TLM Accept transaction to the Core
+ if (tab_available_data_fifo_out[i] > 1 )
+ write_data_accept_fifo_out(i);
+ }
+ } else if (tab_available_data_fifo_out[i] > 0 ) {
+ //New data can be read?
+ //Send the TLM Accept transaction to the Core
+ write_data_accept_fifo_out(i);
+ }
+ }
+
+ //Input FIFOs
+ /////////////
+ //Test if a new Data is present on the Input FIFOs
+ for(int i=0; i<nb_fifo_in; i++) {
+ p_from_MWMR[i].r = tab_fifo_in_accept[i];
+ if (p_from_MWMR[i].rok.read() == true) {
+ //I am ready to accept this new data?
+ if (tab_fifo_in_accept[i] == true) {
+ //Read the data and send a TLM transcation
+ p_from_MWMR[i].r = true;
+ t_uint32 data = (t_uint32)p_from_MWMR[i].data.read();
+ write_data_fifo_in(i, data);
+ //Lower the ROK signal
+ tab_fifo_in_accept[i] = false;
+ //Requires a Accept RTL port update
+ accept_data_update = true;
+ }
+ }
+ }
+
+ //Exec port
+ ///////////////
+ //RTL signals changed?
+ if (exec_last != p_config[0].read()) {
+ ni_exec_transaction exec_trans;
+ //Test bit by bit to identify the source
+ for(int i=0; i<nb_cores; i++) {
+ if (((exec_last & (1<<i)) == 0) && ((p_config[0].read() & (1<<i)) == 1)) {
+ //A new lot_id is ready to be executed on core 'i'
+ EXPRINT(ni, 1,"CORE configuration event");
+ //Get the slot_id
+ t_uint16 slot_id = (t_uint16)p_config[i+1].read();
+ EXPRINT(ni, 0,"CORE " << i << " execute configuration on slot id " << slot_id);
+ // write exec config
+ exec_trans.set_slot_id(slot_id);
+ ni_exec_out[i]->put(&exec_trans);
+ //The CORE is nolonger finished
+ cfg_flag_core_finished[i] = false;
+ //Requires a RTL signal update
+ eoc_update = true;
+ }
+ }
+ exec_last = p_config[0].read();
+ }
+
+ //Core config address
+ /////////////////////
+ if (last_address != p_config[5].read()) {
+ //The address have been changed
+ current_address = p_config[5].read();
+ last_address = p_config[5].read();
+ }
+
+
+ //Core configuration
+ ////////////////////
+ if (p_core_config.rok.read() == true) {
+ //A new configuration data is ready
+ ni_cfg_transaction cfg_trans;
+ t_uint32 data = p_core_config.data.read();
+ cfg_trans.set_data(data);
+ cfg_trans.set_address(current_address);
+#ifdef _ANOC_COPRO_DEBUG
+ printf("Ivan: Config data: %.8x on address %.8x\n", data, current_address);
+#endif
+ ni_cfg_dump_out->put(&cfg_trans);
+ current_address++;
+ }
+
+}
+}}
+
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp
new file mode 100644
index 0000000000..20c731c9d5
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp
@@ -0,0 +1,32 @@
+
+namespace dsx { namespace caba {
+
+
+#define tmpl(...) __VA_ARGS__ MyHWA0
+
+tmpl(/**/)::~MyHWA0()
+{
+}
+
+ //intArray(1,1) there is one element (here an integer) of size 4 OCTETs/Quentin: attention cela a change c'est un MOT dans la version VM
+tmpl(/**/)::MyHWA0(sc_core::sc_module_name insname)
+ :dsx::caba::FifoVirtualCoprocessorWrapper(insname, stringArray("output", NULL), intArray(1,4), stringArray(NULL), NULL)
+{
+}
+
+tmpl(void *)::task_func() {
+ struct mwmr_s *output;
+// mwmr_t output = SRL_GET_MWMR(output);
+ uint32_t data;
+
+ while (true) {
+ for (int32_t i = 0; i < 8; i++) {
+ out=i;
+ mwmr_write(output, &data, 4; // Write integers 0 to 7 to output
+ }
+
+ }
+}
+
+}}
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd
new file mode 100644
index 0000000000..dfcbdc2e04
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd
@@ -0,0 +1,25 @@
+Module('caba:MyHWA0',
+ classname = 'dsx::caba::MyHWA0',
+ header_files = [
+ "my_hwa0.h",
+
+ ],
+ interface_files = [
+ ],
+ implementation_files = [
+ "my_hwa0.cpp",
+
+ ],
+ ports = [
+ ],
+ uses = [
+ Uses('caba:fifo_virtual_copro_wrapper'),
+ ],
+ instance_parameters = [
+ ],
+ tmpl_parameters = [
+ ],
+ extensions = [
+ ],
+)
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd
new file mode 100644
index 0000000000..b0b32c5d02
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd
@@ -0,0 +1,25 @@
+Module('caba:MyHWA1',
+ classname = 'dsx::caba::MyHWA1',
+ header_files = [
+ "my_hwa1.h",
+
+ ],
+ interface_files = [
+ ],
+ implementation_files = [
+ "my_hwa1.cpp",
+
+ ],
+ ports = [
+ ],
+ uses = [
+ Uses('caba:fifo_virtual_copro_wrapper'),
+ ],
+ instance_parameters = [
+ ],
+ tmpl_parameters = [
+ ],
+ extensions = [
+ ],
+)
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h
new file mode 100644
index 0000000000..4e1d1a14ed
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h
@@ -0,0 +1,25 @@
+#ifndef _HWA0_H
+#define _HWA0_H
+
+#include <systemc>
+
+#include "fifo_virtual_copro_wrapper.h"
+
+namespace dsx { namespace caba {
+
+class MyHWA0
+ : public dsx::caba::FifoVirtualCoprocessorWrapper
+{
+
+ public:
+ ~MyHWA0();
+ MyHWA0(sc_core::sc_module_name insname);
+
+
+ private:
+ void * task_func(); // Task code
+
+};
+
+}}
+#endif
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h
new file mode 100644
index 0000000000..785ede2fc5
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h
@@ -0,0 +1,26 @@
+#ifndef _HWA1_H
+#define _HWA1_H
+
+#include <systemc>
+
+#include "fifo_virtual_copro_wrapper.h"
+
+namespace dsx { namespace caba {
+
+class MyHWA1
+ : public dsx::caba::FifoVirtualCoprocessorWrapper
+{
+
+ public:
+ ~MyHWA1();
+ MyHWA1(sc_core::sc_module_name insname);
+
+
+ private:
+ void * task_func(); // Task code
+
+};
+
+}}
+#endif
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp
new file mode 100644
index 0000000000..b4c4efdd6e
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp
@@ -0,0 +1,658 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ *
+ * Copyright (c) CEA-LETI, MINATEC, 2008
+ *
+ * Authors :
+ *
+ * History :
+ *
+ * Comment :
+ *
+ */
+
+#include "anoc_copro_wrapper.h"
+namespace soclib { namespace caba {
+using soclib::common::alloc_elems;
+using soclib::common::dealloc_elems;
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Constructor
+anoc_copro_wrapper::anoc_copro_wrapper(sc_module_name module_name_,
+ t_uint16 nb_cores_,
+ t_uint16 nb_fifo_in_,
+ t_uint16 nb_fifo_out_,
+ t_uint16 n_config_,
+ t_uint16 n_status_,
+ t_uint32 clk_period_) :
+ sc_module(module_name_),
+ p_from_MWMR(alloc_elems<FifoInput<uint32_t> >("p_from_MWMR", nb_fifo_in_)),
+ p_to_MWMR(alloc_elems<FifoOutput<uint32_t> >("p_to_MWMR", nb_fifo_out_ )),
+ p_config(alloc_elems<sc_in<uint32_t> >("p_config", n_config_)),
+ p_status(alloc_elems<sc_out<uint32_t> >("p_status", n_status_)),
+ nb_cores(nb_cores_),
+ nb_fifo_in(nb_fifo_in_),
+ nb_fifo_out(nb_fifo_out_),
+ clk_period(clk_period_)
+{
+ core_fifo_in = new t_uint16[nb_fifo_in];
+ for(int i=0; i<nb_fifo_in; i++) {
+ if(nb_cores>1) {
+// core_fifo_in[i] = core_fifo_in_[i];
+ } else {
+ core_fifo_in[i] = 0; // monocore, core_fifo_in_=NULL
+ }
+ }
+ core_fifo_out = new t_uint16[nb_fifo_out];
+ for(int i=0; i<nb_fifo_out; i++) {
+ if(nb_cores>1) {
+// core_fifo_out[i] = core_fifo_out_[i];
+ } else {
+ core_fifo_out[i] = 0; // monocore, core_fifo_out_=NULL
+ }
+ }
+
+ cfg_flag_core_finished = new bool [nb_cores];
+ for(int i = 0; i < nb_cores; i++) {
+ cfg_flag_core_finished[i]=true;
+ }
+
+
+ // create ni => core ports
+#ifdef TLM_TRANS_RECORD
+ char port_in[80];
+ char port_out[80];
+ char port_debug[80];
+#endif
+ char port_out_name[80];
+ char port_in_name[80];
+
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_IN", basename());
+ sprintf(port_out,"%s_OUT", basename());
+ sprintf(port_debug,"%s_DEBUG", basename());
+#endif // TLM_TRANS_RECORD
+
+ ni_exec_out = new ni_exec_out_port*[nb_cores];
+ for(int i=0;i<nb_cores;i++) {
+ sprintf(port_out_name,"ni_exec_out_port_%i", i);
+ ni_exec_out[i] = new ni_exec_out_port((char *) port_out_name, "exec", "eoc");
+ ni_exec_out[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_cfg_dump_out = new ni_cfg_dump_out_port("ni_cfg_dump_out_port", "cfg_dump", "dump_data");
+ ni_cfg_dump_out->put_if_bind(*this); // for the status target sub-port
+
+
+ t_uint16 fifo_id[nb_cores];
+ for (int i=0; i<nb_cores; i++) {
+ fifo_id[i]=0;
+ }
+ ni_input_fifo_out = new ni_data_out_port*[nb_fifo_in];
+ for(int i=0;i<nb_fifo_in;i++) {
+ sprintf(port_out_name,"ni_input_fifo_out_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_out,"%s_input_fifo_out_%i", basename(), i);
+ ni_input_fifo_out[i] = new ni_data_out_port((char *) port_out_name, (char *)port_out, fifo_id[core_fifo_in[i]]);
+#else
+ ni_input_fifo_out[i] = new ni_data_out_port((char *) port_out_name, fifo_id[core_fifo_in[i]]);
+#endif // TLM_TRANS_RECORD
+ fifo_id[core_fifo_in[i]]++;
+ ni_input_fifo_out[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ // create core => ni ports
+ for (int i=0; i<nb_cores; i++) {
+ fifo_id[i]=0;
+ }
+ ni_output_fifo_in = new ni_data_in_port*[nb_fifo_out];
+ for(int i=0;i<nb_fifo_out;i++) {
+ sprintf(port_in_name,"ni_output_fifo_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_output_fifo_in_%i", basename(), i);
+ ni_output_fifo_in[i] = new ni_data_in_port((char *) port_in_name, (char *)port_in, fifo_id[core_fifo_out[i]]);
+#else
+ ni_output_fifo_in[i] = new ni_data_in_port((char *) port_in_name, fifo_id[core_fifo_out[i]]);
+#endif // TLM_TRANS_RECORD
+ fifo_id[core_fifo_out[i]]++;
+ ni_output_fifo_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_released_in = new ni_released_in_port*[nb_fifo_in];
+ for(int i=0;i<nb_fifo_in;i++) {
+ sprintf(port_in_name,"ni_released_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_released_in_%i", basename(), i);
+ ni_released_in[i] = new ni_released_in_port((char *) port_in_name, (char *)port_in);
+#else
+ ni_released_in[i] = new ni_released_in_port((char *) port_in_name);
+#endif // TLM_TRANS_RECORD
+ ni_released_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_available_in = new ni_available_in_port*[nb_fifo_out];
+ for(int i=0;i<nb_fifo_out;i++) {
+ sprintf(port_in_name,"ni_available_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_available_in_%i", basename(), i);
+ ni_available_in[i] = new ni_available_in_port((char *) port_in_name, (char *)port_in);
+#else
+ ni_available_in[i] = new ni_available_in_port((char *) port_in_name);
+#endif // TLM_TRANS_RECORD
+ ni_available_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+ ni_status_in = new ni_status_in_port*[nb_cores];
+ for(int i=0;i<nb_cores;i++) {
+ sprintf(port_in_name,"ni_status_in_port_%i", i);
+#ifdef TLM_TRANS_RECORD
+ sprintf(port_in,"%s_status_in_%i", basename(), i);
+ ni_status_in[i] = new ni_status_in_port((char *) port_in_name, (char *)port_in);
+#else
+ ni_status_in[i] = new ni_status_in_port((char *) port_in_name);
+#endif // TLM_TRANS_RECORD
+ ni_status_in[i]->put_if_bind(*this); // for the status target sub-port
+ }
+
+
+ /***********************************************/
+ // internal programmation
+
+ /***********************************************/
+ // internal state variables
+
+ last_status = new t_uint32[nb_cores];
+ for(int i=0; i<nb_cores; i++) {
+ last_status[i] = 0;
+ }
+
+ tab_out_data_fifo_out = new t_uint32[nb_fifo_out];
+ flag_tab_out_data_fifo_out = new bool[nb_fifo_out];
+ tab_available_data_fifo_out = new t_uint32[nb_fifo_out];
+ for (int i = 0; i < nb_fifo_out; i++) {
+ tab_out_data_fifo_out[i] = 0;
+ flag_tab_out_data_fifo_out[i] = false;
+ tab_available_data_fifo_out[i]=0;
+ }
+ tab_fifo_in_accept = new bool[nb_fifo_in];
+ for (int i = 0; i < nb_fifo_in; i++) {
+ // fifo accept is initialised to true: ready to accept a new value
+ tab_fifo_in_accept[i] = true;
+ }
+
+
+ /***********************************************/
+ // threads & methods
+ SC_METHOD(rtl_to_tlm);
+ sensitive << rtl_to_tlm_event;
+ dont_initialize();
+
+ SC_METHOD(tlm_to_rtl);
+ sensitive << p_clk.neg();
+ dont_initialize();
+
+ EXPRINT(ni, 2,"anoc_copro_wrapper CREATED");
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Destructor
+anoc_copro_wrapper::~anoc_copro_wrapper() {
+
+ cout << "-------------- DELETE " << name() << " -------------- " << endl;
+
+
+
+ delete core_fifo_in;
+ delete core_fifo_out;
+ for(int i=0;i<nb_cores;i++) {
+ delete ni_exec_out[i];
+ }
+ delete ni_exec_out;
+ delete ni_cfg_dump_out;
+ for(int i=0;i<nb_fifo_in;i++) {
+ delete ni_input_fifo_out[i];
+ }
+ delete ni_input_fifo_out;
+ for(int i=0;i<nb_fifo_out;i++) {
+ delete ni_output_fifo_in[i];
+ }
+ delete ni_output_fifo_in;
+ for(int i=0;i<nb_fifo_in;i++) {
+ delete ni_released_in[i];
+ }
+ delete ni_released_in;
+ for(int i=0;i<nb_fifo_out;i++) {
+ delete ni_available_in[i];
+ }
+ delete ni_available_in;
+ for(int i=0;i<nb_cores;i++) {
+ delete ni_status_in[i];
+ }
+ delete ni_status_in;
+
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive DUMP DATA transaction (remote call)
+void anoc_copro_wrapper::put(const ni_dump_data_transaction &transaction) {
+ //Not yet implemented
+#ifdef _ANOC_COPRO_DEBUG
+ printf("DUMP DATA transaction\n");
+#endif
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive RELEASED transaction (remote call)
+void anoc_copro_wrapper::put(const ni_released_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("RELEASED transaction\n");
+#endif
+ t_uint16 fifo_id = 0;
+ t_uint16 source_id;
+ t_uint16 core_id;
+ t_uint32 size_released;
+ bool fifo_ok = false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+ size_released = transaction.get_data();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_in; i++) {
+ if(core_fifo_in[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive released ("<< size_released <<") from fifo: " << fifo_id);
+// tab_available_size_fifo_in[fifo_id]+=size_released;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for released from CORE " << core_id);
+ exit(0);
+ }
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive AVAILABLE transaction (remote call)
+void anoc_copro_wrapper::put(const ni_available_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("AVAILABLE transaction\n");
+#endif
+ t_uint16 fifo_id = 0;
+ t_uint16 source_id;
+ t_uint16 core_id;
+ t_uint32 available_data;
+ bool fifo_ok = false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+ available_data = transaction.get_data();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_out; i++) {
+ if(core_fifo_out[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive available (" << available_data << ") from fifo: " << fifo_id);
+ tab_available_data_fifo_out[fifo_id] = available_data;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for avaivable from CORE " << core_id);
+ exit(0);
+ }
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive WRITE DATA transaction (remote call)
+void anoc_copro_wrapper::put(const ni_write_data_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("Received DATA transaction\n");
+#endif
+
+ t_uint16 fifo_id = 0;
+ t_uint16 source_id;
+ t_uint16 core_id;
+ t_uint32 data;
+ bool fifo_ok = false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+ data = transaction.get_data();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_out; i++) {
+ if(core_fifo_out[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive write data: " << data << " from fifo: " << fifo_id);
+ tab_out_data_fifo_out[fifo_id] = data;
+ flag_tab_out_data_fifo_out[fifo_id] = true;
+ //Requires a data update on the RTL ports
+ write_data_update = true;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for write data from CORE " << core_id);
+ exit(0);
+ }
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Write DATA ACCEPT transaction for fifo out
+void anoc_copro_wrapper::write_data_accept_fifo_out(int num_fifo) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("DATA ACCEPT transaction\n");
+#endif
+ ni_accept_data_transaction accept_trans;
+ ni_output_fifo_in[num_fifo]->put(&accept_trans);
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive ACCEPT DATA transaction (remote call)
+void anoc_copro_wrapper::put(const ni_accept_data_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("ACCEPT DATA transaction\n");
+#endif
+ t_uint16 source_id;
+ t_uint16 fifo_id = 0;
+ t_uint16 core_id;
+ bool fifo_ok=false;
+
+ source_id = transaction.get_source_id();
+ core_id = transaction.get_core_id();
+
+ int j=0;
+ for(int i=0; i<nb_fifo_in; i++) {
+ if(core_fifo_in[i]==core_id) {
+ if(j==source_id) {
+ fifo_id = i;
+ fifo_ok=true;
+ }
+ j++;
+ }
+ }
+
+ if(fifo_ok) {
+ EXPRINT(ni, 1,"Receive accept data from fifo: " << fifo_id); //FIXPRINT
+ tab_fifo_in_accept[fifo_id] = true;
+ //Requires to update the accept_data (Ivan)
+ accept_data_update = true;
+ } else {
+ EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for accept data from CORE " << core_id );
+ exit(0);
+ }
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Write WRITE DATA transaction for fifo in
+void anoc_copro_wrapper::write_data_fifo_in(int num_fifo, t_uint32 data) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("WRITE DATA transaction\n");
+#endif
+
+ ni_write_data_transaction data_trans;
+ data_trans.set_data(data);
+ EXPRINT(ni, 1,"Write data " << data << " in fifo_in[" << num_fifo << "]"); //FIXPRINT
+ ni_input_fifo_out[num_fifo]->put(&data_trans);
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive STATUS transaction (remote call)
+void anoc_copro_wrapper::put(const ni_status_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("STATUS transaction\n");
+#endif
+
+ t_uint16 core_id;
+ core_id = transaction.get_core_id();
+ if(core_id>=nb_cores) {
+ EXPRINT(ni, 0,"ERROR : Invalid core id for status");
+ exit(0);
+ }
+
+ last_status[core_id] = transaction.get_status();
+ //Requires to update the status port
+ status_update = true;
+
+ EXPRINT(ni, 0,"New status from CORE " << core_id <<" : " << last_status[core_id]); //FIXPRINT
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+/// Receive EOC transaction (remote call)
+void anoc_copro_wrapper::put(const ni_eoc_transaction &transaction) {
+#ifdef _ANOC_COPRO_DEBUG
+ printf("EOC transaction\n");
+#endif
+
+ t_uint16 core_id;
+ core_id = transaction.get_core_id();
+ if(core_id>=nb_cores) {
+ EXPRINT(ni, 0,"ERROR : Invalid core_id for eoc");
+ exit(0);
+ }
+
+ EXPRINT(ni, 0,"CORE " << core_id << " has finished"); //FIXPRINT
+ cfg_flag_core_finished[core_id] = true;
+ //Requires to update the eoc
+ eoc_update = true;
+
+}
+
+/*******************************************************************************/
+/*******************************************************************************/
+// Update the RTL signals when a TLM transcation arrive
+/// Sensitive_neg << p_clk
+void anoc_copro_wrapper::tlm_to_rtl() {
+ //Output FIFOs
+ //////////////
+ // The Data port need to be updated ?
+// if (write_data_update == true) {
+// printf("write_data_update, %i\n",(int)flag_tab_out_data_fifo_out[0]);
+// for(int i=0; i<nb_fifo_out; i++) {
+// p_to_MWMR[i].w = flag_tab_out_data_fifo_out[i];
+// p_to_MWMR[i].data = tab_out_data_fifo_out[i];
+// }
+// //the Data is correctly updated
+// write_data_update = false;
+// }
+ //Input FIFOs
+ /////////////
+ // The Accept port need to be updated ?
+// if (accept_data_update == true) {
+// for(int i=0; i<nb_fifo_in; i++) {
+// p_from_MWMR[i].r = tab_fifo_in_accept[i];
+// }
+// //the Data is correctly updated
+// accept_data_update = false;
+// }
+ //Status port
+ /////////////
+ // The Accept port need to be updated ?
+ if (status_update == true) {
+ for (int i=0; i<nb_cores; i++) {
+ p_status[i+1] = last_status[i];
+ }
+ status_update = false;
+ }
+ //EOC port
+ /////////////
+ if (eoc_update == true) {
+ uint32_t value = 0;
+ for (int i=0; i<nb_cores; i++) {
+ if (cfg_flag_core_finished[i] == true) {
+ value += 1 << i;
+ }
+ }
+ p_status[0] = value;
+ eoc_update = false;
+ }
+
+ //Core configuration
+ ////////////////////
+ p_core_config.r = true;
+
+ //Start the rtl_to_tlm process
+ rtl_to_tlm_event.notify(clk_period/4,SC_PS);
+}
+
+
+/*******************************************************************************/
+/*******************************************************************************/
+// Generate a TLM transaction when the RTL signals change
+/// Sensitive_pos << 3/4*p_clk
+void anoc_copro_wrapper::rtl_to_tlm() {
+
+ //Output FIFOs
+ //////////////
+ //Test if a Send signal is active
+ for(int i=0; i<nb_fifo_out; i++) {
+ //A FIFO was ready to send data ?
+ p_to_MWMR[i].w = false;
+ if (flag_tab_out_data_fifo_out[i]) {
+ //Chech if the accept signal is High
+ if (p_to_MWMR[i].wok.read() == true) {
+ //The FIFO data is correcly transfered
+ p_to_MWMR[i].w = true;
+ p_to_MWMR[i].data = tab_out_data_fifo_out[i];
+
+ //Invalidate the send signal
+ flag_tab_out_data_fifo_out[i] = false;
+ //Requires to update the Data port
+ write_data_update = true;
+ //Send the TLM Accept transaction to the Core
+ if (tab_available_data_fifo_out[i] > 1 )
+ write_data_accept_fifo_out(i);
+ }
+ } else if (tab_available_data_fifo_out[i] > 0 ) {
+ //New data can be read?
+ //Send the TLM Accept transaction to the Core
+ write_data_accept_fifo_out(i);
+ }
+ }
+
+ //Input FIFOs
+ /////////////
+ //Test if a new Data is present on the Input FIFOs
+ for(int i=0; i<nb_fifo_in; i++) {
+ p_from_MWMR[i].r = tab_fifo_in_accept[i];
+ if (p_from_MWMR[i].rok.read() == true) {
+ //I am ready to accept this new data?
+ if (tab_fifo_in_accept[i] == true) {
+ //Read the data and send a TLM transcation
+ p_from_MWMR[i].r = true;
+ t_uint32 data = (t_uint32)p_from_MWMR[i].data.read();
+ write_data_fifo_in(i, data);
+ //Lower the ROK signal
+ tab_fifo_in_accept[i] = false;
+ //Requires a Accept RTL port update
+ accept_data_update = true;
+ }
+ }
+ }
+
+ //Exec port
+ ///////////////
+ //RTL signals changed?
+ if (exec_last != p_config[0].read()) {
+ ni_exec_transaction exec_trans;
+ //Test bit by bit to identify the source
+ for(int i=0; i<nb_cores; i++) {
+ if (((exec_last & (1<<i)) == 0) && ((p_config[0].read() & (1<<i)) == 1)) {
+ //A new lot_id is ready to be executed on core 'i'
+ EXPRINT(ni, 1,"CORE configuration event");
+ //Get the slot_id
+ t_uint16 slot_id = (t_uint16)p_config[i+1].read();
+ EXPRINT(ni, 0,"CORE " << i << " execute configuration on slot id " << slot_id);
+ // write exec config
+ exec_trans.set_slot_id(slot_id);
+ ni_exec_out[i]->put(&exec_trans);
+ //The CORE is nolonger finished
+ cfg_flag_core_finished[i] = false;
+ //Requires a RTL signal update
+ eoc_update = true;
+ }
+ }
+ exec_last = p_config[0].read();
+ }
+
+ //Core config address
+ /////////////////////
+ if (last_address != p_config[5].read()) {
+ //The address have been changed
+ current_address = p_config[5].read();
+ last_address = p_config[5].read();
+ }
+
+
+ //Core configuration
+ ////////////////////
+ if (p_core_config.rok.read() == true) {
+ //A new configuration data is ready
+ ni_cfg_transaction cfg_trans;
+ t_uint32 data = p_core_config.data.read();
+ cfg_trans.set_data(data);
+ cfg_trans.set_address(current_address);
+#ifdef _ANOC_COPRO_DEBUG
+ printf("Ivan: Config data: %.8x on address %.8x\n", data, current_address);
+#endif
+ ni_cfg_dump_out->put(&cfg_trans);
+ current_address++;
+ }
+
+}
+}}
+
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp
new file mode 100644
index 0000000000..20c731c9d5
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp
@@ -0,0 +1,32 @@
+
+namespace dsx { namespace caba {
+
+
+#define tmpl(...) __VA_ARGS__ MyHWA0
+
+tmpl(/**/)::~MyHWA0()
+{
+}
+
+ //intArray(1,1) there is one element (here an integer) of size 4 OCTETs/Quentin: attention cela a change c'est un MOT dans la version VM
+tmpl(/**/)::MyHWA0(sc_core::sc_module_name insname)
+ :dsx::caba::FifoVirtualCoprocessorWrapper(insname, stringArray("output", NULL), intArray(1,4), stringArray(NULL), NULL)
+{
+}
+
+tmpl(void *)::task_func() {
+ struct mwmr_s *output;
+// mwmr_t output = SRL_GET_MWMR(output);
+ uint32_t data;
+
+ while (true) {
+ for (int32_t i = 0; i < 8; i++) {
+ out=i;
+ mwmr_write(output, &data, 4; // Write integers 0 to 7 to output
+ }
+
+ }
+}
+
+}}
+
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp
new file mode 100644
index 0000000000..b6ba89a325
--- /dev/null
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp
@@ -0,0 +1,31 @@
+
+namespace dsx { namespace caba {
+
+
+#define tmpl(...) __VA_ARGS__ MyHWA1
+
+tmpl(/**/)::~MyHWA1()
+{
+}
+
+ //intArray(1,1) there is one element (here an integer) of size 4 OCTETs/Quentin: attention cela a change c'est un MOT dans la version VM
+
+tmpl(/**/)::MyHWA1(sc_core::sc_module_name insname)
+ :dsx::caba::FifoVirtualCoprocessorWrapper(insname, stringArray(NULL), NULL, stringArray("input", NULL), intArray(1,4))
+{
+}
+
+tmpl(void *)::task_func() {
+ struct mwmr_s *input;
+ uint32_t data;
+
+ while (true) {
+ for (int32_t i = 0; i < 8; i++) {
+ mwmr_read(input, &data, 1); // read 8 integers wich have been modified by the intermediate software task
+ }
+
+ }
+}
+
+}}
+
diff --git a/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java b/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java
index 0850154bc4..c578f610e4 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarCoproMWMR.java
@@ -53,7 +53,7 @@ public class AvatarCoproMWMR extends AvatarComponent{
private int tgtid ;
private int plaps ;
private int fifoToCoprocDepth;
- private int fifoFromCoproDepth;
+ private int fifoFromCoprocDepth;
private int nToCopro;
private int nFromCopro;
private int nConfig;
@@ -63,14 +63,14 @@ public class AvatarCoproMWMR extends AvatarComponent{
private AvatarConnectingPoint[] connectingsPoints;
private int nbConnectingPoint = 16 ;
- public AvatarCoproMWMR(String _coprocName,int srcid, int _srcid, int _tgtid, int _plaps, int _fifoToCoprocDepth,int _fifoFromCoproDepth, int _nToCopro, int _nFromCopro, int _nConfig, int _nStatus, boolean _useLLSC)
+ public AvatarCoproMWMR(String _coprocName,int srcid, int _srcid, int _tgtid, int _plaps, int _fifoToCoprocDepth,int _fifoFromCoprocDepth, int _nToCopro, int _nFromCopro, int _nConfig, int _nStatus, boolean _useLLSC)
{
coprocName = _coprocName;
srcid = _srcid;
tgtid = _tgtid;
plaps = _plaps ;
fifoToCoprocDepth = _fifoToCoprocDepth;
- fifoFromCoproDepth = _fifoFromCoproDepth;
+ fifoFromCoprocDepth = _fifoFromCoprocDepth;
nToCopro = _nToCopro;
nFromCopro = _nFromCopro;
nConfig = _nConfig;
@@ -109,10 +109,14 @@ public class AvatarCoproMWMR extends AvatarComponent{
return plaps;
}
- public int getFifoToCoProcDepth(){
+ public int getFifoToCoprocDepth(){
return fifoToCoprocDepth;
}
+ public int getFifoFromCoprocDepth(){
+ return fifoFromCoprocDepth;
+ }
+
public int getNToCopro(){
return nToCopro;
}
diff --git a/src/main/java/ddtranslatorSoclib/AvatarDMA.java b/src/main/java/ddtranslatorSoclib/AvatarDMA.java
new file mode 100755
index 0000000000..3c735cc8ff
--- /dev/null
+++ b/src/main/java/ddtranslatorSoclib/AvatarDMA.java
@@ -0,0 +1,99 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* * @version 1.0 07/07/2015
+ * @author Julien Henon, Daniela Genius */
+
+package ddtranslatorSoclib;
+
+public class AvatarCoproMWMR extends AvatarComponent{
+
+ private String coprocName;
+ private int srcid ;
+ private int tgtid ;
+ private int plaps ;
+ private int fifoToCoprocDepth;
+ private int fifoFromCoproDepth;
+ private int nToCopro;
+ private int nFromCopro;
+ private int nConfig;
+ private int nStatus;
+ private boolean useLLSC;
+
+ private AvatarConnectingPoint[] connectingsPoints;
+ private int nbConnectingPoint = 16 ;
+
+ public AvatarDMA(String _Dmaname, int _srcid, int _tgtid)
+ {
+ DmaName = _DmaName;
+ srcid = _srcid;
+ tgtid = _tgtid;
+
+ connectingsPoints = new AvatarConnectingPoint[nbConnectingPoint] ;
+
+ }
+
+ AvatarConnectingPoint[] getAvatarConnectingPoints(){
+ return connectingsPoints;
+ }
+
+ int getnbConnectingPoint(){
+ return nbConnectingPoint;
+ }
+
+ void setConnectingPoint(int _indexConnectingPoint, AvatarConnector _connector){
+ connectingsPoints[_indexConnectingPoint].setConnector(_connector);
+ }
+
+ public String getDmaName(){
+ return coprocName;
+ }
+
+ public int getSrcid(){
+ return srcid;
+ }
+
+ public int getTgtid(){
+ return tgtid;
+ }
+}
diff --git a/src/main/java/ddtranslatorSoclib/AvatarTask.java b/src/main/java/ddtranslatorSoclib/AvatarTask.java
index 0740aec7c5..8da5799e97 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarTask.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarTask.java
@@ -52,8 +52,8 @@ package ddtranslatorSoclib;
public class AvatarTask extends AvatarMappedObject{
private AvatarCPU avatarCPUReference;
- private String taskName ;
- private String referenceTaskName;
+ private String taskName ;
+ private String referenceTaskName;
public AvatarTask(String _taskName , String _referenceTaskName, AvatarCPU _avatarCPUReference ){
diff --git a/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java b/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java
index 3903cd29ac..05d1bf870e 100755
--- a/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java
+++ b/src/main/java/ddtranslatorSoclib/AvatarddSpecification.java
@@ -220,7 +220,7 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
for (AvatarComponent copro : components )
{
if (copro instanceof AvatarCoproMWMR){
- System.out.println("$$$$$$$Coproc added to specification!$$$$$$$");
+ System.out.println("Coproc added to specification");
copros.add((AvatarCoproMWMR)copro);
}
@@ -228,6 +228,21 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
return copros;
}
+ /* to do, actuellement c'est un hwa generique */
+ /* the hardware accelerators must be taken from DIPLODOCUS specification */
+ /* public List<DiploHWA> getAllHWA(){
+ List<DiploHWA> hwas = new LinkedList<DiploHWA>();
+ for (DiploComponent hwa : diplocomponents )
+ {
+ if (hwa instanceof DiploHWA){
+ System.out.println("Hardware accelerator added to specification");
+
+ hwas.add((DiploHWA)hwa);
+ }
+ }
+ return hwas;
+ }*/
+
public int getNbCPU(){
return (getAllCPU()).size();
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
index 92cb665ee0..71bd91c37c 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
@@ -114,22 +114,25 @@ public class Declaration {
declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);" + CR;
}
- if(nb_clusters==0){
- declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
- }
- else{
- declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
- }
-
+ int last_tty=0;
if(nb_clusters==0){
int i=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab(" + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
i++;
+ last_tty=tty.getNo_target()+1;
}
//target address depends on number of TTYs and RAMs
+ if(nb_clusters==0){
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(last_tty+3)+"), maptab);" + CR;
+ }
+ else{
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
+ }
+
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
if(ram.getIndex()==0){
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab(2), maptab);" + CR;
@@ -150,9 +153,34 @@ public class Declaration {
+ ram.getNo_target() + "), maptab);" + CR2;
}
if(nb_clusters==0){
- declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+(TopCellGenerator.avatardd.getNb_target())+"));" + CR;
+ /*declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+(TopCellGenerator.avatardd.getNb_target())+"));" + CR;
declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("+(TopCellGenerator.avatardd.getNb_target()+1)+"), \"soclib0\");" + CR;
- declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" + CR;
+ declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" + CR;*/
+
+declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+last_tty +"));" + CR;
+ declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("+(last_tty +1)+"), \"soclib0\");" + CR;
+ declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(last_tty +2)+"),\"block0.iso\", 2048);" + CR;
+
+ //only non-clustered version
+ int hwa_no=0;
+ int target_no = TopCellGenerator.avatardd.getNb_target();
+ int init_no = TopCellGenerator.avatardd.getNb_init();
+ for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
+ // declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
+
+ declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+init_no+"), IntTab("+target_no+ "),"+copro.getPlaps()+","+copro.getFifoToCoprocDepth()+","+copro.getFifoFromCoprocDepth()+","+copro.getNToCopro()+","+copro.getNFromCopro()+","+copro.getNConfig()+","+copro.getNStatus()+","+ copro.getUseLLSC()+");"+ CR2;
+
+//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+
+//DG 28.08.
+ // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
+
+declaration += "caba::MyHWA"+hwa_no+" hwa"+hwa_no+"(\"hwa"+hwa_no+"\");"+ CR2;
+ target_no++;
+ init_no++;
+ hwa_no++;
+ }
+
}else{
declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));" + CR;
declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");" + CR;
@@ -160,12 +188,15 @@ public class Declaration {
}
if(nb_clusters==0){
+
for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
//declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
- declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
+ // declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
+
+ declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab,"+(3+TopCellGenerator.avatardd.getNb_init())+"," + (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;//DG 28.08.
int i=0;
//if BUS was not last in input file, update here
@@ -185,7 +216,9 @@ if(nb_clusters==0){
vgmn.setFifoDepth(8); //default value; must be > 2
- declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+ // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, " +(3+TopCellGenerator.avatardd.getNb_init())+"," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;//DG 28.08.
+
// declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNbRAM()+TopCellGenerator.avatardd.getNbTTY()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
@@ -212,24 +245,7 @@ if(nb_clusters==0){
const bool use_llsc );
*/
- //only non-clustered version
- int i=0;
- for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
-
-
- //one virtual component for each hardware accellerator
- declaration += "caba::FifoVirtualCoprocessorWrapper(\"hwa"+i+"\",1,1,1,1);"+ CR;
-//DG 23.08. a adapter
-/*fifos_out,
- fifos_out_width,
- fifos_in,
- fifos_in_width)*/
-
-i++;
-
- }
}
else {
@@ -279,7 +295,6 @@ else {
declaration += "soclib::caba::VciLocalCrossbar<vci_param> crossbar"+crossbar.getClusterIndex()+"(\"" + crossbar.getCrossbarName() + "\"" + " , maptab, IntTab("+ crossbar.getClusterIndex()+"),IntTab("+crossbar.getClusterIndex()+"), "+crossbar.getNbOfAttachedInitiators()+", "+crossbar.getNbOfAttachedTargets()+");" + CR2;
-
//if CROSSBAR was not last in input file, update here
crossbar.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
crossbar.setNbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Header.java b/src/main/java/ddtranslatorSoclib/toTopCell/Header.java
index 8ed3df6643..58f799ce3c 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Header.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Header.java
@@ -99,7 +99,10 @@ int nb_clusters=5;
//The user must ensure that there is a SoCLib component corresponding to this coprocessor
// if (with_hw_accellerator>0){
//DG 23.08. actuellement il ne les trouve pas!
- for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ int hwas=0;
+ header +="#include \"fifo_virtual_copro_wrapper.h\""+ CR;
+
+ for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
// String name = HWAccelerator.getCoprocName();
// header +="#include \""+name+"\""+ CR;
@@ -108,10 +111,12 @@ int nb_clusters=5;
//header +="#include \"output_coproc.hh\""+ CR;
/* can be found in /users/outil/soc/soclib/soclib/module/internal_component/fifo* */
- header +="#include \"fifo_virtual_coprocessor_wrapper.h\""+ CR;
- }
- // }
-
+ //header +="#include \"fifo_virtual_copro_wrapper.h\""+ CR;
+ header +="#include \"my_hwa"+hwas+".h\""+ CR;
+ hwas++;
+ }
+ // }
+
header+= "#include \"vci_block_device.h\"" + CR
+ "#include \"vci_simhelper.h\"" + CR + "#include \"vci_fd_access.h\"" + CR
+ "#include \"vci_ethernet.h\"" + CR
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
index c626c00131..595ce2e80a 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/MappingTable.java
@@ -118,7 +118,7 @@ public class MappingTable {
size = 1073741824;
}
else {//dimension segments to be smaller
- size = 268435456;
+ size = 268435456;
}
}
else{
@@ -168,18 +168,27 @@ public class MappingTable {
mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("+(l+3)+"), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0xC0200000, 0x00000100, IntTab("+(l+4)+"), false));" + CR2;
- int hwa_count=0;
- int hwa_count2=0;
- // if (with_hw_mwmr>0){
- //les accellerateurs sont caches car apparaissent uniquement au niveau DIPLODOCUS
-for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
- // mapping += "maptab.add(Segment(\"mwmr"+HWAccelerator.getNo()+"\", MWMR_BASE , MWMR_SIZE , IntTab("+(m+hwa_count)+"), false));" + CR;
- // mapping += "maptab.add(Segment(\"mwmr_ram"+HWAccelerator.getNo()+"\", MWMRd_BASE , MWMRd_SIZE , IntTab("+(m+hwa_count+1)+"), false));" + CR2;
- mapping += "maptab.add(Segment(\"mwmr"+hwa_count+"\", MWMR_BASE , MWMR_SIZE , IntTab("+(m+hwa_count2)+"), false));" + CR;
- mapping += "maptab.add(Segment(\"mwmr_ram"+hwa_count+"\", MWMRd_BASE , MWMRd_SIZE , IntTab("+(m+hwa_count2+1)+"), false));" + CR2;
- hwa_count2+=2;
- hwa_count++;
- }
+
+ /* Instanciation of the MWMR wrappers for hardware accellerators */
+ /* The accelerators themselves are specifies on DIPLODOCUS level */
+
+ int hwa_count=0;
+ int MWMRd_SIZE=4096;
+ int MWMR_SIZE=1024;
+ int MWMR_BASE=359242137;
+ int MWMRd_BASE=360919859;
+ // int MWMR_BASE=3592421376; //0xd62
+ //int MWMRd_BASE=3609198592; //0xd72
+
+ for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ mapping += "maptab.add(Segment(\"mwmr"+hwa_count+"\", 0x"+Integer.toHexString(MWMR_BASE+i*1024)+", 0x"+ Integer.toHexString(MWMR_SIZE)+", IntTab("+(l+5+hwa_count)+"), false));" + CR;
+ hwa_count++;
+ }
+ hwa_count=0;
+ for (AvatarCoproMWMR MWMRwrapper : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ mapping += "maptab.add(Segment(\"mwmr_ram"+hwa_count+"\", 0x"+(Integer.toHexString(MWMRd_BASE+i*4096))+", 0x"+Integer.toHexString(MWMRd_SIZE)+", IntTab("+(l+5+hwa_count)+"), false));" + CR2;
+ hwa_count++;
+ }
return mapping;
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
index b22c0fc4dd..5299c2125d 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
@@ -341,16 +341,23 @@ public class NetList {
// if(nb_cluster == 0){
i=0;
for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- //a coprocessor with FIFO interface
- netlist = netlist +copro.getCoprocName()+".p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist + copro.getCoprocName()+".p_"+i+"_ctrl(signal_fifo_"+i+"_ctrl);" + CR;
- //and its mwmr controller
- netlist = netlist + "mwmr"+i+".p_clk(signal_clk);" + CR;
- netlist = netlist + "mwmr"+i+".p_resetn(signal_resetn);" + CR;
- netlist = netlist + "mwmr"+i+".p_vci_initiator(signal_mwmr_"+i+"initiator);" + CR;
- netlist = netlist + "mwmr"+i+".p_vci_target(signal_mwmr_"+i+"_target);" + CR;
- netlist = netlist + copro.getCoprocName()+".p_"+i+"_ctrl(signal_fifo_"+i+"_ctrl);" + CR;
+ //a coprocessor with its FIFO interface built from HWA
+ netlist = netlist +"hwa"+i+".p_clk(signal_clk);" + CR;
+ netlist = netlist +"hwa"+i+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist +"hwa"+i+".p_from_ctrl["+i+"](signal_fifo_"+i+"_from_ctrl);" + CR;
+ netlist = netlist +"hwa"+i+".p_to_ctrl["+i+"](signal_fifo_"+i+"_to_ctrl);" + CR2;
+
+ //MWMR controller of the HWA
+ netlist = netlist +copro.getCoprocName() +".p_clk(signal_clk);" + CR;
+ netlist = netlist +copro.getCoprocName() +".p_resetn(signal_resetn);" + CR;
+ netlist = netlist +copro.getCoprocName() +".p_vci_initiator(signal_mwmr_"+i+"_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName()+".p_vci_target(signal_mwmr_"+i+"_target);" + CR2;
+ netlist = netlist +copro.getCoprocName() +".p_from_coproc["+i+"](signal_fifo_"+i+"_from_ctrl);" + CR;
+netlist = netlist +copro.getCoprocName() +".p_to_coproc["+i+"](signal_fifo_"+i+"_to_ctrl);" + CR;
+//DG 5.9.
+// netlist = netlist +copro.getCoprocName() +".status();" + CR;
+// netlist = netlist +copro.getCoprocName() +".config();" + CR;
+i++;
}
@@ -394,7 +401,7 @@ public class NetList {
int p=0;
//for testing: vci_synthetic_initiator.h and vci_synthetic_target.h
-for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ //for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
/* netlist += "mwmr"+HWAccelerator.getNo()+".p_clk(signal_clk);" + CR;
netlist += "mwmr"+HWAccelerator.getNo()+".p_resetn(signal_resetn);" + CR;
netlist += "mwmr"+HWAccelerator.getNo()+".p_vci_initiator(signal_mwmr"+HWAccelerator.getNo()+"_initiator);" + CR;
@@ -402,13 +409,13 @@ for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()
netlist += " mwmr"+HWAccelerator.getNo()+".p_from_coproc["+HWAccelerator.getNo()+"](signal_fifo_to_ctrl);" + CR;
netlist += " mwmr"+HWAccelerator.getNo()+".p_to_coproc["+HWAccelerator.getNo()+"](signal_fifo_from_ctrl);" + CR;*/
- netlist += "mwmr"+p+".p_clk(signal_clk);" + CR;
+ /* netlist += "mwmr"+p+".p_clk(signal_clk);" + CR;
netlist += "mwmr"+p+".p_resetn(signal_resetn);" + CR;
netlist += "mwmr"+p+".p_vci_initiator(signal_mwmr"+p+"_initiator);" + CR;
netlist += " mwmr"+p+".p_vci_target(signal_mwmr"+p+"_target);" + CR;
- netlist += " mwmr"+p+".p_from_coproc["+p+"](signal_fifo_to_ctrl);" + CR;
- netlist += " mwmr"+p+".p_to_coproc["+p+"](signal_fifo_from_ctrl);" + CR;
-}
+ netlist += " mwmr"+p+".p_from_coproc["+p+"](signal_fifo_"+p+"_to_ctrl);" + CR;
+ netlist += " mwmr"+p+".p_to_coproc["+p+"](signal_fifo_"+p+"_from_ctrl);" + CR;
+ } */
// }
//generate trace file if marked trace option
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java b/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
index 4249cd7523..a6c049c822 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
@@ -56,6 +56,8 @@ public class Platforminfo {
public static String getPlatformInfo() {
//determine if the platform is vgsb or vgmn based (mutually exclusive)
int with_vgsb=TopCellGenerator.avatardd.getAllBus().size();
+ int nb_hwa=TopCellGenerator.avatardd.getAllCoproMWMR().size();
+
//bus can be other than VGSB (CAN...), for the moment restricted to VGSB
String platforminfo = CR;
platforminfo +="use = ["+CR
@@ -82,8 +84,14 @@ public class Platforminfo {
platforminfo+="Uses('caba:vci_mwmr_stats'),"+CR
+"Uses('caba:vci_logger'),"+CR
+"Uses('caba:vci_local_crossbar'),"+CR
- +"Uses('caba:fifo_virtual_coprocessor_wrapper'),"+CR
- +"Uses('common:elf_file_loader'),"+CR
+ +"Uses('caba:fifo_virtual_copro_wrapper'),"+CR ;
+ //DG 28.08. example coprocessors
+ int i=0;
+ for(i=0;i<nb_hwa;i++){
+ platforminfo+="Uses('caba:my_hwa"+i+"),"+CR;
+ }
+ //+"Uses('caba:MyHWA1'),"+CR
+ platforminfo+="Uses('common:elf_file_loader'),"+CR
+"Uses('common:plain_file_loader'),"+CR
+"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),"+CR
+"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:arm'),"+CR
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java b/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java
index 27db97eed1..e8da330cd5 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Signal.java
@@ -88,7 +88,9 @@ signal = signal +"caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_v
for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
- signal = signal +"caba::VciSignals<vci_param> signal_fifo_"+i+"_ctrl;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_fifo_"+i+"_from_ctrl;"+ CR;
+ signal = signal +"caba::VciSignals<vci_param> signal_fifo_"+i+"_to_ctrl;"+ CR;
+ i++;
}
if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
diff --git a/src/main/java/ui/AvatarDeploymentPanelTranslator.java b/src/main/java/ui/AvatarDeploymentPanelTranslator.java
index dee6d9ff07..30fec96522 100644
--- a/src/main/java/ui/AvatarDeploymentPanelTranslator.java
+++ b/src/main/java/ui/AvatarDeploymentPanelTranslator.java
@@ -242,9 +242,8 @@ public class AvatarDeploymentPanelTranslator {
int nConfig = addCoproMWMRNode.getNConfig(); // Nb of configuration registers
int nStatus = addCoproMWMRNode.getNStatus(); // nb of status registers
boolean useLLSC = addCoproMWMRNode.getUseLLSC(); // more efficient protocol. 0: not used. 1 or more -> used
-
- // System.out.println("$$$$$$$$$$$Hardware Accelerator found$$$$$$$$$$$");
-
+ nb_init++;
+ nb_target+=2;//DG 28.08. two targets as two segments of memory are created mwmr and mwmrd
AvatarCoproMWMR acpMWMR;
acpMWMR = new AvatarCoproMWMR(timerName, srcid, srcid, tgtid, plaps, fifoToCoprocDepth, fifoFromCoprocDepth, nToCopro, nFromCopro, nConfig, nStatus, useLLSC);
avatarMap.put(dp, acpMWMR);
--
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