diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index 760d20e84e23632c9b1a826f3dbb554650443fd4..061c038b8baa8b3f0b78753b4d7cf757b4e45f2f 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -50,18 +50,20 @@
 FPGA::FPGA(    ID iID, 
 	       std::string iName,  
 	       WorkloadSource* iScheduler,
-	       TMLTime iReconfigTime, 
+	       TMLTime iReconfigTime,
+	       TMLTime iTimePerCycle,
 	       unsigned int iChangeIdleModeCycles, 
 	       unsigned int iCyclesBeforeIdle,
 	       unsigned int iCyclesPerExeci, 
 	       unsigned int iCyclesPerExecc ) : SchedulableDevice(iID, iName, iScheduler)
 					      ,_reconfigTime(iReconfigTime)
+					      ,_timePerCycle(iTimePerCycle)
 					      ,_masterNextTransaction(0)
 					      ,_lastTransaction(0)
-					      ,_changeIdleModeCycles(iChangeIdleModeCycles)
-					      ,_cyclesBeforeIdle(iCyclesBeforeIdle)
-					      ,_cyclesPerExeci(iCyclesPerExeci)
-					      ,_cyclesPerExecc(iCyclesPerExecc)
+					      ,_changeIdleModeCycles(iChangeIdleModeCycles * _timePerCycle)
+					      ,_cyclesBeforeIdle(iCyclesBeforeIdle * _timePerCycle)
+					      ,_cyclesPerExeci(iCyclesPerExeci * _timePerCycle)
+					      ,_cyclesPerExecc(iCyclesPerExecc * _timePerCycle)
 					      ,_reconfigNumber(0)
 					      ,_maxEndTime(0)
 					     
@@ -152,7 +154,7 @@ void FPGA::calcStartTimeLength(){
 #ifdef BUS_ENABLED
   if (_masterNextTransaction==0){
 #endif  
-    _nextTransaction->setLength(max(_nextTransaction->getVirtualLength(),(TMLTime)1));
+    _nextTransaction->setLength(max(_nextTransaction->getVirtualLength() * _cyclesPerExeci,(TMLTime)1));
 #ifdef BUS_ENABLED
   }
 #endif
@@ -189,7 +191,7 @@ std::cout<<"fpga truncateNextTransAt"<<std::endl;
     if (iTime <= _nextTransaction->getStartTime()) return 0;  //before: <=
     TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
     _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration), (TMLTime)1));
-    _nextTransaction->setLength(_nextTransaction->getVirtualLength());
+    _nextTransaction->setLength(_nextTransaction->getVirtualLength() * _cyclesPerExeci);
   }
   return _nextTransaction->getOverallLength();
 }
@@ -259,14 +261,14 @@ std::cout<<"fpga addTransaction"<<std::endl;
         if(!_nextTransaction->getCommand()->getTask()->getIsFirstTranExecuted() && (_tempTranName.find("Read") == std::string::npos
         && _tempTranName.find("Wait") == std::string::npos && _tempTranName.find("Notified") == std::string::npos)) {
             unsigned int _tempStartTime = _nextTransaction->getStartTime();
-            _nextTransaction->setStartTime(_tempStartTime + _reconfigNumber * _reconfigTime);
+            _nextTransaction->setStartTime(_tempStartTime + _reconfigNumber * _reconfigTime * _cyclesPerExeci);
             _maxEndTime=max(_maxEndTime,_nextTransaction->getEndTime());
             _transactListReconfig.push_back(_nextTransaction);
         }
         _nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
     } else if(_tempReconfigNumber>0) {
         if(!_nextTransaction->getCommand()->getTask()->getIsFirstTranExecuted()) {
-            _nextTransaction->setStartTime(_maxEndTime + _tempReconfigNumber * _reconfigTime);
+            _nextTransaction->setStartTime(_maxEndTime + _tempReconfigNumber * _reconfigTime * _cyclesPerExeci);
             _nextTransaction->getCommand()->getTask()->setIsFirstTranExecuted(true);
             _transactListReconfig.push_back(_nextTransaction);
         }
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index ccfde361a3dac5dd17190b5f683b87c76bf4a6a7..85874ea8a445a7fe619441e30a0411161bcc8048 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -78,7 +78,7 @@ public:
 	\param iCyclesPerExecc Cycles needed to execute one EXECC unit
 	*/
 	
-        FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
+        FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, TMLTime iTimePerCycle, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
 	///Destructor
 	virtual ~FPGA();
 	///Determines the next FPGA transaction to be executed
@@ -164,6 +164,7 @@ protected:
 	void calcStartTimeLength();
 
 	TMLTime _reconfigTime;
+	TMLTime _timePerCycle;
 
 
 	///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
index bcb99f76edf187445b1dee08013a58cadb69045d..593cdb0a4a781db880714817434941a8f0046a94 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
@@ -360,7 +360,7 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
                 declaration += "FPGA* " + hwFpgaInstName + " = new FPGA(" + hwFpgaNode.getID() + ", \"" + namesGen.hwFpgaName(hwFpgaNode) + "\", "
                         + schedulerInstName + ", ";
 
-                declaration += hwFpgaNode.reconfigurationTime + ", " + hwFpgaNode.goIdleTime + ", " + hwFpgaNode.maxConsecutiveIdleCycles + ", "
+                declaration += hwFpgaNode.reconfigurationTime + ", " + hwFpgaNode.clockRatio + ", " + hwFpgaNode.goIdleTime + ", " + hwFpgaNode.maxConsecutiveIdleCycles + ", "
                         + hwFpgaNode.execiTime + ", " + hwFpgaNode.execcTime + ")" + SCCR;
 
                 // DB: Issue #21 TODO: Should there be a scheduler?? Given the for loop, cores