From 9923e56381ab28b9975f87eb4bfbe11418d3b144 Mon Sep 17 00:00:00 2001
From: niusiyuan <siyuan.niu@telecom-paristech.fr>
Date: Tue, 19 Mar 2019 15:54:23 +0100
Subject: [PATCH] segment fault
---
simulators/c++2/Makefile | 1 +
simulators/c++2/Makefile.defs | 6 +++---
simulators/c++2/src_simulator/app/TMLChannel.cpp | 11 +++++++++--
.../c++2/src_simulator/arch/MultiCoreCPU.cpp | 13 +++++++++++--
.../c++2/src_simulator/arch/SchedulableDevice.cpp | 1 -
simulators/c++2/src_simulator/sim/Simulator.cpp | 15 +++++++++++----
6 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/simulators/c++2/Makefile b/simulators/c++2/Makefile
index a134a6fadc..236bc48298 100755
--- a/simulators/c++2/Makefile
+++ b/simulators/c++2/Makefile
@@ -11,6 +11,7 @@ LOPT = -O3 -ldl
LTHREAD = -pthread
DEBUG = -g
+DEBUGFLAGS = -O0 -g -D_DEBUG
PROFILE = -pg
OTHER = -Wall
SOLARIS_SPECIFIC = -lsocket -lnsl
diff --git a/simulators/c++2/Makefile.defs b/simulators/c++2/Makefile.defs
index 3b54a42b2f..cf94839149 100644
--- a/simulators/c++2/Makefile.defs
+++ b/simulators/c++2/Makefile.defs
@@ -30,13 +30,13 @@ makedir:
mkdir -p ./lib/sim
$(OBJDIR)/%.o: $(SRCS_base_DIR)/%.cpp
- $(CC) $(CFLAGS) $(INCDIR) -o $@ -c $<
+ $(CC) $(CFLAGS) $(INCDIR) -g -o $@ -c $<
#$(OBJDIR)/evt/ListenersSimCmd.o: $(SRCS_base_DIR)/evt/ListenersSimCmd.cpp
-# $(CC) $(CFLAGS) $(INCDIR) -o - ldl $@ -c $<
+# $(CC) $(CFLAGS) $(INCDIR) -g -o - ldl $@ -c $<
$(OBJDIR)/%.o: ./%.cpp
- $(CC) $(CFLAGS) $(INCDIR) -o $@ -c $<
+ $(CC) $(CFLAGS) $(INCDIR) -g -o $@ -c $<
test:
./run.x -oxml answer.xml -cmd '1 2 1000000;22 100;7 0 vcddump.vcd'
diff --git a/simulators/c++2/src_simulator/app/TMLChannel.cpp b/simulators/c++2/src_simulator/app/TMLChannel.cpp
index da05937a11..1b1b2b0a16 100755
--- a/simulators/c++2/src_simulator/app/TMLChannel.cpp
+++ b/simulators/c++2/src_simulator/app/TMLChannel.cpp
@@ -67,20 +67,27 @@ BusMaster* TMLChannel::getNextMaster(TMLTransaction* iTrans){
}
BusMaster* TMLChannel::getFirstMaster(TMLTransaction* iTrans){
+ std::cout<<"get First master"<<std::endl;
//if (iTrans->getCommand()->getTask()==_writeTask){
//std::cout << "fima 1\n";
- if (_masters==0 || _slaves==0 || _numberOfHops==0) return 0;
+ if(iTrans==0) std::cout<<"iTrans==0"<<std::endl;
+ else std::cout<<"iTrans is: "<<iTrans->toString()<<std::endl;
+ if (_masters==0 || _slaves==0 || _numberOfHops==0 ) { std::cout<<"case 1"<<std::endl; return 0;}
//std::cout << "fima 2\n";
+ std::cout<<"test11111"<<std::endl;
if (iTrans==_writeTrans){
//if (iTrans->getCommand()->getTask()==_writeTask){
//std::cout << "fima 3\n";
+ std::cout<<"case 2"<<std::endl;
_writeTransCurrHop=0;
return _masters[_writeTransCurrHop];
}else{
+ std::cout<<"case 4"<<std::endl;
//std::cout << "fima 4\n";
- if (_slaves[(_numberOfHops/2)]==0) return 0; //NEW!!!
+ if (_slaves[(_numberOfHops/2)]==0) { std::cout<<"case 3"<<std::endl; return 0;} //NEW!!!
//std::cout << "fima 5\n";
_readTransCurrHop=_numberOfHops-1;
+
return _masters[_readTransCurrHop];
}
}
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index 592168b2eb..5b5ebeca4c 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -118,6 +118,7 @@ TMLTime MultiCoreCPU::getMinEndSchedule(){
}
TMLTransaction* MultiCoreCPU::getNextTransaction(){
+std::cout<<"getNextTransaction"<<std::endl;
#ifdef BUS_ENABLED
if (_masterNextTransaction == 0 || _nextTransaction == 0){
return _nextTransaction;
@@ -125,8 +126,9 @@ TMLTransaction* MultiCoreCPU::getNextTransaction(){
#ifdef DEBUG_CPU
std::cout << "CPU:getNT: " << _name << " has bus transaction on master " << _masterNextTransaction->toString() << std::endl;
#endif
- //std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
+ std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
+ std::cout<<"getNextTransaction getfirstmaster ok"<<std::endl;
//std::cout << "1 aTempMaster: " << aTempMaster << std::endl;
bool aResult = aTempMaster->accessGranted();
//std::cout << "2" << std::endl;
@@ -145,11 +147,13 @@ TMLTransaction* MultiCoreCPU::getNextTransaction(){
}
void MultiCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
+std::cout<<"calcStartTimeLength"<<std::endl;
#ifdef DEBUG_CPU
std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
#endif
#ifdef BUS_ENABLED
- //std::cout << "get channel " << std::endl;
+std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
+ //std::cout << " " << std::endl;
TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
//std::cout << "after get channel " << std::endl;
if(aChannel == 0){
@@ -277,6 +281,7 @@ TMLTime MultiCoreCPU::truncateNextTransAt(TMLTime iTime){
}
bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
+std::cout<<"addTransaction"<<std::endl;
bool aFinish;
//TMLTransaction* aTransCopy=0;
if (_masterNextTransaction==0){
@@ -366,6 +371,7 @@ bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
}
void MultiCoreCPU::schedule(){
+std::cout<<"schedule"<<std::endl;
//std::cout <<"Hello\n";
//std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
@@ -386,8 +392,11 @@ void MultiCoreCPU::schedule(){
if (_masterNextTransaction!=0) _masterNextTransaction->registerTransaction(0);
}
//std::cout << "5\n";
+ if (_nextTransaction ==0) std::cout<<"in schedule nextTransaction is 0"<<std::endl;
+ if (aOldTransaction != _nextTransaction) std::cout<<"in schedule aOldTransaction = nextTransaction"<<std::endl;
if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
//std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
+ else std::cout<<"no need calcStartTimeLength"<<std::endl;
}
//std::string MultiCoreCPU::toString() const{
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index 51c32eb1d1..dc7fac968e 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -198,7 +198,6 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
TMLTime aCurrTime = 0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
- myfile<<"test transaction core number!!!"<<(*i)->getTransactCoreNumber()<<std::endl;
if( (*i)->getTransactCoreNumber() == time ){
TMLTransaction* aCurrTrans = *i;
unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index be2d4f5327..99bd1bd0b4 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -81,7 +81,9 @@ TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevi
//for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
aTempDevice=*i;
+ std::cout<<"test888!!!"<<std::endl;
aTempTrans=aTempDevice->getNextTransaction();
+ std::cout<<"test999!!!"<<std::endl;
if (aTempTrans!=0 && aTempTrans->getVirtualLength()>0){
#ifdef DEBUG_KERNEL
std::cout << "kernel:getTLET: transaction found on " << aTempDevice->toString() << ": " << aTempTrans->toString() << std::endl;
@@ -297,6 +299,7 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
}
std::ofstream myfile(iTraceFileName.c_str());
+ myfile<<iTraceFileName.c_str()<<std::endl;
if (myfile.is_open()) {
// DB: Issue #4
@@ -309,23 +312,24 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
if ( findSlash == std::string::npos ) {
indexSlash = 0;
+ myfile<<"indexSlash=0\n";
}
else {
indexSlash = findSlash;
}
const std::string ext( EXT_HTML );
- const std::string cssFileName = iTraceFileName.substr( indexSlash + 1, iTraceFileName.length() - indexSlash - ext.length() - 1 ) + EXT_CSS;
-
+ const std::string cssFileName = iTraceFileName.substr( indexSlash + 1, iTraceFileName.length() - indexSlash - ext.length() - 1 ) + EXT_CSS;
+ myfile<<"length is "<< iTraceFileName.length() - indexSlash - ext.length() - 1<<std::endl;
const std::string cssFullFileName = iTraceFileName.substr( 0, indexSlash + 1 ) + cssFileName;
std::ofstream cssfile( cssFullFileName.c_str() );
-
+ myfile<<"full name is "<<cssFullFileName<<std::endl;
if ( cssfile.is_open() ) {
cssfile << SCHED_HTML_CSS_CONTENT;
cssfile.close();
myfile << SCHED_HTML_CSS_BEG_LINK;
- myfile << cssFileName;
+ myfile << cssFullFileName;
myfile << SCHED_HTML_CSS_END_LINK;
}
else {
@@ -491,9 +495,12 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
//std::cout << "after loop2" << std::endl;
//for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::setRescheduleFlag));
//for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::schedule));
+ std::cout<<"test666!!!"<<std::endl;
for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
+ std::cout<<"test777!!!"<<std::endl;
//std::cout << "after schedule" << std::endl;
transLET=getTransLowestEndTime(cpuLET);
+ std::cout<<"test000!!!"<<std::endl;
//std::cout << "after getTLET" << std::endl;
#ifdef LISTENERS_ENABLED
if (_wasReset) NOTIFY_SIM_STARTED();
--
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