diff --git a/simulators/c++2/src_simulator/app/TMLTask.cpp b/simulators/c++2/src_simulator/app/TMLTask.cpp
index 0dc23521127cffcafba64baba7e5a7e01cc126ae..e3eb8d57fcb3c64bd77ea25b2fbaa4c06c0e138b 100755
--- a/simulators/c++2/src_simulator/app/TMLTask.cpp
+++ b/simulators/c++2/src_simulator/app/TMLTask.cpp
@@ -345,7 +345,9 @@ unsigned int TMLTask::getState() const{
 		
 		}
 	}*/
-	if (_currCommand==0 || _currCommand->getCurrTransaction()==0 || dynamic_cast<TMLStopCommand*>(_currCommand)!=0){
+	if(_endLastTransaction == 0) { // when user starts the simulator the status should be RUNABLE, not TERMINATED
+	    return RUNNABLE;
+	} else if (_currCommand==0 || _currCommand->getCurrTransaction()==0 || dynamic_cast<TMLStopCommand*>(_currCommand)!=0){
 		return TERMINATED;
 	} else if (_currCommand->getCurrTransaction()->getVirtualLength()==0){
 		return SUSPENDED;
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index 64d050acf5bf37cd5ec25920d61edcda25d900fa..1d6dc8d72397e4f8df7124b799374fbf2b3af80e 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -61,7 +61,7 @@ MultiCoreCPU::MultiCoreCPU(ID iID,
 			   unsigned int iCyclesBeforeIdle, 
 			   unsigned int ibyteDataSize,
 			   unsigned int iAmountOfCore): CPU(iID, iName, iScheduler, iAmountOfCore), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle), 
-							coreNumber(0)
+							coreNumber(0), timeCnt(0)
 #ifdef PENALTIES_ENABLED
                                                                                                                                                                                                                                                                  , _pipelineSize(iPipelineSize), _taskSwitchingCycles(iTaskSwitchingCycles),_brachingMissrate(iBranchingMissrate)
                                                                                                                                                                                                                                                                  , _changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
@@ -92,6 +92,8 @@ MultiCoreCPU::~MultiCoreCPU(){
 
 ///test///
 void MultiCoreCPU::initCore(){
+  if (timeCnt > 0) timeCnt = 0;
+  if (coreNumber != 0) coreNumber = 0;
   for (unsigned int i = 0; i < amountOfCore; i++)
     multiCore[i] = 0;
 }
@@ -340,16 +342,10 @@ std::cout<<"addTransaction"<<_name<<std::endl;
     //    std::cout << "CPU:addt: to be started" << std::endl;
     //std::cout << "CPU:calcSTL: addtransaction of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
     _endSchedule=_nextTransaction->getEndTime();
-    ////test///
-   // unsigned int iCoreNumber=getCoreNumber();
-    static unsigned int time=0;
-    // std::cout<<"multicore number "<<coreNumber<<" end schedule "<<_endSchedule<<std::endl;
-//    multiCore[coreNumber]=_endSchedule;
-  //  std::cout<<"cycle time is "<<_cycleTime<<std::endl;
-    if (time < amountOfCore -1){
+    if (timeCnt < amountOfCore -1){
 //	  _endSchedule=0;
         // check if lasttrans = idle Delay and current trans has the same task=> not change core, after that update the multicore mapping
-        if ((_nextTransaction != NULL  && _lastTransaction != NULL && !(_lastTransaction->getCommand()->getActiveDelay()) && _lastTransaction->getCommand()->isDelayTransaction())) {
+        if ((_nextTransaction != NULL  && _lastTransaction != NULL && (_lastTransaction->getEndTime() == _nextTransaction->getStartTime()))) {
             if (_nextTransaction->getCommand()->getTask() == _lastTransaction->getCommand()->getTask()) {
                 _nextTransaction->setTransactCoreNumber(_lastTransaction->getTransactCoreNumber());
                 multiCore[_lastTransaction->getTransactCoreNumber()] = _endSchedule;
@@ -366,7 +362,7 @@ std::cout<<"addTransaction"<<_name<<std::endl;
 	 
     } else {
         // check if lasttrans = idle Delay and current trans has the same task=> not change core, after that update the multicore mapping
-        if ((_nextTransaction != NULL  && _lastTransaction != NULL && !(_lastTransaction->getCommand()->getActiveDelay()) && _lastTransaction->getCommand()->isDelayTransaction())) {
+        if ((_nextTransaction != NULL  && _lastTransaction != NULL && (_lastTransaction->getEndTime() == _nextTransaction->getStartTime()))) {
             if (_nextTransaction->getCommand()->getTask() == _lastTransaction->getCommand()->getTask()) {
                 _nextTransaction->setTransactCoreNumber(_lastTransaction->getTransactCoreNumber());
                 multiCore[_lastTransaction->getTransactCoreNumber()] = _endSchedule;
@@ -381,7 +377,8 @@ std::cout<<"addTransaction"<<_name<<std::endl;
 
         _endSchedule = getMinEndSchedule();
     }
-    time++;
+    std::cout << "MULTICORE: assign transaction " << _nextTransaction->toShortString() << " to core " << _nextTransaction->getTransactCoreNumber() << std::endl;
+    timeCnt++;
     if(!(_nextTransaction->getCommand()->getTask()->getIsDaemon()==true && _nextTransaction->getCommand()->getTask()->getNextTransaction(0)==0))
       _simulatedTime=max(_simulatedTime,_nextTransaction->getEndTime());
     _overallTransNo++; //NEW!!!!!!!!
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
index a3a1b8c2836e0d9190c2a72cb16e780c5f084e7a..a59c628ccb8c8fde0f7d1df88422ca0da2537767 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
@@ -148,6 +148,7 @@ protected:
 	TMLTime _timePerCycle;
 	///test////
 	unsigned int coreNumber;
+	unsigned int timeCnt; // count the time of mapping transaction to core
 	//first parameter is the core number
 	///second parameter is the end schedule in the core
 	std::map <unsigned int, unsigned int> multiCore;
diff --git a/simulators/c++2/src_simulator/arch/RRPrioScheduler.cpp b/simulators/c++2/src_simulator/arch/RRPrioScheduler.cpp
index b20e461ecd328cb90d6a1acf8143fda78e60beda..2860d7383534080848b339b988d2bf8a517dfc3c 100644
--- a/simulators/c++2/src_simulator/arch/RRPrioScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/RRPrioScheduler.cpp
@@ -65,7 +65,8 @@ TMLTime RRPrioScheduler::schedule(TMLTime iEndSchedule){
             if((!(isDelayTrans->getCommand()->getActiveDelay()) && isDelayTrans->getCommand()->isDelayTransaction())){
                  aSameTaskFound=false;
             }else if (anOldTransaction==0 || _lastSource->getNextTransaction(iEndSchedule)==anOldTransaction || _timeSlice >=_elapsedTime + anOldTransaction->getOperationLength() + _minSliceSize){
-				std::cout << "Select same task, remaining: " << _timeSlice - anOldTransaction->getOperationLength() << "\n";
+				if (anOldTransaction != 0)
+				    std::cout << "Select same task, remaining: " << _timeSlice - anOldTransaction->getOperationLength() << "\n";
 				aSourcePast=_lastSource;
 				aSameTaskFound=true;
 			}
diff --git a/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java b/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
index 6473e7974e5a5863aa16ab62f689e7c26e51aabf..b406d11b31c7a0b1f7134bc5f1bc9ff62bde3e30 100644
--- a/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
+++ b/ttool/src/test/java/tmltranslator/DiplodocusSimulatorTest.java
@@ -32,8 +32,8 @@ public class DiplodocusSimulatorTest extends AbstractUITest {
     final String DIR_GEN = "test_diplo_simulator/";
     final int [] NB_Of_STATES = {173, 1824};
     final int [] NB_Of_TRANSTIONS = {172, 1823};
-    final int [] MIN_CYCLES = {210, 4106};
-    final int [] MAX_CYCLES = {315, 4106};
+    final int [] MIN_CYCLES = {210, 4308};
+    final int [] MAX_CYCLES = {315, 4308};
     //model for daemon task
     final String [] MODELS_DAEMON = {"daemontest1", "daemontest2"};
     final int [] NB_Of_DAEMON_STATES = {12, 124};
diff --git a/ttool/src/test/java/tmltranslator/HTMLParseTest.java b/ttool/src/test/java/tmltranslator/HTMLParseTest.java
index f540f3003ad8c6072fd39d8666c4135f947e677d..60bc3c4a9190a7a68373684c6cc035bc7ee87f4e 100644
--- a/ttool/src/test/java/tmltranslator/HTMLParseTest.java
+++ b/ttool/src/test/java/tmltranslator/HTMLParseTest.java
@@ -33,9 +33,10 @@ public class HTMLParseTest extends AbstractUITest {
     final String [] MODELS_PARSE_HTML = {"parseFPGA_HTML", "parseCPU1_HTML","parseCPU2_HTML"};
     final String [] PARSE_FPGA = {"<- idle 471 ->","", "", "", ""};
     final String [] PARSE_SINGLE_CORE = {"<- idle 366 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->", "<- idle 401 ->"};
-    final String [] PARSE_MULTI_CORE = { "", "", "<- idle 376 ->", "<- idle 807 ->", "<- idle 807 ->"};
+    final String [] PARSE_MULTI_CORE = { "", "", "", "<- idle 778 ->", "<- idle 807 ->"};
     final static String EXPECTED_FILE_GET_ALL_TRANS = getBaseResourcesDir() + "tmltranslator/expected/expected_get_all_transactions.txt";
     private String SIM_DIR;
+
     @BeforeClass
     public static void setUpBeforeClass() throws Exception {
         RESOURCES_DIR = getBaseResourcesDir() + "/tmltranslator/simulator/";
@@ -212,6 +213,7 @@ public class HTMLParseTest extends AbstractUITest {
 
         }
     }
+
     @Test
     public void testListAllTransactionsOfTask() throws Exception {
         for (int i = 0; i < 1; i++) {
diff --git a/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java b/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java
index 593e9ce61c6d0288faa9473aa7f50abf70f6de5f..c1c7763e13480f9cfaf7537bbb98f7a6a6ef90fc 100644
--- a/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java
+++ b/ttool/src/test/java/tmltranslator/MulticoreCrossCpuSchedulingTest.java
@@ -27,14 +27,23 @@ import static org.junit.Assert.assertTrue;
 
 public class MulticoreCrossCpuSchedulingTest extends AbstractUITest {
     final String DIR_GEN = "test_diplo_simulator/";
-    final String [] MODELS_CPU_CROSS = {"crossCpuScheduling"};
+    final String [] MODELS_CPU_CROSS = {"testMultiCore"};
     private String SIM_DIR;
-    final int [] NB_OF_CS_STATES = {29};
-    final int [] NB_OF_CS_TRANSTIONS = {28};
-    final int [] MIN_CS_CYCLES = {42};
-    final int [] MAX_CS_CYCLES = {42};
+    final int [] NB_OF_CS_STATES = {9};
+    final int [] NB_OF_CS_TRANSTIONS = {8};
+    final int [] MIN_CS_CYCLES = {65};
+    final int [] MAX_CS_CYCLES = {65};
+    static final String EXPECTED =
+            "MULTICORE: assign transaction Application__C1: Execi 15 t:0 l:15 (vl:15) params: to core 0\n" +
+            "MULTICORE: assign transaction Application__C0: Execi 10 t:15 l:10 (vl:10) params: to core 1\n" +
+            "MULTICORE: assign transaction Application__S: Execi 16 t:15 l:16 (vl:16) params: to core 0\n" +
+            "MULTICORE: assign transaction Application__S: Send Application__evt__Application__evt(evtFB) len:8 content:0 params: t:31 l:1 (vl:1) params: Ch: Application__evt__Application__evt to core 0\n" +
+            "MULTICORE: assign transaction Application__C3: Execi 40 t:25 l:40 (vl:40) params: to core 1\n" +
+            "MULTICORE: assign transaction Application__C0: Wait Application__evt__Application__evt params: t:32 l:1 (vl:1) params: Ch: Application__evt__Application__evt to core 0\n" +
+            "MULTICORE: assign transaction Application__C0: Execi 15 t:33 l:15 (vl:15) params: to core 0";
     static String CPP_DIR = "../../../../simulators/c++2/";
     static String mappingName = "Architecture";
+    private String actualResult = "";
     private TMLArchiDiagramPanel currTdp;
 
     @BeforeClass
@@ -156,14 +165,16 @@ public class MulticoreCrossCpuSchedulingTest extends AbstractUITest {
 
                 params[0] = "./" + SIM_DIR + "run.x";
                 params[1] = "-cmd";
-                params[2] = "1 6 10; 1 7 100 100 " + graphPath;
+                params[2] = "1 0; 1 7 100 100 " + graphPath;
                 proc = Runtime.getRuntime().exec(params);
                 proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
 
                 monitorError(proc);
 
                 while ((str = proc_in.readLine()) != null) {
-                    // TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
+                    if (str.contains("MULTICORE: assign transaction")) {
+                        actualResult += str;
+                    }
                     System.out.println("executing: " + str);
                 }
             } catch (Exception e) {
@@ -197,6 +208,9 @@ public class MulticoreCrossCpuSchedulingTest extends AbstractUITest {
             int maxValue = graph.getMaxValue("allCPUsFPGAsTerminated");
             System.out.println("executing: maxvalue of " + s + " " + maxValue);
             assertTrue(MAX_CS_CYCLES[i] == maxValue);
+
+            // compare which transaction belong to which core
+            assertTrue(EXPECTED.equals(actualResult));
         }
     }
 }
diff --git a/ttool/src/test/resources/tmltranslator/simulator/testMultiCore.xml b/ttool/src/test/resources/tmltranslator/simulator/testMultiCore.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a1c680928cd9feeef1d3ac6595c7cad7b0c55e28
--- /dev/null
+++ b/ttool/src/test/resources/tmltranslator/simulator/testMultiCore.xml
@@ -0,0 +1,570 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<TURTLEGMODELING version="1.0beta" ANIMATE_INTERACTIVE_SIMULATION="false" ACTIVATE_PENALTIES="false" UPDATE_INFORMATION_DIPLO_SIM="false" ANIMATE_WITH_INFO_DIPLO_SIM="true" OPEN_DIAG_DIPLO_SIM="false" LAST_SELECTED_MAIN_TAB="1" LAST_SELECTED_SUB_TAB="0">
+
+<Modeling type="TML Component Design" nameTab="Application" tabs="TML Component Task Diagram$C0$S$C1$C3" >
+<TMLComponentTaskDiagramPanel name="TML Component Task Diagram" minX="10" maxX="2500" minY="10" maxY="1500" channels="true" events="true" requests="true" zoom="1.0" >
+<CONNECTOR type="126" id="1" >
+<cdparam x="750" y="200" />
+<sizeparam width="0" height="0" minWidth="0" minHeight="0" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<infoparam name="connector" value="Connector between ports" />
+<P1  x="746" y="221" id="2" />
+<P2  x="419" y="227" id="13" />
+<AutomaticDrawing  data="true" />
+</CONNECTOR>
+<COMPONENT type="1202" id="12" >
+<cdparam x="759" y="154" />
+<sizeparam width="200" height="150" minWidth="150" minHeight="100" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Primitive component" value="S" />
+<custom data="LE||DSP||BRAM||WCET||" />
+<TGConnectingPoint num="0" id="4" />
+<TGConnectingPoint num="1" id="5" />
+<TGConnectingPoint num="2" id="6" />
+<TGConnectingPoint num="3" id="7" />
+<TGConnectingPoint num="4" id="8" />
+<TGConnectingPoint num="5" id="9" />
+<TGConnectingPoint num="6" id="10" />
+<TGConnectingPoint num="7" id="11" />
+<extraparam>
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ms" Operation="" />
+</extraparam>
+</COMPONENT>
+<SUBCOMPONENT type="1203" id="3" >
+<father id="12" num="0" />
+<cdparam x="746" y="208" />
+<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" />
+<infoparam name="Primitive port" value="Event evt" />
+<TGConnectingPoint num="0" id="2" />
+<extraparam>
+<Prop commName="evt" commType="1" origin="true" finite="true" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="0" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+</extraparam>
+</SUBCOMPONENT>
+
+<COMPONENT type="1202" id="23" >
+<cdparam x="206" y="140" />
+<sizeparam width="200" height="150" minWidth="150" minHeight="100" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Primitive component" value="C0" />
+<custom data="LE||DSP||BRAM||WCET||" />
+<TGConnectingPoint num="0" id="15" />
+<TGConnectingPoint num="1" id="16" />
+<TGConnectingPoint num="2" id="17" />
+<TGConnectingPoint num="3" id="18" />
+<TGConnectingPoint num="4" id="19" />
+<TGConnectingPoint num="5" id="20" />
+<TGConnectingPoint num="6" id="21" />
+<TGConnectingPoint num="7" id="22" />
+<extraparam>
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ms" Operation="" />
+</extraparam>
+</COMPONENT>
+<SUBCOMPONENT type="1203" id="14" >
+<father id="23" num="0" />
+<cdparam x="393" y="214" />
+<sizeparam width="26" height="26" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="-13" maxX="187" minY="-13" maxY="137" />
+<infoparam name="Primitive port" value="Event evt" />
+<TGConnectingPoint num="0" id="13" />
+<extraparam>
+<Prop commName="evt" commType="1" origin="false" finite="true" blocking="true" maxSamples="8" widthSamples="4" isLossy="false" isPrex="false" isPostex="false" lossPercentage="0" maxNbOfLoss="0" dataFlowType="int16_t" associatedEvent="" checkConf="false" checkConfStatus="0" checkAuth="false" checkWeakAuthStatus="0" checkStrongAuthStatus="0" vc="0" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+<Type type="0" typeOther="" />
+</extraparam>
+</SUBCOMPONENT>
+
+<COMPONENT type="1202" id="32" >
+<cdparam x="504" y="411" />
+<sizeparam width="200" height="150" minWidth="150" minHeight="100" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Primitive component" value="C3" />
+<custom data="LE||DSP||BRAM||WCET||" />
+<TGConnectingPoint num="0" id="24" />
+<TGConnectingPoint num="1" id="25" />
+<TGConnectingPoint num="2" id="26" />
+<TGConnectingPoint num="3" id="27" />
+<TGConnectingPoint num="4" id="28" />
+<TGConnectingPoint num="5" id="29" />
+<TGConnectingPoint num="6" id="30" />
+<TGConnectingPoint num="7" id="31" />
+<extraparam>
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ms" Operation="" />
+</extraparam>
+</COMPONENT>
+
+<COMPONENT type="1202" id="41" >
+<cdparam x="203" y="407" />
+<sizeparam width="200" height="150" minWidth="150" minHeight="100" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="Primitive component" value="C1" />
+<custom data="LE||DSP||BRAM||WCET||" />
+<TGConnectingPoint num="0" id="33" />
+<TGConnectingPoint num="1" id="34" />
+<TGConnectingPoint num="2" id="35" />
+<TGConnectingPoint num="3" id="36" />
+<TGConnectingPoint num="4" id="37" />
+<TGConnectingPoint num="5" id="38" />
+<TGConnectingPoint num="6" id="39" />
+<TGConnectingPoint num="7" id="40" />
+<extraparam>
+<Data isAttacker="No" daemon="false" periodic="false" periodValue="" unit="ms" Operation="" />
+</extraparam>
+</COMPONENT>
+
+
+</TMLComponentTaskDiagramPanel>
+
+<TMLActivityDiagramPanel name="C0" minX="10" maxX="2500" minY="10" maxY="1500" zoom="1.0" >
+<COMPONENT type="1001" id="43" >
+<cdparam x="399" y="281" />
+<sizeparam width="20" height="20" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="stop state" value="null" />
+<TGConnectingPoint num="0" id="42" />
+</COMPONENT>
+
+<COMPONENT type="1015" id="47" >
+<cdparam x="401" y="220" />
+<sizeparam width="10" height="30" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<enabled value="true" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="execIInterval" value="null" />
+<TGConnectingPoint num="0" id="45" />
+<TGConnectingPoint num="1" id="46" />
+</COMPONENT>
+<SUBCOMPONENT type="-1" id="44" >
+<father id="47" num="0" />
+<cdparam x="416" y="240" />
+<sizeparam width="51" height="15" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<cdrectangleparam minX="-75" maxX="30" minY="10" maxY="30" />
+<infoparam name="value of the time interval" value="[15, 15]" />
+<extraparam>
+<Interval minDelay="15" maxDelay="15" />
+</extraparam>
+</SUBCOMPONENT>
+
+<COMPONENT type="1010" id="50" >
+<cdparam x="374" y="168" />
+<sizeparam width="63" height="20" minWidth="30" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<enabled value="true" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="wait event" value="evt() " />
+<TGConnectingPoint num="0" id="48" />
+<TGConnectingPoint num="1" id="49" />
+<extraparam>
+<Data eventName="evt" nbOfParams="5" />
+</extraparam>
+</COMPONENT>
+
+<COMPONENT type="1013" id="54" >
+<cdparam x="401" y="105" />
+<sizeparam width="10" height="30" minWidth="1" minHeight="1" maxWidth="2000" maxHeight="2000" minDesiredWidth="0" minDesiredHeight="0" />
+<hidden value="false" />
+<enabled value="true" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
+<infoparam name="execI" value="null" />
+<TGConnectingPoint num="0" id="52" />
+<TGConnectingPoint num="1" id="53" />
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+<infoparam name="start state" value="null" />
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+</TMLActivityDiagramPanel>
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+<TMLActivityDiagramPanel name="S" minX="10" maxX="2500" minY="10" maxY="1500" zoom="1.0" >
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+<infoparam name="send event" value="evt()" />
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+
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+<Interval minDelay="16" maxDelay="16" />
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+</SUBCOMPONENT>
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+</TMLActivityDiagramPanel>
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+<cdrectangleparam minX="-75" maxX="30" minY="10" maxY="30" />
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+<extraparam>
+<Interval minDelay="15" maxDelay="15" />
+</extraparam>
+</SUBCOMPONENT>
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+</TMLActivityDiagramPanel>
+
+<TMLActivityDiagramPanel name="C3" minX="10" maxX="2500" minY="10" maxY="1500" zoom="1.0" >
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+<cdrectangleparam minX="-75" maxX="30" minY="10" maxY="30" />
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+<extraparam>
+<Interval minDelay="40" maxDelay="40" />
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+</CONNECTOR>
+
+</TMLActivityDiagramPanel>
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+</Modeling>
+
+
+
+
+<Modeling type="TML Architecture" nameTab="Architecture" >
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+<hidden value="false" />
+<cdrectangleparam minX="10" maxX="2500" minY="10" maxY="1500" />
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+<info stereotype="CPURRPB" nodeName="CPU0" />
+<attributes nbOfCores="2" byteDataSize="4"  schedulingPolicy="1"  sliceTime="10000"  goIdleTime="10"  maxConsecutiveIdleCycles="10"  pipelineSize="5"  taskSwitchingTime="20"  branchingPredictionPenalty="2"  cacheMiss="5" execiTime="1" execcTime="1" clockRatio="1" operation="" MECType="0" encryption="0"/>
+</extraparam>
+</COMPONENT>
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="244" minY="0" maxY="271" />
+<infoparam name="TGComponent" value="Application::C3" />
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+<TGConnectingPoint num="7" id="102" />
+<extraparam>
+<info value="Application::C3" taskName="C3" referenceTaskName="Application" priority="5" operationMEC="C3" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
+<SUBCOMPONENT type="1101" id="112" >
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="244" minY="0" maxY="271" />
+<infoparam name="TGComponent" value="Application::C0" />
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+<extraparam>
+<info value="Application::C0" taskName="C0" referenceTaskName="Application" priority="1" operationMEC="C0" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
+<SUBCOMPONENT type="1101" id="121" >
+<father id="155" num="2" />
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="244" minY="0" maxY="271" />
+<infoparam name="TGComponent" value="Application::C1" />
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+<extraparam>
+<info value="Application::C1" taskName="C1" referenceTaskName="Application" priority="0" operationMEC="C1" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
+<SUBCOMPONENT type="1101" id="130" >
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+<hidden value="false" />
+<cdrectangleparam minX="0" maxX="252" minY="0" maxY="271" />
+<infoparam name="TGComponent" value="Application::S" />
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+<info value="Application::S" taskName="S" referenceTaskName="Application" priority="1" operationMEC="S" fatherComponentMECType="0" />
+</extraparam>
+</SUBCOMPONENT>
+
+
+</TMLArchiDiagramPanel>
+
+</Modeling>
+
+
+
+
+</TURTLEGMODELING>
\ No newline at end of file