diff --git a/simulators/c++2/Makefile b/simulators/c++2/Makefile
index 500646b6db50cee77dab24507272c947f90735f7..3d6ee018b3369dbe14c573778c966727d6b0d4fa 100755
--- a/simulators/c++2/Makefile
+++ b/simulators/c++2/Makefile
@@ -24,7 +24,7 @@ OS := $(shell uname)
 
 MODULE = run
 include Makefile.src
-SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
+SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/OrderScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
 
 SRCS_base_DIR = src_simulator
 SRCS_generated = .
diff --git a/simulators/c++2/src_simulator/app/TMLTask.cpp b/simulators/c++2/src_simulator/app/TMLTask.cpp
index 42c96848a51730093fde352468e63b46965afef6..d85534b7c96cd7c548fe8da309fd1e918e1e0a66 100755
--- a/simulators/c++2/src_simulator/app/TMLTask.cpp
+++ b/simulators/c++2/src_simulator/app/TMLTask.cpp
@@ -358,7 +358,7 @@ unsigned int TMLTask::getState() const{
 }
 
 TMLTransaction* TMLTask::getNextTransaction(TMLTime iEndSchedule) const{
-	//std::cout << "Task::getNextTransaction\n";
+  std::cout<<"TMLTask get next trans"<<std::endl;
 	return (_currCommand==0)?0:_currCommand->getCurrTransaction();
 	//return (_currCommand==0 || _isScheduled)?0:_currCommand->getCurrTransaction();
 }
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index f37d5ffcb7258a6278c4b88912ee351338bded9a..464ee183e77c466af9262448bbd3c6b8a575a5c4 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -48,27 +48,21 @@
 
 
 FPGA::FPGA(    ID iID, 
-	       std::string iName,
+	       std::string iName,  
 	       WorkloadSource* iScheduler,
- 	       TMLTime iTimePerCycle, 
 	       TMLTime iReconfigTime, 
 	       unsigned int iChangeIdleModeCycles, 
 	       unsigned int iCyclesBeforeIdle,
 	       unsigned int iCyclesPerExeci, 
 	       unsigned int iCyclesPerExecc ) : SchedulableDevice(iID, iName, iScheduler)
-					      ,_timePerCycle(iTimePerCycle)
 					      ,_reconfigTime(iReconfigTime)
 					      ,_lastTransaction(0)
-#ifdef PENALTIES_ENABLED
-					      ,_changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
-#endif 
-#ifdef PENALTIES_ENABLED
-					      , _timePerExeci(_cyclesPerExeci * _timePerCycle /100.0)
-					      , _timeBeforeIdle(_cyclesBeforeIdle*_timePerCycle)
-					      , _changeIdleModeTime(_changeIdleModeCycles*_timePerCycle)
-#else
-					      , _timePerExeci(_cyclesPerExeci*_timePerCycle)
-#endif
+					      ,_changeIdleModeCycles(iChangeIdleModeCycles)
+					      ,_cyclesBeforeIdle(iCyclesBeforeIdle)
+					      ,_cyclesPerExeci(iCyclesPerExeci)
+					      ,_cyclesPerExecc(iCyclesPerExecc)
+					      ,_transNumber(0)
+					     
 {}
 
 FPGA::~FPGA(){}
@@ -78,8 +72,8 @@ void FPGA::streamBenchmarks(std::ostream& s) const{
   std::cout<<"test fpga stramBenchmarks"<<std::endl;
   s << TAG_FPGAo << " id=\"" << _ID << "\" name=\"" << _name << "\">" << std::endl;
   if (_simulatedTime!=0) s << TAG_UTILo << (static_cast<float>(_busyCycles)/static_cast<float>(_simulatedTime)) << TAG_UTILc;
-  s << TAG_ENERGYo << ( (_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle) << TAG_ENERGYc;
-  std::cout<< "power consumption "<< ((_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle)<< std::endl;
+  s << TAG_ENERGYo << ( (_simulatedTime)*_static_consumPerCycle) + ((_busyCycles)*_dynamic_consumPerCycle) << TAG_ENERGYc;
+  std::cout<< "power consumption "<< ((_simulatedTime)*_static_consumPerCycle) + ((_busyCycles)*_dynamic_consumPerCycle)<< std::endl;
   for(BusMasterList::const_iterator i=_busMasterList.begin(); i != _busMasterList.end(); ++i) (*i)->streamBenchmarks(s);
   s << TAG_FPGAc;
 }
@@ -87,44 +81,50 @@ void FPGA::streamBenchmarks(std::ostream& s) const{
 
 
 TMLTransaction* FPGA::getNextTransaction(){
-std::cout<<"fpga getNextTransaction"<<std::endl;
-#ifdef BUS_ENABLE
-  if(_masterNextTransaction==0 || _nextTransaction==0){
-    return _nextTransaction;
-   }
-  else{
+  std::cout<<"fpga getNextTransaction"<<_name<<" ";
+  #ifdef BUS_ENABLED
+  if (_masterNextTransaction==0 || _nextTransaction==0){
+    if(_masterNextTransaction == 0) std::cout<<"master is 0"<<std::endl;
+    if(_nextTransaction==0) std::cout<<"nexttrans is 0"<<std::endl;
+    //if(_nextTransaction)  std::cout<<_nextTransaction->toString()<<std::endl;
+     return _nextTransaction;
+     //return 0;
+  }else{
+#ifdef DEBUG_CPU
+    std::cout << "CPU:getNT: " << _name << " has bus transaction on master " << _masterNextTransaction->toString() << std::endl;
+#endif
+    //std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
     BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
+    std::cout << "1  aTempMaster: " << aTempMaster << std::endl;
     bool aResult = aTempMaster->accessGranted();
- 
+    // std::cout << "2" << std::endl;
     while (aResult && aTempMaster!=_masterNextTransaction){
-      
+      // std::cout << "3" << std::endl;
       aTempMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
-      
+      // std::cout << "4" << std::endl;
       aResult = aTempMaster->accessGranted();
- 
+      // std::cout << "5" << std::endl;
     }
+    if(_nextTransaction)std::cout<<"haha1"<<_nextTransaction->toString()<<std::endl;
     return (aResult)?_nextTransaction:0;
   }
 #else
+  if(_nextTransaction)std::cout<<"haha2"<<_nextTransaction->toString()<<std::endl;
+
   return _nextTransaction;
 #endif
  }
 
-void FPGA::calcStartTimeLength(TMLTime iTimeSlice){
-std::cout<<"fpga calStartTimeLength"<<std::endl;
+void FPGA::calcStartTimeLength(){
+  std::cout<<"fpga calStartTimeLength "<<std::endl;
   
 #ifdef BUS_ENABLED
   
   std::cout << "FPGA:calcSTL: scheduling decision of FPGA " << _name << ": " << _nextTransaction->toString() << std::endl;
-  std::cout << "get channel " << std::endl;
   TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
-  std::cout << "after get channel " << std::endl;
   if (aChannel==0) {
-    std::cout<<"test111"<<std::endl;
-    //std::cout << "no channel " << std::endl;
     _masterNextTransaction=0;
   } else {
-    std::cout << "get bus " << std::endl;
     _masterNextTransaction= getMasterForBus(aChannel->getFirstMaster(_nextTransaction));
     if (_masterNextTransaction!=0){
       std::cout << "before register transaction at bus " << _masterNextTransaction->toString() << std::endl;
@@ -135,38 +135,18 @@ std::cout<<"fpga calStartTimeLength"<<std::endl;
     }
   }
 #endif
-  std::cout<<"test222"<<std::endl;
   //round to full cycles!!!
-  std::cout<<"time per cycle is "<<_timePerCycle<<std::endl;
-  std::cout<<"test333"<<std::endl;
-  TMLTime aStartTime = _nextTransaction->getRunnableTime();
-  TMLTime aReminder = aStartTime % _timePerCycle;
-  if (aReminder!=0) aStartTime+=_timePerCycle - aReminder;
-  std::cout << "FPGA: set start time in FPGA=" << aStartTime << " Reminder=" << aReminder <<"\n";
 
+  TMLTime aStartTime = _nextTransaction->getRunnableTime();
+  std::cout<<"start time !!!!!!!!!!"<<_nextTransaction->toShortString()<<"is "<<aStartTime<<std::endl;
+  //or setStartTime(0)???
   _nextTransaction->setStartTime(aStartTime);
 
 #ifdef BUS_ENABLED
   if (_masterNextTransaction==0){
-#endif
-    //calculate length of transaction
-    //if (_nextTransaction->getOperationLength()!=-1){
-    std::cout<<"at first virtual length "<<_nextTransaction->getVirtualLength()<<std::endl;
-    std::cout<<"another "<<(TMLLength)(iTimeSlice /_timePerExeci)<<std::endl;
-    if (iTimeSlice!=0){
-      _nextTransaction->setVirtualLength(max(min(_nextTransaction->getVirtualLength(), (TMLLength)(iTimeSlice /_timePerExeci)), (TMLTime)1));
-    }
-    _nextTransaction->setLength(_nextTransaction->getVirtualLength()*_timePerExeci);
-    std::cout<<"!!!!!virtual length is "<<_nextTransaction->getVirtualLength()<<std::endl;
-#ifdef BUS_ENABLED
-  }
-#endif
-#ifdef PENALTIES_ENABLED
-  //std::cout << "starttime=" <<  _nextTransaction->getStartTime() << "\n";
-  if ((_nextTransaction->getStartTime()-_endSchedule) >=_timeBeforeIdle){
-    _nextTransaction->setIdlePenalty(_changeIdleModeTime);
+#endif  
+    _nextTransaction->setLength(max(_nextTransaction->getVirtualLength(),(TMLTime)1));
   }
-#endif
 }
 
 void FPGA::truncateAndAddNextTransAt(TMLTime iTime){
@@ -175,7 +155,7 @@ std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
   //return truncateNextTransAt(iTime);
   //not a problem if scheduling does not take place at time when transaction is actually truncated, tested
   //std::cout << "CPU:truncateAndAddNextTransAt " << _name << "time: +++++++++++++++++++++" << iTime << "\n";
-  TMLTime aTimeSlice = _scheduler->schedule(iTime);
+//  TMLTime aTimeSlice = _scheduler->schedule(iTime);
   //_schedulingNeeded=false;  05/05/11
   TMLTransaction* aNewTransaction =_scheduler->getNextTransaction(iTime);
   //std::cout << "before if\n";
@@ -188,7 +168,7 @@ std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
     //if (_nextTransaction!=0 && truncateNextTransAt(iTime)!=0) addTransaction(); //NEW!!!!
     if (_nextTransaction!=0 && _masterNextTransaction!=0) _masterNextTransaction->registerTransaction(0);
     _nextTransaction = aNewTransaction;
-    if (_nextTransaction!=0) calcStartTimeLength(aTimeSlice);
+    if (_nextTransaction!=0) calcStartTimeLength();
   }
   //std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
 }
@@ -196,30 +176,10 @@ std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
 TMLTime FPGA::truncateNextTransAt(TMLTime iTime){
 std::cout<<"fpga truncateNextTransAt"<<std::endl;
   if (_masterNextTransaction==0){
-#ifdef PENALTIES_ENABLED
-
-    //std::cout << "CPU:nt.startTime: " << _nextTransaction->getStartTime() << std::endl;
-    if (iTime < _nextTransaction->getStartTime()) {
-      return 0;
-    }
-
-    TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
-    TMLTime aStaticPenalty = _nextTransaction->getIdlePenalty() + _nextTransaction->getTaskSwitchingPenalty();
-    if (aNewDuration<=aStaticPenalty){
-      _nextTransaction->setLength(_timePerExeci);
-      _nextTransaction->setVirtualLength(1);
-
-    } else{
-      aNewDuration-=aStaticPenalty;
-      _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration /_timePerExeci),(TMLTime)1));
-      _nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
-    }
-#else
     if (iTime <= _nextTransaction->getStartTime()) return 0;  //before: <=
     TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
-    _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration /_timePerExeci), (TMLTime)1));
-    _nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
-#endif
+    _nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration), (TMLTime)1));
+    _nextTransaction->setLength(_nextTransaction->getVirtualLength());
   }
   return _nextTransaction->getOverallLength();
 }
@@ -235,41 +195,45 @@ std::cout<<"fpga addTransaction"<<std::endl;
   }else{
     BusMaster* aFollowingMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
     if (aFollowingMaster==0){
-      std::cout << "1\n";
+      //std::cout << "1\n";
       aFinish=true;
       BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
-      std::cout << "2\n";
+      // std::cout << "2\n";
       Slave* aTempSlave= _nextTransaction->getChannel()->getNextSlave(_nextTransaction);
-      std::cout << "3\n";
-      aTempMaster->addBusContention(_nextTransaction->getStartTime()-max(_endSchedule,_nextTransaction->getRunnableTime()));
+      //std::cout << "3\n";
       while (aTempMaster!=0){
-        std::cout << "3a\n";
+	// std::cout << "3a\n";
         aTempMaster->addTransaction(_nextTransaction);
-        std::cout << "3b\n";
+	// std::cout << "3b\n";
         //if (aTempSlave!=0) aTempSlave->addTransaction(_nextTransaction);
         if (aTempSlave!=0) aTempSlave->addTransaction(_nextTransaction);  //NEW
-        std::cout << "4\n";
+        //std::cout << "4\n";
         aTempMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
-        std::cout << "5\n";
+        //std::cout << "5\n";
         aTempSlave= _nextTransaction->getChannel()->getNextSlave(_nextTransaction);
       }
-      std::cout << "6\n";
+      // std::cout << "6\n";
     } else {
       std::cout << _name << " bus transaction next round" << std::endl;
       _masterNextTransaction=aFollowingMaster;
-      std::cout << "7\n";
+      // std::cout << "7\n";
       _masterNextTransaction->registerTransaction(_nextTransaction);
       aFinish=false;
     }
     //std::cout << "8\n";
   }
+ 
   if (aFinish){
+    //std::cout<<"I am in finish!!!"<<std::endl;
     _endSchedule=0;
     _simulatedTime=max(_simulatedTime,_endSchedule);
     _overallTransNo++; //NEW!!!!!!!!
     _overallTransSize+=_nextTransaction->getOperationLength();  //NEW!!!!!!!!
     //std::cout << "lets crash execute\n";
-    _nextTransaction->getCommand()->execute();  //NEW!!!!
+
+    // std::cout<<_nextTransaction->toString()<<std::endl;
+    if(_nextTransaction->getCommand()==0) std::cout<<"d"<<std::endl;
+     _nextTransaction->getCommand()->execute();  //NEW!!!!
     //std::cout << "not crashed\n";
 #ifdef TRANSLIST_ENABLED
     _transactList.push_back(_nextTransaction);
@@ -279,29 +243,41 @@ std::cout<<"fpga addTransaction"<<std::endl;
 #ifdef LISTENERS_ENABLED
     NOTIFY_TRANS_EXECUTED(_nextTransaction);
 #endif
+  
     _nextTransaction=0;
+
     return true;
   } else return false;
 }
 
+
 void FPGA::schedule(){ 
   
   std::cout << "fpga:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
-  
-  TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
-  
+  _scheduler->schedule(_endSchedule);
   TMLTransaction* aOldTransaction = _nextTransaction;
   _nextTransaction=_scheduler->getNextTransaction(_endSchedule);
-
-  if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW
-  
+  /* TaskList::const_iterator iter_task=_taskList.begin();
+  std::advance(iter_task,_transNumber);
+   if(iter_task!=_taskList.end()){    
+     _nextTransaction=(*iter_task)->getNextTransaction(_endSchedule);
+    if(_nextTransaction!=0 && _nextTransaction->getVirtualLength()==0){
+      _nextTransaction=0;
+      _transNumber=0;
+    }
+    else if(++iter_task==_taskList.end())
+      _transNumber=0;
+    else if(_nextTransaction->getCommand()->getProgress()==_nextTransaction->getLength())
+      _transNumber++;
+   }
+  */
+  if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW 
     if (_masterNextTransaction!=0) {
       _masterNextTransaction->registerTransaction(0);
 
     }
   }
-
-  if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
+  if (_nextTransaction!=0 && aOldTransaction != _nextTransaction)  calcStartTimeLength();
   std::cout << "fpga:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
 }
 
@@ -433,5 +409,168 @@ void FPGA::latencies2XML(std::ostringstream& glob, unsigned int id1, unsigned in
   return;
 }
 
+double FPGA::averageLoad (TMLTask* currTask) const{
+  double _averageLoad=0;
+  TMLTime _maxEndTime=0;
+  for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+    if( (*i)-> getCommand()->getTask() == currTask ){
+      TMLTime _endTime= (*i)->getEndTime();
+      _maxEndTime=max(_maxEndTime,_endTime);
+    }
+  }
+  for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+     if( (*i)-> getCommand()->getTask() == currTask ){
+      _averageLoad += (*i)->getEndTime() - (*i)->getStartTime();
+    }
+  }
+  if(_maxEndTime == 0)
+    return 0;
+  else {
+    _averageLoad = (double)_averageLoad/_maxEndTime;
+    return _averageLoad;
+  }
+  /*if( _maxEndTime == 0 ) 
+    myfile << "average load is 0" << "<br>";
+  else
+  myfile<<" average load is "<<(double)_averageLoad/_maxEndTime<<"<br>";*/
+ 
+}
+
+
+void FPGA::drawPieChart(std::ofstream& myfile) const {
+  std::cout<<"fpga drawpie chart"<<std::endl;
+   TMLTime _maxEndTime=0;
+   for(TaskList::const_iterator j =_taskList.begin(); j != _taskList.end(); ++j){
+     for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+       if( (*i)-> getCommand()->getTask() == (*j) ){
+	 TMLTime _endTime= (*i)->getEndTime();
+	 _maxEndTime=max(_maxEndTime,_endTime);
+       }
+     }
+     std::cout<<"max end time is "<<_maxEndTime<<std::endl;
+     std::map <TMLTask*, double > transPercentage;
+     for( TransactionList::const_iterator i = _transactList.begin(); i!= _transactList.end(); ++i){
+       if( (*i)-> getCommand()->getTask() == (*j) ){
+	 transPercentage[(*i)-> getCommand()->getTask()]+=(double)((*i)->getEndTime()-(*i)->getStartTime())/_maxEndTime;      
+       }
+     }
+     std::map <TMLTask*, double>::iterator iter = transPercentage.begin();
+     myfile << "     var chart" << _ID << "_" << (*j)->toShortString() << "= new CanvasJS.Chart(\"chartContainer" << _ID << "_" <<  (*j)->toShortString() <<"\"," << std::endl;
+     myfile <<  SCHED_HTML_JS_CONTENT2 << "Average load is " << averageLoad(*j) <<  SCHED_HTML_JS_CONTENT3 << std::endl;
+     double idle=1;
+     while( iter != transPercentage.end()){
+       myfile << "                { y:" << (iter->second)*100 << ", indexLabel: \"" << iter->first->toString() << "\" }," << std::endl;
+       idle-=iter->second;
+       ++iter;  
+     }
+     myfile << "                { y:" << idle*100 << ", indexLabel: \"idle time\"" << " }" << std::endl;
+     myfile << std::endl;
+     myfile << SCHED_HTML_PIE_END;
+     myfile << "chart" << _ID << "_" <<  (*j)->toShortString() << ".render();" << std::endl;
+   }
+  
+}
+
+void FPGA::showPieChart(std::ofstream& myfile) const{
+  myfile << SCHED_HTML_JS_DIV_ID << _ID << "_" << _htmlCurrTask->toShortString() << SCHED_HTML_JS_DIV_END << "<br>";
+}
+  
+void FPGA::schedule2HTML(std::ofstream& myfile) const {  
+  myfile << "<h2><span>Scheduling for device: "<< _name << "</span></h2>" << std::endl;
+
+  if ( _transactList.size() == 0 ) {
+    myfile << "<h4>Device never activated</h4>" << std::endl;
+  }
+   else {
+    myfile << "<table>" << std::endl << "<tr>";
+
+    std::map<TMLTask*, std::string> taskCellClasses;
+    unsigned int nextCellClassIndex = 0;
+    TMLTime aCurrTime = 0;
+
+    for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+      std::cout <<  (*i)-> getCommand()->getTask()->toString() <<std::endl;
+      std::cout<< _htmlCurrTask->toString()<<std::endl;
+      if( (*i)-> getCommand()->getTask() == _htmlCurrTask ){
+	std::cout<<"in!!"<<_htmlCurrTask->toString()<<std::endl;
+	TMLTransaction* aCurrTrans = *i;
+	unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
+	std::cout<<"blank is "<<aBlanks<<std::endl;
+	if ( aBlanks > 0 ) {
+	  writeHTMLColumn( myfile, aBlanks, "not", "idle time" );
+	}
+
+	unsigned int aLength = aCurrTrans->getOperationLength();
+
+
+	// Issue #4
+	TMLTask* task = aCurrTrans->getCommand()->getTask();
+	std::cout<<"what is this task?"<<task->toString()<<std::endl;
+	const std::string cellClass = determineHTMLCellClass( taskCellClasses, task, nextCellClassIndex );
+
+	writeHTMLColumn( myfile, aLength, cellClass, aCurrTrans->toShortString() );
+
+	aCurrTime = aCurrTrans->getEndTime();
+      }
+    }
+		
+
+    myfile << "</tr>" << std::endl << "<tr>";
+
+    for ( unsigned int aLength = 0; aLength < aCurrTime; aLength++ ) {
+      myfile << "<th></th>";
+    }
+
+    myfile << "</tr>" << std::endl << "<tr>";
+
+    for ( unsigned int aLength = 0; aLength <= aCurrTime; aLength += 5 ) {
+      std::ostringstream spanVal;
+      spanVal << aLength;
+      writeHTMLColumn( myfile, 5, "sc", "", spanVal.str(), false );
+      //myfile << "<td colspan=\"5\" class=\"sc\">" << aLength << "</td>";
+    }
+
+    myfile << "</tr>" << std::endl << "</table>" << std::endl << "<table>" << std::endl << "<tr>";
+
+    for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
+      TMLTask* task = (*taskColIt).first;
+      // Unset the default td max-width of 5px. For some reason setting the max-with on a specific t style does not work
+      myfile << "<td class=\"" << taskCellClasses[ task ] << "\"></td><td style=\"max-width: unset;\">" << task->toString() << "</td><td class=\"space\"></td>";
+    }
+
+    myfile << "</tr>" << std::endl;
+
+#ifdef ADD_COMMENTS
+    bool aMoreComments = true, aInit = true;
+    Comment* aComment;
+
+    while ( aMoreComments ) {
+      aMoreComments = false;
+      myfile << "<tr>";
+
+      for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
+	//for(TaskList::const_iterator j=_taskList.begin(); j != _taskList.end(); ++j){
+	TMLTask* task = (*taskColIt).first;
+	std::string aCommentString = task->getNextComment( aInit, aComment );
+
+	if ( aComment == 0 ) {
+	  myfile << "<td></td><td></td><td class=\"space\"></td>";
+	}
+	else {
+	  replaceAll(aCommentString,"<","&lt;");
+	  replaceAll(aCommentString,">","&gt;");
+	  aMoreComments = true;
+	  myfile << "<td style=\"max-width: unset;\">" << aComment->_time << "</td><td><pre>" << aCommentString << "</pre></td><td class=\"space\"></td>";
+	}
+      }
+
+      aInit = false;
+      myfile << "</tr>" << std::endl;
+    }
+#endif
+    myfile << "</table>" << std::endl;
+   }
+  std::cout<<"end in!!!"<<std::endl;
+}
 
 
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index e7aa72e06db2c45d7bda7e23c44175855034460a..26b652f550cf7b08fa070c32663562fd71c5f720 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -71,9 +71,6 @@ public:
 	\param iID ID of the device
 	\param iName Name of the device
 	\param iScheduler Pointer to the scheduler object
-	\param iTimePerCycle 1/Processor frequency
-	\param iMapCapacity Pointer to the overall mapping capacity ????
-	\param iMapPenalty Pointer to the mapping penalty  ????
 	\param iReconfigTime reconfiguration time
 	\param iChangeIdleModeCycles Cycles needed to switch into indle mode
 	\param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle
@@ -81,7 +78,7 @@ public:
 	\param iCyclesPerExecc Cycles needed to execute one EXECC unit
 	*/
 	
-        FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iTimePerCycle, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
+        FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
 	///Destructor
 	virtual ~FPGA();
 	///Determines the next FPGA transaction to be executed
@@ -130,10 +127,18 @@ public:
 		_taskList.push_back(iTask);
 		if (_scheduler!=0) _scheduler->addWorkloadSource(iTask);
 	}
+	inline void setTransNumber(unsigned int num) { _transNumber=num;}
+	inline unsigned int getTransNumber() { return _transNumber;}
+	double averageLoad (TMLTask* currTask) const;
+	void drawPieChart(std::ofstream& myfile) const;
+	void showPieChart(std::ofstream& myfile) const;
+	void schedule2HTML(std::ofstream& myfile) const;
+	inline const TaskList& getTaskList() const{return _taskList;}
+	inline void setHtmlCurrTask(TMLTask *t) { _htmlCurrTask=t;}
 protected:
 	///List of all tasks running on the FPGA
 	TaskList _taskList;
-	
+	TMLTask* _htmlCurrTask;
 	/**
 	\param iTime Indicates at what time the transaction should be truncated
 	*/
@@ -142,12 +147,11 @@ protected:
 	/**
 	\param iTimeSlice FPGA Time slice granted by the scheduler
 	*/
-	void calcStartTimeLength(TMLTime iTimeSlice);
-	///1/Processor frequency
-	TMLTime _timePerCycle;
+	void calcStartTimeLength();
 
 	TMLTime _reconfigTime;
 
+
 	///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
 	/**
 	\param iDummy Dummy Bus Master
@@ -159,22 +163,25 @@ protected:
 	TMLTransaction* _lastTransaction;
 	///List of bus masters
 	BusMasterList _busMasterList;
-#ifdef PENALTIES_ENABLED		
+
+ 		
 	///Cycles needed to switch to idle mode
 	unsigned int _changeIdleModeCycles;
 	///Idle cycles which elapse before entering idle mode
 	unsigned int _cyclesBeforeIdle;
-#endif
+ 
 	///Cycles needed to execute one execi unit
 	unsigned int _cyclesPerExeci;
+	unsigned int _cyclesPerExecc;
 	///Time needed to execute one execi unit
 	float _timePerExeci;
-#ifdef PENALTIES_ENABLED
+ 
 	///Idle time which elapses before entering idle mode
 	TMLTime _timeBeforeIdle;
 	///Time needed to switch into idle mode
 	TMLTime _changeIdleModeTime;
-#endif
+	unsigned int _transNumber;
+ 		
 	///State variable for the VCD output
 	vcdFPGAVisState _vcdOutputState;
 };
diff --git a/simulators/c++2/src_simulator/arch/OrderScheduler.cpp b/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..ef5ca41d56aceb64c40132fbd902e8c66c997e22
--- /dev/null
+++ b/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
@@ -0,0 +1,94 @@
+/*Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Niu Siyuan,
+Ludovic Apvrille, Renaud Pacalet
+ *
+ * ludovic.apvrille AT telecom-paristech.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL  license under French law and
+ * abiding by the rules of distribution of free software.  You can  use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and  rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty  and the software's author,  the holder of the
+ * economic rights,  and the successive licensors  have only  limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading,  using,  modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean  that it is complicated to manipulate,  and  that  also
+ * therefore means  that it is reserved for developers  and  experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and,  more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ *
+ */
+#include<OrderScheduler.h>
+#include <TMLTransaction.h>
+
+OrderScheduler::OrderScheduler(const std::string& iName, Priority iPrio): WorkloadSource(iPrio), _name(iName), _nextTransaction(0) {
+}
+
+OrderScheduler::OrderScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources): WorkloadSource(iPrio, aSourceArray, iNbOfSources), _name(iName), _nextTransaction(0), _lastSource(0) {
+}
+
+TMLTime OrderScheduler::schedule(TMLTime iEndSchedule){
+	TaskList::iterator i;
+	TMLTransaction *aMarkerPast=0, *aMarkerFuture=0,*aTempTrans;
+	TMLTime aTransTimeFuture=-1,aRunnableTime;
+	WorkloadSource *aSourcePast=0, *aSourceFuture=0;  //NEW
+	for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
+		(*i)->schedule(iEndSchedule);
+		aTempTrans=(*i)->getNextTransaction(iEndSchedule);
+		if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0){
+			aRunnableTime=aTempTrans->getRunnableTime();	
+			if (aRunnableTime<=iEndSchedule){
+			  //Past
+
+			  aMarkerPast=aTempTrans;
+			  aSourcePast=*i; //NEW
+		        
+			}else{
+			  //Future
+		        
+			  aTransTimeFuture=aRunnableTime;
+			  aMarkerFuture=aTempTrans;
+			  aSourceFuture=*i; //NEW
+		        
+				
+			}
+		}
+		     
+	}
+	if (aMarkerPast==0){
+		_nextTransaction=aMarkerFuture;
+		_lastSource=aSourceFuture; //NEW
+	}else{
+		_nextTransaction=aMarkerPast;
+		_lastSource=aSourcePast; //NEW
+	}
+	return 0;
+}
+
+OrderScheduler::~OrderScheduler(){
+	std::cout << _name << ": Scheduler deleted\n";
+}
+
+void OrderScheduler::reset(){
+	WorkloadSource::reset();
+	_nextTransaction=0;
+}
diff --git a/simulators/c++2/src_simulator/arch/OrderScheduler.h b/simulators/c++2/src_simulator/arch/OrderScheduler.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c0888f3802f60d8d0913d0b84d65260a34b3f76
--- /dev/null
+++ b/simulators/c++2/src_simulator/arch/OrderScheduler.h
@@ -0,0 +1,77 @@
+/*Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Niu Siyuan,
+Ludovic Apvrille, Renaud Pacalet
+ *
+ * ludovic.apvrille AT telecom-paristech.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL  license under French law and
+ * abiding by the rules of distribution of free software.  You can  use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and  rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty  and the software's author,  the holder of the
+ * economic rights,  and the successive licensors  have only  limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading,  using,  modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean  that it is complicated to manipulate,  and  that  also
+ * therefore means  that it is reserved for developers  and  experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and,  more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ *
+ */
+#ifndef PrioSchedulerH
+#define PrioSchedulerH
+#include <WorkloadSource.h>
+
+class TMLTransaction;
+
+///Fixed priority based scheduler
+class OrderScheduler: public WorkloadSource{
+public:
+	///Constructor
+    	/**
+	\param iName Name of the scheduler
+      	\param iPrio Priority of the scheduler
+    	*/
+	OrderScheduler(const std::string& iName, Priority iPrio);
+	///Constructor
+    	/**
+	\param iName Name of the scheduler
+      	\param iPrio Priority of the scheduler
+	\param aSourceArray Array of pointers to workload ressources from which transactions may be received
+	\param iNbOfSources Length of the array
+    	*/
+	OrderScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources);
+	~OrderScheduler();
+	TMLTime schedule(TMLTime iEndSchedule);
+	inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
+	inline std::string toString() const {return _name;}
+	void reset();
+	//void transWasScheduled(SchedulableDevice* iDevice);
+protected:
+	///Name of the scheduler
+	std::string _name;
+	///Next transaction to be executed
+	TMLTransaction* _nextTransaction;
+	///Last workload source to which ressource access was granted
+	WorkloadSource* _lastSource;
+};
+#endif
diff --git a/simulators/c++2/src_simulator/arch/RRScheduler.cpp b/simulators/c++2/src_simulator/arch/RRScheduler.cpp
index e6a025c019ec2fd523aba1dbc3a071189ef46bd4..804ecab31baf3e6e759636ff86c9ef4311fa5326 100644
--- a/simulators/c++2/src_simulator/arch/RRScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/RRScheduler.cpp
@@ -123,7 +123,9 @@ TMLTime RRScheduler::schedule(TMLTime iEndSchedule){
 	//	_nextTransaction->setLength(min(_nextTransaction->getOperationLength(), _timeSlice-_elapsedTime));
 	//}
 	//std::cout << "End schedule\n" ;
+
 	return _timeSlice-_elapsedTime;
+       
 }
 
 //TMLTransaction* RRScheduler::getNextTransaction(TMLTime iEndSchedule) const{
diff --git a/simulators/c++2/src_simulator/arch/RRScheduler.h b/simulators/c++2/src_simulator/arch/RRScheduler.h
index 1291fd2d42f2260ed81f7d998b36c576f3c2a17b..d80bd381b4d8fa1847df872e0d1aa6a25ea772f4 100644
--- a/simulators/c++2/src_simulator/arch/RRScheduler.h
+++ b/simulators/c++2/src_simulator/arch/RRScheduler.h
@@ -69,7 +69,7 @@ public:
 	///Destructor
 	~RRScheduler();
 	TMLTime schedule(TMLTime iEndSchedule);
-	inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
+	inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {if(_nextTransaction) std::cout<<"rr next trans"<<std::endl;return _nextTransaction;}
 	void reset();
 	std::istream& readObject(std::istream &is);
 	std::ostream& writeObject(std::ostream &os);
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index 8522156a00b19edb9a814f4ef7955f3aa7f5f3e2..3e50eac625004ae13f30fa5ec84f16300c7ede59 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -191,13 +191,14 @@ std::string SchedulableDevice::determineHTMLCellClass( 	std::map<TMLTask*, std::
 
 
 double SchedulableDevice::averageLoad() const{
+  std::cout<<"average load"<<std::endl;
   double _averageLoad=0;
   TMLTime _maxEndTime=0;
   for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
       TMLTime _endTime= (*i)->getEndTime();
       _maxEndTime=max(_maxEndTime,_endTime);
   }
-  std::cout<<"max end time is "<<_maxEndTime<<std::endl;
+  // std::cout<<"max end time is "<<_maxEndTime<<std::endl;
   for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
      _averageLoad += (*i)->getEndTime() - (*i)->getStartTime();  
   
diff --git a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
index f0ada248717b0bb94dbcba478a723acb7f38cadb..f36d97a4536efdc046e54b255870600e3d26c6a3 100644
--- a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
@@ -311,12 +311,14 @@ std::cout<<"addTransaction"<<std::endl;
 
 void SingleCoreCPU::schedule(){
   //std::cout <<"Hello\n";
-  std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+  // std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+  std::cout<<"CPU schedule"<<std::endl;
   TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
-  //_schedulingNeeded=false;  05/05/11
-  //std::cout << "1\n";
+
   TMLTransaction* aOldTransaction = _nextTransaction;
   _nextTransaction=_scheduler->getNextTransaction(_endSchedule);
+  if(_nextTransaction) std::cout<<"next trans is "<<_nextTransaction->toShortString()<<std::endl;
+  else std::cout<<"next trans is 0"<<std::endl;
   //std::cout << "2\n";
 
   //_scheduler->transWasScheduled(this); //NEW 05/05/11
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index bb0683206c8c5f8f380ba5e219a56d7527b84f5b..71ac78db506b94bced1a9e94a60375305333a74a 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -46,6 +46,7 @@
 #include <SimComponents.h>
 #include <IndeterminismSource.h>
 #include <CPU.h>
+#include <FPGA.h>
 #include <TMLTask.h>
 #include <TMLChannel.h>
 #include <ServerIF.h>
@@ -79,7 +80,8 @@ TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevi
 #endif
   //for(SchedulingList::const_iterator i=_simComp->_cpuList.begin(); i != _simComp->_cpuList.end(); ++i){
   //for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
-  for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+  // for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+  for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
     aTempDevice=*i;
     aTempTrans=aTempDevice->getNextTransaction();
     if (aTempTrans!=0 && aTempTrans->getVirtualLength()>0){
@@ -87,10 +89,13 @@ TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevi
       std::cout << "kernel:getTLET: transaction found on " << aTempDevice->toString() << ": " << aTempTrans->toString() << std::endl;
 #endif
       //tmp++;
+      std::cout<<aTempTrans->toShortString()<<"getEndtime is "<<aTempTrans->getEndTime()<<std::endl;
+      std::cout<<"alowest time is "<<aLowestTime<<std::endl;
       if (aTempTrans->getEndTime() < aLowestTime){
+	std::cout<<"in!!!"<<std::endl;
         aMarker=aTempTrans;
         aLowestTime=aTempTrans->getEndTime();
-        oResultDevice=aTempDevice;
+        oResultDevice=aTempDevice;     
       }
     }
     //#ifdef DEBUG_KERNEL
@@ -247,7 +252,8 @@ void Simulator::schedule2TXT(std::string& iTraceFileName) const{
   std::ofstream myfile(iTraceFileName.c_str());
   if (myfile.is_open()){
     //for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
-    for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+    //for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+    for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
       (*i)->schedule2TXT(myfile);
     }
     //for(BusList::const_iterator j=_simComp->getBusIterator(false); j != _simComp->getBusIterator(true); ++j){
@@ -362,6 +368,9 @@ std::cout<<"schedule2HTML--------------------------------------*****************
     for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
       (*i)->drawPieChart(myfile);
     }
+    for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
+      (*i)->drawPieChart(myfile);
+    }
     for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
       (*j)->drawPieChart(myfile);
     }
@@ -387,6 +396,16 @@ std::cout<<"schedule2HTML--------------------------------------*****************
     }
     jsfile.close();
     
+    for(FPGAList::const_iterator j=_simComp->getFPGAList().begin(); j != _simComp->getFPGAList().end(); ++j){     
+      for(TaskList::const_iterator i = (*j)->getTaskList().begin(); i != (*j)->getTaskList().end(); ++i){
+      	(*j)->setHtmlCurrTask(*i);
+	std::cout<<"begin fpga html "<<(*j)->toShortString()<<std::endl;
+	(*j)->schedule2HTML(myfile);
+	std::cout<<"end fpga html "<<(*j)->toShortString()<<std::endl;
+	(*j)->showPieChart(myfile);
+      }
+    }
+    
     for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
       (*j)->schedule2HTML(myfile);     
       (*j)->showPieChart(myfile);
@@ -554,21 +573,23 @@ bool Simulator::channelImpactsCommand(TMLChannel* iCh, TMLCommand* iCmd){
 }
 
 bool Simulator::simulate(TMLTransaction*& oLastTrans){
-  TMLTransaction* depTransaction,*depCPUnextTrans,*transLET;
-  TMLCommand* commandLET,*depCommand,*depCPUnextCommand;
+  //TMLTransaction* depTransaction,*depCPUnextTrans,*transLET;
+  //TMLCommand* commandLET,*depCommand,*depCPUnextCommand;
+  TMLTransaction* depTransaction,*depFPGAnextTrans,*transLET;
+  TMLCommand* commandLET,*depCommand,*depFPGAnextCommand;
   TMLTask* depTask;
-  SchedulableDevice* cpuLET;
-  CPU* depCPU;
+  // SchedulableDevice* cpuLET;
+  // CPU* depCPU;
+  SchedulableDevice* fpgaLET;
+  FPGA* depFPGA;
 #ifdef DEBUG_KERNEL
   std::cout << "kernel:simulate: first schedule" << std::endl;
 #endif
   _simComp->setStopFlag(false,"");
-  //std::cout << "before loop " << std::endl;
+
   //for(TaskList::const_iterator i=_simComp->getTaskIterator(false); i!=_simComp->getTaskIterator(true);i++){
   for(TaskList::const_iterator i=_simComp->getTaskList().begin(); i!=_simComp->getTaskList().end();i++){
-    //std::cout << "loop it " << (*i)->toString() << std::endl;
     if ((*i)->getCurrCommand()!=0) (*i)->getCurrCommand()->prepare(true);
-    //std::cout << "loop it end" << (*i)->toString() << std::endl;
   }
   //std::cout << "after loop1" << std::endl;
 #ifdef EBRDD_ENABLED
@@ -580,10 +601,15 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
   //for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::setRescheduleFlag));
   //for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::schedule));
   std::cout<<"simulate"<<std::endl;
-  for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
-  //std::cout << "after schedule" << std::endl;
-  transLET=getTransLowestEndTime(cpuLET);	      
-  //std::cout << "after getTLET" << std::endl;
+  //for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
+   for_each(_simComp->getFPGAList().begin(), _simComp->getFPGAList().end(),std::mem_fun(&FPGA::schedule));
+   std::cout<<"simulate schedule end!!!"<<std::endl;
+
+  //transLET=getTransLowestEndTime(cpuLET);
+   std::cout<<"simulator get next transaction begin"<<std::endl;
+  transLET=getTransLowestEndTime(fpgaLET);
+  std::cout<<"simulator get next transaction end"<<std::endl;
+
 #ifdef LISTENERS_ENABLED
   if (_wasReset) NOTIFY_SIM_STARTED();
   _wasReset=false;
@@ -598,11 +624,14 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
     //}
 #ifdef DEBUG_KERNEL
     std::cout << "kernel:simulate: BEFORE add trans " << commandLET->toString() << std::endl;
-    std::cout << "cpuLET= " << cpuLET->toString() << std::endl;
+    // std::cout << "cpuLET= " << cpuLET->toString() << std::endl;
+    std::cout << "fpgaLET= " << fpgaLET->toString() << std::endl;
     std::cout << "kernel:simulate:cpuLET printed" << std::endl;
 #endif
 	std::cout<<"in simulator begin addTransaction "<<std::endl;
-        bool x = cpuLET->addTransaction(0);
+	// bool x = cpuLET->addTransaction(0);
+	  std::cout << "fpgaLET= " << fpgaLET->toString() << std::endl;
+	 bool x = fpgaLET->addTransaction(0);
        // cpuLET->setCycleTime(0);
         std::cout<<"in simulator end addTransactin "<<std::endl;
 
@@ -622,10 +651,12 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
 #ifdef DEBUG_KERNEL
         std::cout << "kernel:simulate: dependent Task found" << std::endl;
 #endif
-        depCPU=depTask->getCPU();
+	// depCPU=depTask->getCPU();
+	depFPGA=depTask->getFPGA();
         //std::cout << "CPU this task : " << cpuLET->toString();
         //if (depCPU==0) std::cout << "  CPU dep task " << depTask->toString() << ": 0\n"; else std::cout << "  CPU dep task: "<< depTask->toString() << " " << depCPU->toString() << std::endl;
-        if (depCPU!=cpuLET){
+	// if (depCPU!=cpuLET){
+	if(depFPGA!=fpgaLET){
 #ifdef DEBUG_KERNEL
           std::cout << "kernel:simulate: Tasks running on different CPUs" << std::endl;
 #endif
@@ -650,28 +681,37 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
                  continue;
                  }*/
               //std::cout << "Let's crash!!!!!!!!\n";
-              depCPUnextTrans=depCPU->getNextTransaction();
+              //depCPUnextTrans=depCPU->getNextTransaction();
+	      std::cout<<"depFpga get nexttrans begin"<<std::endl;
+	      depFPGAnextTrans=depFPGA->getNextTransaction();
+	      std::cout<<"depFpga get nexttrans end"<<std::endl;
               //std::cout << "Not crahed!!!!!!!!\n";
-              if (depCPUnextTrans!=0){
+	      // if (depCPUnextTrans!=0){
+	      if(depFPGAnextTrans!=0){
 #ifdef DEBUG_KERNEL
                 std::cout << "kernel:simulate: transaction scheduled on dependent CPU" << std::endl;
 #endif
-                depCPUnextCommand=depCPUnextTrans->getCommand();
-                if (depCPUnextCommand->getTask()!=depTask){
+                //depCPUnextCommand=depCPUnextTrans->getCommand();
+		depFPGAnextCommand=depFPGAnextTrans->getCommand();
+		// if (depCPUnextCommand->getTask()!=depTask){
+		 if (depFPGAnextCommand->getTask()!=depTask){
 #ifdef DEBUG_KERNEL
                   std::cout << "kernel:simulate: dependent task not yet scheduled on dependent CPU" << std::endl;
 #endif
 
-                  depCPU->truncateAndAddNextTransAt(transLET->getEndTime());
+		  // depCPU->truncateAndAddNextTransAt(transLET->getEndTime());
+		  // depFPGA->truncateAndAddNextTransAt(transLET->getEndTime());
 #ifdef DEBUG_KERNEL
                   std::cout << "kernel:simulate: dependent transaction truncated" << std::endl;
 #endif
                 }
               }else{
 #ifdef DEBUG_KERNEL
-                std::cout << "kernel:simulate: schedule dependent CPU  " << depCPU->toString() << std::endl;
+                //std::cout << "kernel:simulate: schedule dependent CPU  " << depCPU->toString() << std::endl;
 #endif
-                depCPU->schedule();
+		std::cout<<"depfpga schedule begin"<<std::endl;
+		depFPGA->schedule();
+		std::cout<<"depfpga schedule end"<<std::endl;
               }
             }
           }
@@ -688,7 +728,10 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
         if (*i!=cpuLET) (*i)->rescheduleIfNecessary();
         }
         }*/
-      cpuLET->schedule();
+      // cpuLET->schedule();
+      std::cout<<"fpgalet schedule begin"<<std::endl;
+      fpgaLET->schedule();
+      std::cout<<"fpgalet schedule end"<<std::endl;
 #ifdef LISTENERS_ENABLED
       NOTIFY_TIME_ADVANCES(transLET->getEndTime());
 #endif
@@ -696,7 +739,12 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
     oLastTrans=transLET;
 
     //std::cout << "kernel:simulate: getTransLowestEndTime" << std::endl;
-    transLET=getTransLowestEndTime(cpuLET);
+    //transLET=getTransLowestEndTime(cpuLET);
+    std::cout<<"~~~~~~get next trans begin"<<std::endl;
+      
+    transLET=getTransLowestEndTime(fpgaLET);
+    
+    std::cout<<"~~~~get next trans end"<<std::endl;
 
     //_syncInfo->_server->sendReply("Sleep once again\n");
     //sleep(1);
diff --git a/simulators/c++2/src_simulator/sim/Simulator.h b/simulators/c++2/src_simulator/sim/Simulator.h
index 173b66cb5010ec4865bb0e85f973621832cbed7a..f9674446c165c1b1c5cdd658adbf98fa5680936d 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.h
+++ b/simulators/c++2/src_simulator/sim/Simulator.h
@@ -71,6 +71,7 @@ Ludovic Apvrille, Renaud Pacalet
 #endif
 
 class CPU;
+class FPGA;
 class TMLTransaction;
 class TMLCommand;
 class TMLTask;