From a31cb004ae8381b3eb4740f6343fdb0e91d0d652 Mon Sep 17 00:00:00 2001
From: niusiyuan <siyuan.niu@telecom-paristech.fr>
Date: Thu, 2 May 2019 14:32:05 +0200
Subject: [PATCH] several tasks on one fpga ok, 2 fpga not ok
---
simulators/c++2/Makefile | 2 +-
simulators/c++2/src_simulator/app/TMLTask.cpp | 2 +-
simulators/c++2/src_simulator/arch/FPGA.cpp | 109 ++++++++----------
simulators/c++2/src_simulator/arch/FPGA.h | 15 +--
.../c++2/src_simulator/arch/RRScheduler.cpp | 5 +
.../c++2/src_simulator/arch/RRScheduler.h | 2 +-
.../c++2/src_simulator/arch/SingleCoreCPU.cpp | 8 +-
.../c++2/src_simulator/sim/Simulator.cpp | 65 +++++++----
simulators/c++2/src_simulator/sim/Simulator.h | 1 +
9 files changed, 112 insertions(+), 97 deletions(-)
diff --git a/simulators/c++2/Makefile b/simulators/c++2/Makefile
index 500646b6db..36a0bb57f4 100755
--- a/simulators/c++2/Makefile
+++ b/simulators/c++2/Makefile
@@ -24,7 +24,7 @@ OS := $(shell uname)
MODULE = run
include Makefile.src
-SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
+SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
SRCS_base_DIR = src_simulator
SRCS_generated = .
diff --git a/simulators/c++2/src_simulator/app/TMLTask.cpp b/simulators/c++2/src_simulator/app/TMLTask.cpp
index 42c96848a5..d85534b7c9 100755
--- a/simulators/c++2/src_simulator/app/TMLTask.cpp
+++ b/simulators/c++2/src_simulator/app/TMLTask.cpp
@@ -358,7 +358,7 @@ unsigned int TMLTask::getState() const{
}
TMLTransaction* TMLTask::getNextTransaction(TMLTime iEndSchedule) const{
- //std::cout << "Task::getNextTransaction\n";
+ std::cout<<"TMLTask get next trans"<<std::endl;
return (_currCommand==0)?0:_currCommand->getCurrTransaction();
//return (_currCommand==0 || _isScheduled)?0:_currCommand->getCurrTransaction();
}
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index f37d5ffcb7..976c523203 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -48,27 +48,19 @@
FPGA::FPGA( ID iID,
- std::string iName,
- WorkloadSource* iScheduler,
- TMLTime iTimePerCycle,
+ std::string iName,
TMLTime iReconfigTime,
unsigned int iChangeIdleModeCycles,
unsigned int iCyclesBeforeIdle,
unsigned int iCyclesPerExeci,
- unsigned int iCyclesPerExecc ) : SchedulableDevice(iID, iName, iScheduler)
- ,_timePerCycle(iTimePerCycle)
+ unsigned int iCyclesPerExecc ) : SchedulableDevice(iID, iName, 0)
,_reconfigTime(iReconfigTime)
,_lastTransaction(0)
-#ifdef PENALTIES_ENABLED
- ,_changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
-#endif
-#ifdef PENALTIES_ENABLED
- , _timePerExeci(_cyclesPerExeci * _timePerCycle /100.0)
- , _timeBeforeIdle(_cyclesBeforeIdle*_timePerCycle)
- , _changeIdleModeTime(_changeIdleModeCycles*_timePerCycle)
-#else
- , _timePerExeci(_cyclesPerExeci*_timePerCycle)
-#endif
+ ,_changeIdleModeCycles(iChangeIdleModeCycles)
+ ,_cyclesBeforeIdle(iCyclesBeforeIdle)
+ ,_cyclesPerExeci(iCyclesPerExeci)
+ ,_cyclesPerExecc(iCyclesPerExecc)
+
{}
FPGA::~FPGA(){}
@@ -78,8 +70,8 @@ void FPGA::streamBenchmarks(std::ostream& s) const{
std::cout<<"test fpga stramBenchmarks"<<std::endl;
s << TAG_FPGAo << " id=\"" << _ID << "\" name=\"" << _name << "\">" << std::endl;
if (_simulatedTime!=0) s << TAG_UTILo << (static_cast<float>(_busyCycles)/static_cast<float>(_simulatedTime)) << TAG_UTILc;
- s << TAG_ENERGYo << ( (_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle) << TAG_ENERGYc;
- std::cout<< "power consumption "<< ((_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle)<< std::endl;
+ s << TAG_ENERGYo << ( (_simulatedTime)*_static_consumPerCycle) + ((_busyCycles)*_dynamic_consumPerCycle) << TAG_ENERGYc;
+ std::cout<< "power consumption "<< ((_simulatedTime)*_static_consumPerCycle) + ((_busyCycles)*_dynamic_consumPerCycle)<< std::endl;
for(BusMasterList::const_iterator i=_busMasterList.begin(); i != _busMasterList.end(); ++i) (*i)->streamBenchmarks(s);
s << TAG_FPGAc;
}
@@ -87,7 +79,7 @@ void FPGA::streamBenchmarks(std::ostream& s) const{
TMLTransaction* FPGA::getNextTransaction(){
-std::cout<<"fpga getNextTransaction"<<std::endl;
+ std::cout<<"fpga getNextTransaction";
#ifdef BUS_ENABLE
if(_masterNextTransaction==0 || _nextTransaction==0){
return _nextTransaction;
@@ -106,25 +98,22 @@ std::cout<<"fpga getNextTransaction"<<std::endl;
return (aResult)?_nextTransaction:0;
}
#else
+ if(_nextTransaction)std::cout<<_nextTransaction->toString()<<std::endl;
+ else std::cout<<"nexttrans is 0"<<std::endl;
return _nextTransaction;
#endif
}
-void FPGA::calcStartTimeLength(TMLTime iTimeSlice){
+void FPGA::calcStartTimeLength(){
std::cout<<"fpga calStartTimeLength"<<std::endl;
#ifdef BUS_ENABLED
std::cout << "FPGA:calcSTL: scheduling decision of FPGA " << _name << ": " << _nextTransaction->toString() << std::endl;
- std::cout << "get channel " << std::endl;
TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
- std::cout << "after get channel " << std::endl;
if (aChannel==0) {
- std::cout<<"test111"<<std::endl;
- //std::cout << "no channel " << std::endl;
_masterNextTransaction=0;
} else {
- std::cout << "get bus " << std::endl;
_masterNextTransaction= getMasterForBus(aChannel->getFirstMaster(_nextTransaction));
if (_masterNextTransaction!=0){
std::cout << "before register transaction at bus " << _masterNextTransaction->toString() << std::endl;
@@ -135,38 +124,16 @@ std::cout<<"fpga calStartTimeLength"<<std::endl;
}
}
#endif
- std::cout<<"test222"<<std::endl;
//round to full cycles!!!
- std::cout<<"time per cycle is "<<_timePerCycle<<std::endl;
- std::cout<<"test333"<<std::endl;
TMLTime aStartTime = _nextTransaction->getRunnableTime();
- TMLTime aReminder = aStartTime % _timePerCycle;
- if (aReminder!=0) aStartTime+=_timePerCycle - aReminder;
- std::cout << "FPGA: set start time in FPGA=" << aStartTime << " Reminder=" << aReminder <<"\n";
-
+ //or setStartTime(0)???
_nextTransaction->setStartTime(aStartTime);
#ifdef BUS_ENABLED
if (_masterNextTransaction==0){
-#endif
- //calculate length of transaction
- //if (_nextTransaction->getOperationLength()!=-1){
- std::cout<<"at first virtual length "<<_nextTransaction->getVirtualLength()<<std::endl;
- std::cout<<"another "<<(TMLLength)(iTimeSlice /_timePerExeci)<<std::endl;
- if (iTimeSlice!=0){
- _nextTransaction->setVirtualLength(max(min(_nextTransaction->getVirtualLength(), (TMLLength)(iTimeSlice /_timePerExeci)), (TMLTime)1));
- }
- _nextTransaction->setLength(_nextTransaction->getVirtualLength()*_timePerExeci);
- std::cout<<"!!!!!virtual length is "<<_nextTransaction->getVirtualLength()<<std::endl;
-#ifdef BUS_ENABLED
- }
-#endif
-#ifdef PENALTIES_ENABLED
- //std::cout << "starttime=" << _nextTransaction->getStartTime() << "\n";
- if ((_nextTransaction->getStartTime()-_endSchedule) >=_timeBeforeIdle){
- _nextTransaction->setIdlePenalty(_changeIdleModeTime);
+#endif
+ _nextTransaction->setLength(max(_nextTransaction->getVirtualLength(),(TMLTime)1));
}
-#endif
}
void FPGA::truncateAndAddNextTransAt(TMLTime iTime){
@@ -188,7 +155,7 @@ std::cout<<"fpga truncateAndAddNextTransAt"<<std::endl;
//if (_nextTransaction!=0 && truncateNextTransAt(iTime)!=0) addTransaction(); //NEW!!!!
if (_nextTransaction!=0 && _masterNextTransaction!=0) _masterNextTransaction->registerTransaction(0);
_nextTransaction = aNewTransaction;
- if (_nextTransaction!=0) calcStartTimeLength(aTimeSlice);
+ if (_nextTransaction!=0) calcStartTimeLength();
}
//std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
@@ -263,13 +230,18 @@ std::cout<<"fpga addTransaction"<<std::endl;
}
//std::cout << "8\n";
}
+
if (aFinish){
+
_endSchedule=0;
_simulatedTime=max(_simulatedTime,_endSchedule);
_overallTransNo++; //NEW!!!!!!!!
_overallTransSize+=_nextTransaction->getOperationLength(); //NEW!!!!!!!!
//std::cout << "lets crash execute\n";
- _nextTransaction->getCommand()->execute(); //NEW!!!!
+
+ // std::cout<<_nextTransaction->toString()<<std::endl;
+ if(_nextTransaction->getCommand()==0) std::cout<<"d"<<std::endl;
+ _nextTransaction->getCommand()->execute(); //NEW!!!!
//std::cout << "not crashed\n";
#ifdef TRANSLIST_ENABLED
_transactList.push_back(_nextTransaction);
@@ -280,6 +252,7 @@ std::cout<<"fpga addTransaction"<<std::endl;
NOTIFY_TRANS_EXECUTED(_nextTransaction);
#endif
_nextTransaction=0;
+
return true;
} else return false;
}
@@ -287,21 +260,37 @@ std::cout<<"fpga addTransaction"<<std::endl;
void FPGA::schedule(){
std::cout << "fpga:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
-
- TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
-
+ /* TMLTransaction* _firstTransaction=(*_taskList.begin())->getNextTransaction(0);
+ static bool first=true;
TMLTransaction* aOldTransaction = _nextTransaction;
- _nextTransaction=_scheduler->getNextTransaction(_endSchedule);
-
- if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW
-
+ if(first==true){
+ _nextTransaction=_firstTransaction;
+ first=false;
+ }*/
+ for(TaskList::iterator it=_taskList.begin();it!=_taskList.end();++it){
+ std::cout<<"hahah"<<std::endl;
+ std::cout<<(*it)->toShortString()<<std::endl;
+ }
+ TMLTransaction* aOldTransaction = _nextTransaction;
+ std::cout<<"111"<<std::endl;
+ static TaskList::iterator iter_task=_taskList.begin();
+ std::cout<<"222"<<std::endl;
+ if(iter_task!=_taskList.end()){
+ std::cout<<"555"<<std::endl;
+ _nextTransaction=(*iter_task++)->getNextTransaction(0);
+ std::cout<<"666"<<std::endl;
+ }
+
+ std::cout<<"333"<<std::endl;
+ //std::cout<<_nextTransaction->toShortString()<<std::endl;
+ if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW
if (_masterNextTransaction!=0) {
_masterNextTransaction->registerTransaction(0);
}
}
-
- if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
+ std::cout<<"444"<<std::endl;
+ if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength();
std::cout << "fpga:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index e7aa72e06d..f4590f088b 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -70,10 +70,6 @@ public:
/**
\param iID ID of the device
\param iName Name of the device
- \param iScheduler Pointer to the scheduler object
- \param iTimePerCycle 1/Processor frequency
- \param iMapCapacity Pointer to the overall mapping capacity ????
- \param iMapPenalty Pointer to the mapping penalty ????
\param iReconfigTime reconfiguration time
\param iChangeIdleModeCycles Cycles needed to switch into indle mode
\param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle
@@ -81,7 +77,7 @@ public:
\param iCyclesPerExecc Cycles needed to execute one EXECC unit
*/
- FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iTimePerCycle, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
+ FPGA(ID iID, std::string iName, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
///Destructor
virtual ~FPGA();
///Determines the next FPGA transaction to be executed
@@ -128,12 +124,11 @@ public:
*/
virtual void registerTask(TMLTask* iTask){
_taskList.push_back(iTask);
- if (_scheduler!=0) _scheduler->addWorkloadSource(iTask);
}
protected:
///List of all tasks running on the FPGA
TaskList _taskList;
-
+
/**
\param iTime Indicates at what time the transaction should be truncated
*/
@@ -142,9 +137,7 @@ protected:
/**
\param iTimeSlice FPGA Time slice granted by the scheduler
*/
- void calcStartTimeLength(TMLTime iTimeSlice);
- ///1/Processor frequency
- TMLTime _timePerCycle;
+ void calcStartTimeLength();
TMLTime _reconfigTime;
@@ -167,6 +160,7 @@ protected:
#endif
///Cycles needed to execute one execi unit
unsigned int _cyclesPerExeci;
+ unsigned int _cyclesPerExecc;
///Time needed to execute one execi unit
float _timePerExeci;
#ifdef PENALTIES_ENABLED
@@ -175,6 +169,7 @@ protected:
///Time needed to switch into idle mode
TMLTime _changeIdleModeTime;
#endif
+
///State variable for the VCD output
vcdFPGAVisState _vcdOutputState;
};
diff --git a/simulators/c++2/src_simulator/arch/RRScheduler.cpp b/simulators/c++2/src_simulator/arch/RRScheduler.cpp
index e6a025c019..ed50d0d2da 100644
--- a/simulators/c++2/src_simulator/arch/RRScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/RRScheduler.cpp
@@ -123,7 +123,12 @@ TMLTime RRScheduler::schedule(TMLTime iEndSchedule){
// _nextTransaction->setLength(min(_nextTransaction->getOperationLength(), _timeSlice-_elapsedTime));
//}
//std::cout << "End schedule\n" ;
+ if(_nextTransaction)
+ std::cout<<"in rr next trans is"<<_nextTransaction->toShortString()<<std::endl;
+ else
+ std::cout<<"in rr next trans is 0"<<std::endl;
return _timeSlice-_elapsedTime;
+
}
//TMLTransaction* RRScheduler::getNextTransaction(TMLTime iEndSchedule) const{
diff --git a/simulators/c++2/src_simulator/arch/RRScheduler.h b/simulators/c++2/src_simulator/arch/RRScheduler.h
index 1291fd2d42..d80bd381b4 100644
--- a/simulators/c++2/src_simulator/arch/RRScheduler.h
+++ b/simulators/c++2/src_simulator/arch/RRScheduler.h
@@ -69,7 +69,7 @@ public:
///Destructor
~RRScheduler();
TMLTime schedule(TMLTime iEndSchedule);
- inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
+ inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {if(_nextTransaction) std::cout<<"rr next trans"<<std::endl;return _nextTransaction;}
void reset();
std::istream& readObject(std::istream &is);
std::ostream& writeObject(std::ostream &os);
diff --git a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
index 86d66785d2..d588a48d81 100644
--- a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
@@ -311,12 +311,14 @@ std::cout<<"addTransaction"<<std::endl;
void SingleCoreCPU::schedule(){
//std::cout <<"Hello\n";
- std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+ // std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+ std::cout<<"CPU schedule"<<std::endl;
TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
- //_schedulingNeeded=false; 05/05/11
- //std::cout << "1\n";
+
TMLTransaction* aOldTransaction = _nextTransaction;
_nextTransaction=_scheduler->getNextTransaction(_endSchedule);
+ if(_nextTransaction) std::cout<<"next trans is "<<_nextTransaction->toShortString()<<std::endl;
+ else std::cout<<"next trans is 0"<<std::endl;
//std::cout << "2\n";
//_scheduler->transWasScheduled(this); //NEW 05/05/11
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index bb0683206c..496df3ee28 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -46,6 +46,7 @@
#include <SimComponents.h>
#include <IndeterminismSource.h>
#include <CPU.h>
+#include <FPGA.h>
#include <TMLTask.h>
#include <TMLChannel.h>
#include <ServerIF.h>
@@ -79,7 +80,8 @@ TMLTransaction* Simulator::getTransLowestEndTime(SchedulableDevice*& oResultDevi
#endif
//for(SchedulingList::const_iterator i=_simComp->_cpuList.begin(); i != _simComp->_cpuList.end(); ++i){
//for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
- for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+ // for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+ for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
aTempDevice=*i;
aTempTrans=aTempDevice->getNextTransaction();
if (aTempTrans!=0 && aTempTrans->getVirtualLength()>0){
@@ -247,7 +249,8 @@ void Simulator::schedule2TXT(std::string& iTraceFileName) const{
std::ofstream myfile(iTraceFileName.c_str());
if (myfile.is_open()){
//for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
- for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+ //for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
+ for(FPGAList::const_iterator i=_simComp->getFPGAList().begin(); i != _simComp->getFPGAList().end(); ++i){
(*i)->schedule2TXT(myfile);
}
//for(BusList::const_iterator j=_simComp->getBusIterator(false); j != _simComp->getBusIterator(true); ++j){
@@ -554,11 +557,15 @@ bool Simulator::channelImpactsCommand(TMLChannel* iCh, TMLCommand* iCmd){
}
bool Simulator::simulate(TMLTransaction*& oLastTrans){
- TMLTransaction* depTransaction,*depCPUnextTrans,*transLET;
- TMLCommand* commandLET,*depCommand,*depCPUnextCommand;
+ //TMLTransaction* depTransaction,*depCPUnextTrans,*transLET;
+ //TMLCommand* commandLET,*depCommand,*depCPUnextCommand;
+ TMLTransaction* depTransaction,*depFPGAnextTrans,*transLET;
+ TMLCommand* commandLET,*depCommand,*depFPGAnextCommand;
TMLTask* depTask;
- SchedulableDevice* cpuLET;
- CPU* depCPU;
+ // SchedulableDevice* cpuLET;
+ // CPU* depCPU;
+ SchedulableDevice* fpgaLET;
+ FPGA* depFPGA;
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: first schedule" << std::endl;
#endif
@@ -580,9 +587,13 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
//for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::setRescheduleFlag));
//for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::schedule));
std::cout<<"simulate"<<std::endl;
- for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
+ //for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
+ for_each(_simComp->getFPGAList().begin(), _simComp->getFPGAList().end(),std::mem_fun(&FPGA::schedule));
//std::cout << "after schedule" << std::endl;
- transLET=getTransLowestEndTime(cpuLET);
+ //transLET=getTransLowestEndTime(cpuLET);
+ std::cout<<"simulator get next transaction begin"<<std::endl;
+ transLET=getTransLowestEndTime(fpgaLET);
+ std::cout<<"simulator get next transaction end"<<std::endl;
//std::cout << "after getTLET" << std::endl;
#ifdef LISTENERS_ENABLED
if (_wasReset) NOTIFY_SIM_STARTED();
@@ -598,11 +609,13 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
//}
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: BEFORE add trans " << commandLET->toString() << std::endl;
- std::cout << "cpuLET= " << cpuLET->toString() << std::endl;
+ // std::cout << "cpuLET= " << cpuLET->toString() << std::endl;
+ std::cout << "fpgaLET= " << fpgaLET->toString() << std::endl;
std::cout << "kernel:simulate:cpuLET printed" << std::endl;
#endif
std::cout<<"in simulator begin addTransaction "<<std::endl;
- bool x = cpuLET->addTransaction(0);
+ // bool x = cpuLET->addTransaction(0);
+ bool x = fpgaLET->addTransaction(0);
// cpuLET->setCycleTime(0);
std::cout<<"in simulator end addTransactin "<<std::endl;
@@ -622,10 +635,12 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: dependent Task found" << std::endl;
#endif
- depCPU=depTask->getCPU();
+ // depCPU=depTask->getCPU();
+ depFPGA=depTask->getFPGA();
//std::cout << "CPU this task : " << cpuLET->toString();
//if (depCPU==0) std::cout << " CPU dep task " << depTask->toString() << ": 0\n"; else std::cout << " CPU dep task: "<< depTask->toString() << " " << depCPU->toString() << std::endl;
- if (depCPU!=cpuLET){
+ // if (depCPU!=cpuLET){
+ if(depFPGA!=fpgaLET){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: Tasks running on different CPUs" << std::endl;
#endif
@@ -650,28 +665,34 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
continue;
}*/
//std::cout << "Let's crash!!!!!!!!\n";
- depCPUnextTrans=depCPU->getNextTransaction();
+ //depCPUnextTrans=depCPU->getNextTransaction();
+ depFPGAnextTrans=depFPGA->getNextTransaction();
//std::cout << "Not crahed!!!!!!!!\n";
- if (depCPUnextTrans!=0){
+ // if (depCPUnextTrans!=0){
+ if(depFPGAnextTrans!=0){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: transaction scheduled on dependent CPU" << std::endl;
#endif
- depCPUnextCommand=depCPUnextTrans->getCommand();
- if (depCPUnextCommand->getTask()!=depTask){
+ //depCPUnextCommand=depCPUnextTrans->getCommand();
+ depFPGAnextCommand=depFPGAnextTrans->getCommand();
+ // if (depCPUnextCommand->getTask()!=depTask){
+ if (depFPGAnextCommand->getTask()!=depTask){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: dependent task not yet scheduled on dependent CPU" << std::endl;
#endif
- depCPU->truncateAndAddNextTransAt(transLET->getEndTime());
+ // depCPU->truncateAndAddNextTransAt(transLET->getEndTime());
+ depFPGA->truncateAndAddNextTransAt(transLET->getEndTime());
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: dependent transaction truncated" << std::endl;
#endif
}
}else{
#ifdef DEBUG_KERNEL
- std::cout << "kernel:simulate: schedule dependent CPU " << depCPU->toString() << std::endl;
+ //std::cout << "kernel:simulate: schedule dependent CPU " << depCPU->toString() << std::endl;
#endif
- depCPU->schedule();
+ // depCPU->schedule();
+ depFPGA->schedule();
}
}
}
@@ -688,7 +709,8 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
if (*i!=cpuLET) (*i)->rescheduleIfNecessary();
}
}*/
- cpuLET->schedule();
+ // cpuLET->schedule();
+ fpgaLET->schedule();
#ifdef LISTENERS_ENABLED
NOTIFY_TIME_ADVANCES(transLET->getEndTime());
#endif
@@ -696,7 +718,8 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
oLastTrans=transLET;
//std::cout << "kernel:simulate: getTransLowestEndTime" << std::endl;
- transLET=getTransLowestEndTime(cpuLET);
+ //transLET=getTransLowestEndTime(cpuLET);
+ transLET=getTransLowestEndTime(fpgaLET);
//_syncInfo->_server->sendReply("Sleep once again\n");
//sleep(1);
diff --git a/simulators/c++2/src_simulator/sim/Simulator.h b/simulators/c++2/src_simulator/sim/Simulator.h
index 173b66cb50..f9674446c1 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.h
+++ b/simulators/c++2/src_simulator/sim/Simulator.h
@@ -71,6 +71,7 @@ Ludovic Apvrille, Renaud Pacalet
#endif
class CPU;
+class FPGA;
class TMLTransaction;
class TMLCommand;
class TMLTask;
--
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