diff --git a/src/ddtranslatorSoclib/toTopCell/Declaration.java b/src/ddtranslatorSoclib/toTopCell/Declaration.java
index 83f7b7654a5d3305180c4cba844329f4fe30a446..ed58a37eb980cd1fd58ce9a3c904749e3365cebb 100755
--- a/src/ddtranslatorSoclib/toTopCell/Declaration.java
+++ b/src/ddtranslatorSoclib/toTopCell/Declaration.java
@@ -374,8 +374,10 @@ else {
 	      }
 	  else{ 
 	      //processor(s) and link to central interconnect are initiators
-	      crossbar.setNbOfAttachedInitiators(2);	 
-	      crossbar.setNbOfAttachedTargets(2);
+	      //crossbar.setNbOfAttachedInitiators(2);	 
+	      //crossbar.setNbOfAttachedTargets(2);
+	      crossbar.setNbOfAttachedInitiators(1);//DG 27.09.	 
+	      crossbar.setNbOfAttachedTargets(1);//DG 27.09.
 	  }
 
           System.out.println("initiators: "+crossbar.getNbOfAttachedInitiators());	
diff --git a/src/ddtranslatorSoclib/toTopCell/MappingTable.java b/src/ddtranslatorSoclib/toTopCell/MappingTable.java
index e093521c7a7f97e2034fac41a4f5aaa326dc9b85..8735a5847f5bc1ed5307776f4f7da5a32aced084 100755
--- a/src/ddtranslatorSoclib/toTopCell/MappingTable.java
+++ b/src/ddtranslatorSoclib/toTopCell/MappingTable.java
@@ -241,7 +241,7 @@ public class MappingTable {
       int SEG_RAM_BASE   =        268435456;    
       int    cluster = 0;
 
-      //DG 1.9. on cluster 0 only	 
+      	 
       //   mapping += "maptab.add(Segment(\"icu" + cluster + "\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,9), false));" + CR;
   mapping += "maptab.add(Segment(\"vci_xicu\",0x"+ Integer.toHexString(SEG_ICU_BASE)+", 0x"+ Integer.toHexString(SEG_ICU_SIZE)+", IntTab(0,9), false));" + CR;
   //mapping += "maptab.add(Segment(\"dma" + cluster + "\", 0x"+ Integer.toHexString(SEG_DMA_BASE)+", 0x"+ Integer.toHexString(SEG_DMA_SIZE)+", IntTab(0,10), false));" + CR;