diff --git a/src/main/java/tmltranslator/TMLArchiTextSpecification.java b/src/main/java/tmltranslator/TMLArchiTextSpecification.java
index 6d13fb1a7d2d34297f0fb72bc1231abec96775fa..77402c8cb211eca7814d512a50a92485a97dbd58 100755
--- a/src/main/java/tmltranslator/TMLArchiTextSpecification.java
+++ b/src/main/java/tmltranslator/TMLArchiTextSpecification.java
@@ -78,7 +78,7 @@ public class TMLArchiTextSpecification {
"maxConsecutiveIdleCycles", "reconfigurationTime", "execiTime", "execcTime", "scheduling", "clockDivider"};
private String linkparameters[] = {"bus", "node", "priority"};
private String hwaparameters[] = {"byteDataSize", "execiTime", "execcTime", "clockDivider"};
- private String busparameters[] = {"byteDataSize", "pipelineSize", "arbitration", "clockDivider"};
+ private String busparameters[] = {"byteDataSize", "pipelineSize", "arbitration", "sliceTime", "clockDivider"};
private String bridgeparameters[] = {"bufferByteSize", "clockDivider"};
private String memoryparameters[] = {"byteDataSize", "clockDivider"};
private String nocparameters[] = {"bufferbytesize", "nocSize", "clockdivider"};
@@ -225,6 +225,7 @@ public class TMLArchiTextSpecification {
code += set + "byteDataSize " + bus.byteDataSize + CR;
code += set + "pipelineSize " + bus.pipelineSize + CR;
code += set + "arbitration " + bus.arbitration + CR;
+ code += set + "sliceTime " + bus.sliceTime + CR;
}
@@ -774,6 +775,10 @@ public class TMLArchiTextSpecification {
if (_split[2].toUpperCase().equals("CLOCKDIVIDER")) {
bus.clockRatio = Integer.decode(_split[3]).intValue();
}
+
+ if (_split[2].toUpperCase().equals("SLICETIME")) {
+ bus.sliceTime = Integer.decode(_split[3]).intValue();
+ }
}
if (node instanceof HwBridge) {
diff --git a/src/main/java/tmltranslator/TMLTextSpecification.java b/src/main/java/tmltranslator/TMLTextSpecification.java
index 4b6cf17bff66119957b0320a23e608153aff7b95..820491a04b0da00672ee1f50045b2b998ed7951a 100755
--- a/src/main/java/tmltranslator/TMLTextSpecification.java
+++ b/src/main/java/tmltranslator/TMLTextSpecification.java
@@ -914,13 +914,13 @@ public class TMLTextSpecification<E> {
ch = new TMLChannel(_split[1], null);
ch.setTypeByName(_split[2]);
+ ch.setMax(tmp);// the capacity already calculated with _split[4]
try {
tmp = Integer.decode(_split[3]).intValue();
} catch (Exception e) {
tmp = 4;
}
ch.setSize(tmp);
- ch.setMax(tmp);
for (i = 5 + dec; i < _split.length; i++) {
if (i != indexOfIN) {
diff --git a/ttool/src/test/java/tmltranslator/BusSliceTimeConfigurationTest.java b/ttool/src/test/java/tmltranslator/BusSliceTimeConfigurationTest.java
index 6455351e8c21204b93eefd876f8ae45ed6b0be20..3e3084975e776626a3f126442d70be42adfafb0c 100644
--- a/ttool/src/test/java/tmltranslator/BusSliceTimeConfigurationTest.java
+++ b/ttool/src/test/java/tmltranslator/BusSliceTimeConfigurationTest.java
@@ -2,17 +2,16 @@ package tmltranslator;
import common.ConfigurationTTool;
import common.SpecConfigTTool;
-import graph.AUTGraph;
import myutil.FileUtils;
import org.junit.Before;
import org.junit.BeforeClass;
import org.junit.Test;
import req.ebrdd.EBRDD;
import tepe.TEPE;
+import test.AbstractTest;
import tmltranslator.tomappingsystemc2.DiploSimulatorFactory;
import tmltranslator.tomappingsystemc2.IDiploSimulatorCodeGenerator;
import tmltranslator.tomappingsystemc2.Penalties;
-import ui.AbstractUITest;
import java.io.BufferedReader;
import java.io.File;
@@ -22,11 +21,11 @@ import java.util.List;
import static org.junit.Assert.assertTrue;
-public class BusSliceTimeConfigurationTest extends AbstractUITest {
+public class BusSliceTimeConfigurationTest extends AbstractTest {
private final String DIR_GEN = "test_diplo_simulator/";
private final String[] MODELS_BUS_SLICE_TIME = {"bus_rr_preempted", "bus_rr_not_preempted","bus_rrpb_preempted", "bus_rrpb_not_preempted"};
- private final Integer[] EXPECTED_RESULT = {5, 2, 5, 2};
+ private final String[] EXPECTED_RESULT = {"20 - 2", "10 - 2", "10 - 2", "10 - 2"};
private String SIM_DIR;
private static String CPP_DIR = "../../../../simulators/c++2/";
@@ -175,16 +174,22 @@ public class BusSliceTimeConfigurationTest extends AbstractUITest {
File graphFile = new File(graphPath + ".txt");
String graphData = "";
- String findStr = "Execi";
+ String findStr0 = "Application__Src0: Write";
+ String findStr1 = "Application__Src1: Write";
try {
graphData = FileUtils.loadFileData(graphFile);
} catch (Exception e) {
assertTrue(false);
}
- int countExecI = graphData.split(findStr, -1).length-1;
- System.out.println("Number of ExecI transactions in model " + s + ": " + countExecI);
- assertTrue(countExecI == EXPECTED_RESULT[i]);
+ String result = "";
+ int countExecI = graphData.split(findStr0, -1).length-1;
+ System.out.println("Number of Write transactions of Src0 in model " + s + ": " + countExecI);
+ result += countExecI;
+ countExecI = graphData.split(findStr1, -1).length-1;
+ System.out.println("Number of Write transactions of Src1 in model " + s + ": " + countExecI);
+ result += " - " + countExecI;
+ assertTrue(result.equals(EXPECTED_RESULT[i]));
}
}
}
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tarchi b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tarchi
index d7d8c5ba4c819687f878c2d726017a455a197328..75e3cafa4f154792683f89f9e9417353c728fb3a 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tarchi
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tarchi
@@ -9,6 +9,7 @@ NODE BUS Bus0
SET Bus0 byteDataSize 1
SET Bus0 pipelineSize 1
SET Bus0 arbitration 0
+SET Bus0 sliceTime 10000
SET Bus0 clockDivider 1
NODE CPU TGT
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tml b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tml
index c8739d78441bceb38acce48818769f5443c5a4d1..756ed45bddc8140c59f71fc5b2e7c8b6ccace6ed 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tml
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_not_preempted.tml
@@ -19,7 +19,7 @@ TASK Application__Src0
//Local variables
//Behavior
- WRITE Application__c0 5
+ WRITE Application__c0 200
EXECI 400
ENDTASK
@@ -28,7 +28,7 @@ TASK Application__Src1
//Local variables
//Behavior
- WRITE Application__c1 5
+ WRITE Application__c1 10
EXECI 300
ENDTASK
@@ -37,7 +37,7 @@ TASK Application__Tgt0
//Local variables
//Behavior
- READ Application__c0 5
+ READ Application__c0 200
ENDTASK
TASK Application__Tgt1
@@ -45,6 +45,6 @@ TASK Application__Tgt1
//Local variables
//Behavior
- READ Application__c1 5
+ READ Application__c1 10
ENDTASK
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tarchi b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tarchi
index 97d0344ae109074ada16fb737724ee148e6ce366..2fea812680f112218a551a788a731e9512759c6b 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tarchi
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tarchi
@@ -1,5 +1,5 @@
// Master clock frequency - in MHz
-MASTERCLOCKFREQUENCY 200
+MASTERCLOCKFREQUENCY 20
NODE MEMORY Memory0
SET Memory0 byteDataSize 4
@@ -9,6 +9,7 @@ NODE BUS Bus0
SET Bus0 byteDataSize 1
SET Bus0 pipelineSize 1
SET Bus0 arbitration 0
+SET Bus0 sliceTime 1
SET Bus0 clockDivider 1
NODE CPU TGT
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tml b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tml
index fcb7571789e8e828cb4ed9ba60d3ea954e7e409d..a33ed2cd6718313694c3e21ac57d5d090293c69c 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tml
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rr_preempted.tml
@@ -19,7 +19,7 @@ TASK Application__Src0
//Local variables
//Behavior
- WRITE Application__c0 5
+ WRITE Application__c0 200
EXECI 400
ENDTASK
@@ -28,7 +28,7 @@ TASK Application__Src1
//Local variables
//Behavior
- WRITE Application__c1 5
+ WRITE Application__c1 10
EXECI 300
ENDTASK
@@ -37,7 +37,7 @@ TASK Application__Tgt0
//Local variables
//Behavior
- READ Application__c0 5
+ READ Application__c0 200
ENDTASK
TASK Application__Tgt1
@@ -45,6 +45,6 @@ TASK Application__Tgt1
//Local variables
//Behavior
- READ Application__c1 5
+ READ Application__c1 10
ENDTASK
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tarchi b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tarchi
index 4ca7e0e889b12596d8bda13b47f064ca3ad5ab1e..b8028606674035baf06e0bc12e861515192b7e2b 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tarchi
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tarchi
@@ -9,6 +9,7 @@ NODE BUS Bus0
SET Bus0 byteDataSize 1
SET Bus0 pipelineSize 1
SET Bus0 arbitration 1
+SET Bus0 sliceTime 10000
SET Bus0 clockDivider 1
NODE CPU TGT
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tml b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tml
index 9b30d97ee171249f4ec1aa7ea14340a2cad70e39..fe1e4cf636ea1d0c83ca2b2b9c275a1166d09f69 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tml
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_not_preempted.tml
@@ -19,7 +19,7 @@ TASK Application__Src0
//Local variables
//Behavior
- WRITE Application__c0 5
+ WRITE Application__c0 200
EXECI 400
ENDTASK
@@ -28,7 +28,7 @@ TASK Application__Src1
//Local variables
//Behavior
- WRITE Application__c1 5
+ WRITE Application__c1 10
EXECI 300
ENDTASK
@@ -37,7 +37,7 @@ TASK Application__Tgt0
//Local variables
//Behavior
- READ Application__c0 5
+ READ Application__c0 200
ENDTASK
TASK Application__Tgt1
@@ -45,6 +45,6 @@ TASK Application__Tgt1
//Local variables
//Behavior
- READ Application__c1 5
+ READ Application__c1 10
ENDTASK
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tarchi b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tarchi
index f0bd87bb45e02eaa68daaa7dafe8cb0c83260dfd..2daca434d8638a807e7fe8dea353a349e1e52290 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tarchi
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tarchi
@@ -1,5 +1,5 @@
// Master clock frequency - in MHz
-MASTERCLOCKFREQUENCY 200
+MASTERCLOCKFREQUENCY 20
NODE MEMORY Memory0
SET Memory0 byteDataSize 4
@@ -9,6 +9,7 @@ NODE BUS Bus0
SET Bus0 byteDataSize 1
SET Bus0 pipelineSize 1
SET Bus0 arbitration 1
+SET Bus0 sliceTime 1
SET Bus0 clockDivider 1
NODE CPU TGT
diff --git a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tml b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tml
index f0d06dee590bb236d29ec32877699c161e707765..fddce899a08ee617013c7d94063429e69b00e272 100644
--- a/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tml
+++ b/ttool/src/test/resources/tmltranslator/simulator/bus_rrpb_preempted.tml
@@ -19,7 +19,7 @@ TASK Application__Src0
//Local variables
//Behavior
- WRITE Application__c0 5
+ WRITE Application__c0 200
EXECI 400
ENDTASK
@@ -28,7 +28,7 @@ TASK Application__Src1
//Local variables
//Behavior
- WRITE Application__c1 5
+ WRITE Application__c1 10
EXECI 300
ENDTASK
@@ -37,7 +37,7 @@ TASK Application__Tgt0
//Local variables
//Behavior
- READ Application__c0 5
+ READ Application__c0 200
ENDTASK
TASK Application__Tgt1
@@ -45,6 +45,6 @@ TASK Application__Tgt1
//Local variables
//Behavior
- READ Application__c1 5
+ READ Application__c1 10
ENDTASK