diff --git a/src/main/java/camstranslator/SystemCamsSpecification.java b/src/main/java/camstranslator/SystemCamsSpecification.java
deleted file mode 100755
index 9da15a45d50b487a7223eb12a7d289ee21eb98db..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/SystemCamsSpecification.java
+++ /dev/null
@@ -1,266 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-
-/* * @version 1.0 07/07/2015
- * @author Julien Henon, Daniela Genius */
-
-package ddtranslatorSoclib;
-
-import java.util.LinkedList;
-import java.util.List;
-
-public class AvatarddSpecification{
-
- private List<AvatarComponent> components;
- private List<AvatarConnector> connectors;
- private List<AvatarMappedObject> mappedObjects;
-
- private int nb_init = 0;
-
-/*there are seven targets which are fixed but invisible to the user of the TTool deployment diagram) :
-
-Targets on RAM0 :
-the text segment (target 0)
-the reset segment (target 1)
-the data segment (target 2)
-
-Other targets :
-the simhelper segment (target 3)
-the icu segment (target 4)
-the timer segment (target 5)
-the fdt segment (target 6)
-
-There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) otherwise an error message is printed
-*/
-
-/* initialization of counters, there are at least 6 targets */
- int nb_target = 6;
- int nb_mwmr_segments = 0;
-
- public AvatarddSpecification( List<AvatarComponent> _components, List<AvatarConnector> _connectors, List<AvatarMappedObject> _mappedObjects, int _nb_target, int _nb_init){
- components = _components ;
- connectors = _connectors ;
- mappedObjects = _mappedObjects ;
- nb_target = _nb_target;
- nb_init = _nb_init;
- }
-
- public List<AvatarComponent> getComponents(){
- return components;
- }
-
- public List<AvatarConnector> getConnectors(){
- return connectors;
- }
-
- public List<AvatarMappedObject> getMappedObjects(){
- return mappedObjects;
- }
-
- public List<AvatarTask> getAllMappedTask(){
- List<AvatarTask> tasks = new LinkedList<AvatarTask>();
-
- for (AvatarMappedObject task : mappedObjects ) {
- if (task instanceof AvatarTask) {
- tasks.add((AvatarTask)task);
- }
- }
-
- return tasks;
- }
-
- public LinkedList<AvatarChannel> getAllMappedChannels(){
- LinkedList<AvatarChannel> channels = new LinkedList<AvatarChannel>();
- for (AvatarMappedObject channel : mappedObjects )
- {
- if (channel instanceof AvatarChannel)
- channels.add((AvatarChannel)channel);
- }
- return channels;
- }
-
- public LinkedList<AvatarTTY> getAllTTY(){
- //int i=0;
- LinkedList<AvatarTTY> ttys = new LinkedList<AvatarTTY>();
- for (AvatarComponent tty : components )
- {
- if (tty instanceof AvatarTTY){
- ttys.add((AvatarTTY)tty);
- }
- }
- return ttys;
- }
-
- public LinkedList<AvatarCPU> getAllCPU(){
- LinkedList<AvatarCPU> cpus = new LinkedList<AvatarCPU>();
- for (AvatarComponent cpu : components )
- {
- if (cpu instanceof AvatarCPU){
- cpus.add((AvatarCPU)cpu);
- }
- }
- return cpus;
- }
-
- public List<AvatarRAM> getAllRAM(){
- //int i=0;
- List<AvatarRAM> rams = new LinkedList<AvatarRAM>();
-
- for (AvatarComponent ram : components ) {
- if (ram instanceof AvatarRAM){
- rams.add((AvatarRAM)ram);
- }
- }
-
- return rams;
- }
-
- public List<AvatarBus> getAllBus(){
- LinkedList<AvatarBus> buss = new LinkedList<AvatarBus>();
- for (AvatarComponent bus : components )
- {
- if (bus instanceof AvatarBus)
- buss.add((AvatarBus)bus);
- }
- return buss;
- }
-
- public LinkedList<AvatarVgmn> getAllVgmn(){
- LinkedList<AvatarVgmn> vgmns = new LinkedList<AvatarVgmn>();
- for (AvatarComponent vgmn : components )
- {
- if (vgmn instanceof AvatarVgmn){
- vgmns.add((AvatarVgmn)vgmn);
-
- }
- }
- return vgmns;
- }
-
- public LinkedList<AvatarCrossbar> getAllCrossbar(){
- LinkedList<AvatarCrossbar> crossbars = new LinkedList<AvatarCrossbar>();
- //int i=0;
- for (AvatarComponent crossbar : components )
- {
- //Currently, at least one crossbar -> clustered
- if (crossbar instanceof AvatarCrossbar){
- System.out.println("Clustered Interconnect found");
- crossbars.add((AvatarCrossbar)crossbar);
- //crossbar.setClusterIndex(i);
- //i++;
- }
-
- }
- return crossbars;
- }
-
- /* public LinkedList<AvatarBridge> getAllBridge(){
- LinkedList<AvatarBridge> bridges = new LinkedList<AvatarBridge>();
- for (AvatarComponent bridge : components )
- {
- if (bridges instanceof AvatarBridge){
- bridges.add((AvatarBridge)bridge);
- }
- }
- return bridges;
- }*/
-
-
- //Currently, we define 1 crossbar = 1 cluster
- public int getNbClusters(){
- return getAllCrossbar().size();
- }
-
- public List<AvatarCoproMWMR> getAllCoproMWMR(){
- List<AvatarCoproMWMR> copros = new LinkedList<AvatarCoproMWMR>();
- for (AvatarComponent copro : components )
- {
- if (copro instanceof AvatarCoproMWMR)
- copros.add((AvatarCoproMWMR)copro);
-
- }
- return copros;
- }
-
- public int getNbCPU(){
- return (getAllCPU()).size();
- }
-
- public int getNbTTY(){
- return (getAllTTY()).size();
- }
-
- public int getNbRAM(){
- return (getAllRAM()).size();
- }
-
- public int getNbBus(){
- return (getAllBus()).size();
- }
-
- public int getNbVgmn(){
- return (getAllVgmn()).size();
- }
-
- public int getNbCrossbar(){
- return (getAllCrossbar()).size();
- }
-
- public int getNbCoproMWMR(){
- return (getAllCoproMWMR()).size();
- }
-
- // for construction of the central interconnect
-
- public int getNb_init(){
- return nb_init ;
- }
-
- public int getNb_target(){
- return nb_target;
- }
-
- // etc .....
-
-}
diff --git a/src/main/java/camstranslator/toComponent/SystemCAMSComponentGenerator.java b/src/main/java/camstranslator/toComponent/SystemCAMSComponentGenerator.java
deleted file mode 100755
index 7b5a2a920e73aca2e53e7c8bfc3d47327221cbbe..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toComponent/SystemCAMSComponentGenerator.java
+++ /dev/null
@@ -1,218 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- *
- * ludovic.apvrille AT enst.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-package systemcamstranslator.toComponent;
-
-import systemcamstranslator.*;
-import systemcamstranslator.GenericTLMComponent;
-import systemcamstranslator.SystemCamsSpecification;
-import ddtranslatorSoclib.toTopCell.TopCellGenerator;
-import myutil.Conversion;
-import myutil.FileException;
-import myutil.FileUtils;
-import myutil.TraceManager;
-
-import java.io.File;
-import java.util.LinkedList;
-import java.util.List;
-import java.util.Vector;
-
-/**
- * Daniela GENIUS
- */
-public class ToComponent {
-
- private final static int USEC = 0;
- private final static int MSEC = 1;
- private final static int SEC = 2;
-
-
- private final static String UNUSED_ATTR = "__attribute__((unused))";
- private final static String GENERATED_PATH = "generated_component" + File.separator;
- // private final static String UNKNOWN = "UNKNOWN";
- private final static String CR = "\n";
- private final static String CR2 = "\n\n";
-
- public static SystemCamsSpecification spec ;
-
- private Vector<?> warnings;
-
- private MainFileSoclib mainFile;
- private Vector<ComponentFiles> ComponentFiles;
- private String makefile_src;
- private String makefile_SocLib;
-
- private int timeUnit;
- private boolean debug;
- private boolean tracing;
- private boolean includeUserCode = true;
-
- public ToComponent(SystemCamsSpecification spec) {
- spec = _spec;
- componentFiles = new Vector<ComponentFiles>();
- }
-
- public void setTimeUnit(int _timeUnit) {
- timeUnit = _timeUnit;
- }
-
- public void includeUserCode(boolean _inc) {
- includeUserCode = _inc;
- }
-
- public static String getGeneratedPath() {
- return GENERATED_PATH;
- }
-
- public void saveInFiles(String path) throws FileException {
-
- System.err.println("ok");
- TraceManager.addDev("Generating files");
-
- if (mainFile != null) {
- TraceManager.addDev("Generating main files in " + path + mainFile.getName() + ".h");
- FileUtils.saveFile(path + GENERATED_PATH + mainFile.getName() + ".h", Conversion.indentString(mainFile.getHeaderCode(), 2));
- FileUtils.saveFile(path + GENERATED_PATH + mainFile.getName() + ".c", Conversion.indentString(mainFile.getMainCode(), 2));
- }
-
- for(ComponentFiles componentFile: componentFiles) {
- FileUtils.saveFile(path + GENERATED_PATH + componentFile.getName() + ".h", Conversion.indentString(componentFile.getFullHeaderCode/*Soclib*/(), 2));
- FileUtils.saveFile(path + GENERATED_PATH + componentFile.getName() + ".cpp", Conversion.indentString(taskFile.getMainCode(), 2));
- }
-
- // Standard Makefile
- makeMakefileSrc(GENERATED_PATH);
- FileUtils.saveFile(path + "Makefile.src", makefile_src);
-
- // Makefile for SocLib
- makeMakefileSocLib();
- FileUtils.saveFile(path + "Makefile.soclib", makefile_SocLib);
- }
-
- public Vector<?> getWarnings() {
- return warnings;
- }
-
- public void generateSystemCAms(boolean _debug, boolean _tracing) {
- debug = _debug;
- tracing = _tracing;
-
- mainFile = new MainFileSoclib("main");
-
- if (avspec.hasApplicationCode() && includeUserCode) {
- //mainFile.appendToBeforeMainCode("/* User code */\n");
- mainFile.appendToBeforeMainCode(avspec.getApplicationCode());
- //mainFile.appendToBeforeMainCode("\n/* End of User code */\n\n");
- }
-
- makeComponents();
-
- }
-
-
-
- public int FindCPUidFromTask(SystemCamsBlock block){
- List<SystemCamsTask> tasks = avddspec.getAllMappedTask();
-
- for (SystemCamsTask task : tasks){
- if (task.getTaskName().equals(block.getName())){
- return task.getCPUNo();
- }
- }
-
- return -1;
- }
-
- public void makeComponents() {
- componentFiles.add(componentFile);
- }
-
-
- public void defineAllSignal(ComponentFile _componentFile) {
-
- for () {
-
- _componentFile.addToMainCode( "" + CR);
- }
- _componentFile.addToMainCode(CR);
- }
-
- public void defineAllMethods(SystemCamsBlock _block, TaskFileSoclib _taskFile) {
- Vector<String> allNames = new Vector<String>();
- for (SystemCamsMethod am: _block.getMethods()) {
- makeMethod(_block, am, allNames, _taskFile);
- }
-
- // Make method of father
- makeFatherMethod(_block, _block, allNames, _taskFile);
- }
-
- private void makeFatherMethod(SystemCamsBlock _originBlock, SystemCamsBlock _currentBlock, Vector<String> _allNames, componentFile _componentFile) {
- if (_currentBlock.getFather() == null) {
- return;
- }
-
- for (SystemCamsMethod am: _currentBlock.getFather().getMethods()) {
- makeMethod(_originBlock, am, _allNames, _taskFile);
- }
-
- makeFatherMethod(_originBlock, _currentBlock.getFather(), _allNames, _taskFile);
- }
-
- private void makeMethod(SystemCamsBlock _block, SystemCamsMethod _am, Vector<String> _allNames, TaskFileSoclib _taskFile) {
-
- }
-
-
- private String makeChannelAction(SystemCamsBlock _block, SystemCamsStateMachineElement asme) {
-
- }
-
-
- public String makeCanalDec(SystemCamsBlock _block) {
-
- }
- //************************************************************************RG
-
- public void makeMainFunction(SystemCamsBlock _block, TaskFileSoclib _taskFile) {
- }
-
-}
diff --git a/src/main/java/camstranslator/toTopcell/Constants.java b/src/main/java/camstranslator/toTopcell/Constants.java
deleted file mode 100755
index 6752ac2277c61be2829165ab41442e6af4287b10..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/Constants.java
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
-
-/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
-
-package ddtranslatorSoclib.toTopCell;
-
-public class Constants {
-
- static private String constants;
- private final static String CR = "\n";
- private final static String CR2 = "\n\n";
-
- Constants(){
- }
- public static String getConstants() {
-
- constants = "
- ////////////////////////////////////////////////////////////////////////
- // System components constants.
- ////////////////////////////////////////////////////////////////////////
-
-
-constants +=
-
-+ CR2
-
- ////////////////////////////////////////////////////////////////////////
- // Initial conditions and stimuli.
- ////////////////////////////////////////////////////////////////////////
-
-
-
- }
- return constants;
-}
diff --git a/src/main/java/camstranslator/toTopcell/Declaration.java b/src/main/java/camstranslator/toTopcell/Declaration.java
deleted file mode 100755
index 95030f3a27473e7378ae253f9094b9673887431e..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/Declaration.java
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015
- v2.1 Daniela GENIUS, 2016, 2017 */
-
-package ddtranslatorSoclib.toTopCell;
-
-import ddtranslatorSoclib.*;
-import avatartranslator.AvatarRelation;
-import avatartranslator.AvatarBlock;
-import avatartranslator.AvatarSignal;
-import avatartranslator.AvatarSpecification;
-
-public class Declaration {
- public static SCamsSpecification spec;
- private static String CR = "\n";
- private static String CR2 = "\n\n";
-
-
- public static String getDeclarations(SCamsSpecification _spec) {
- spec =_spec;
-
- String declaration = " ////////////////////////////////////////////////////////////////////////
- // Model instantiation.
- ////////////////////////////////////////////////////////////////////////
-+ CR2;
-
-
-
-return declaration;
- }
-
-}
\ No newline at end of file
diff --git a/src/main/java/camstranslator/toTopcell/Header.java b/src/main/java/camstranslator/toTopcell/Header.java
deleted file mode 100755
index 6decdf31a29e5d10638596947f8d54e04d847d02..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/Header.java
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
-
-/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
-
-package ddtranslatorSoclib.toTopCell;
-
-public class Header {
-
- static private String header;
- private final static String CR = "\n";
- private final static String CR2 = "\n\n";
-
- Header(){
- }
- public static String getHeader() {
-
- header = "//-------------------------------Header------------------------------------" + CR2
- + "#include <systemc-ams>" + CR
- + "#include \"generic_tdf_compoent.h\"" + CR2;
-
-
- header+= "int sc_main(int argc, char* argv[]) {
- using namespace sc_core;
- using namespace sca_util;
- using namespace heter;
-
-" + CR2;
- }
- return header;
-}
diff --git a/src/main/java/camstranslator/toTopcell/NetList.java b/src/main/java/camstranslator/toTopcell/NetList.java
deleted file mode 100755
index 74870d23ee8af377e4bed015477f95024caafd69..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/NetList.java
+++ /dev/null
@@ -1,448 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
-
-package ddtranslatorSoclib.toTopCell;
-
-import ddtranslatorSoclib.AvatarCPU;
-import ddtranslatorSoclib.AvatarCoproMWMR;
-import ddtranslatorSoclib.AvatarRAM;
-import ddtranslatorSoclib.AvatarTTY;
-
-public class NetList {
- public static final String NAME_CLK = "signal_clk";
- public static final String CR = "\n";
- public static final String CR2 = "\n\n";
- private static final String NAME_RST = "signal_resetn";
- private static boolean tracing;
-
- public static String getNetlist(String icn, boolean _tracing) {
- int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
-
- tracing = _tracing;
-
- String netlist;
-
- netlist = CR2 + "//------------------------------Netlist---------------------------------" + CR2;
-
- netlist = netlist + "// icu" + CR2;
- netlist = netlist + " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));" + CR2;
-
- netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
- netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
-
- netlist = netlist + " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");" + CR;
-
- netlist = netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");" + CR2;
- netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
- netlist = netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
- netlist = netlist + " {" + CR;
- netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
- netlist = netlist + " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
- netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
- netlist = netlist + " }" + CR2;
- netlist = netlist + " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR2;
-
- netlist = netlist + " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
- netlist = netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
-
- netlist = netlist + "///////////////// cpus" + CR2;
-
- netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
- netlist = netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
- netlist = netlist + " // configure het_rom" + CR;
- netlist = netlist + " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
-
- netlist = netlist + " // add cpu node to device tree" + CR;
- netlist = netlist + " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + "// connect cpu" + CR;
- netlist = netlist + " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);" + CR;
- if(icn=="vgmn")
- {
- netlist = netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
- }
- else{
- netlist = netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
- }
-
- netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
- netlist = netlist + " }" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + " vcihetrom.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcifdtrom.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcirom.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcisimhelper.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcirttimer.p_clk(signal_clk);" + CR;
-
- netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vcifdtrom.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vcirom.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vcisimhelper.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vcirttimer.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
-
- netlist = netlist + " vcifdtrom.p_vci(signal_vci_vcifdtrom);" + CR;
- netlist = netlist + " vcirom.p_vci(signal_vci_vcirom);" + CR;
- netlist = netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
- netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
- netlist = netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
-
- if(icn=="vgmn"){
- netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
- netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" + CR;
- netlist = netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
- netlist = netlist + " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
- netlist = netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
- netlist = netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" + CR2;
- netlist = netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
- netlist = netlist + " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
- netlist = netlist + " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
- netlist = netlist + " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
- }
- else{
- netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
- netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" + CR;
- netlist = netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
- netlist = netlist + " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
- netlist = netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
- netlist = netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" + CR2;
- netlist = netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
- netlist = netlist + " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
- netlist = netlist + " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
- netlist = netlist + " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
- }
-
- if(nb_clusters==0){
- netlist = netlist + "// RAM netlist" + CR2;
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
-
- netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
- if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
- }
- else{
- netlist = netlist + "vgsb.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
- }
- }
- }
-
- /* clustered version */
- /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster*/
- else{
- int i;
- netlist = netlist + "// RAM netlist" + CR2;
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
-
- netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
- //target number for local cluster: this is set at avatardd creation
- netlist = netlist + "crossbar"+ram.getNo_cluster()+".p_to_target["+ram.getNo_target()+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
- }
-
- //one mwmr ram and one mwmrdram per cluster are added transparently
-
- /*convention for local target ids on cluster :
- channel: 0
- mwmr_ram: 1
- mwmrd_ram: 2
- locks: 3
- ram: 4
- tty: 5
- */
-
- /* for(i=0;i<nb_clusters;i++){
- netlist = netlist + "crossbar"+i+".p_to_target["+1+"](signal_vci_mwmr_ram"+i+");" + CR2;
- //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
- netlist = netlist + "crossbar"+i+".p_to_target["+2+"](signal_vci_mwmrd_ram"+i+");" + CR2;
- //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
- } */
- }
-
- if(nb_clusters==0){
- /* we can have several TTYs and each is associated to the fdtrom */
- if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
- }else{ /* vgsb */
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
- }
- }else{
- /* cluster case */
- if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgmn.p_to_target["+6+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgmn.p_to_target["+7+"](signal_vci_bdt);" + CR;
- }else{
- netlist = netlist + "vgsb.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgsb.p_to_target["+6+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgsb.p_to_target["+7+"](signal_vci_bdt);" + CR;
- }
- }
- //netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty\",\"soclib:vci_multi_tty\");" + CR2;
-
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
- netlist = netlist + "vcifdtrom.end_node();;" + CR2;
-
- netlist = netlist + "// TTY netlist" + CR2;
- int i=0;
-
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
- netlist = netlist + tty.getTTYName()+".p_clk(signal_clk);" + CR;
- netlist = netlist + tty.getTTYName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist + tty.getTTYName()+".p_vci(signal_vci_tty"+i+");" + CR2;
- int no_irq_tty=0;
- if(nb_clusters==0){
-
- if(icn=="vgmn"){
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+i+"\");" + CR2;
- netlist = netlist + "vgmn.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
- netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
- }else{
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+tty.getNo_tty()+"\");" + CR2;
- netlist = netlist + "vgsb.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
- netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
- }
- }
-
- //we have a clustered architecture: identify local crossbar
- else{
- int j;
- for(j=0;j<nb_clusters;j++){
- netlist = netlist + "crossbar"+j+".p_to_target["+tty.getNo_target()+"](signal_vci_tty"+j+");" + CR2;
- //recalculate irq addresses, 5 devices generating irq per cluster
- netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+(tty.getNo_cluster()*5)+"]);" + CR2;
- }
- }
- i++;
- //One ICU per cluster per default
- no_irq_tty+=6;//if there is more than one tty, irq >5
- }
-
- //////////////// fdrom
-
- netlist = netlist + "{" + CR2;
- netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR; netlist = netlist + " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR;
- netlist = netlist + "}" + CR2;
-
- //////////////// ethernet
-
- netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
- netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
- netlist = netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
-
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");" + CR;
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
- netlist = netlist + "vcifdtrom.end_node();" + CR;
-
- //////////////// block device
-
- netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
- netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
- netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
-
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");" + CR;
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
- netlist = netlist + "vcifdtrom.end_node();" + CR;
-
- //////////////// fd access
- netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
-
- netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
- netlist = netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
-
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");" + CR;
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
- netlist = netlist + "vcifdtrom.end_node();" + CR2;
-
- //////////////// locks
-
- netlist = netlist + "vcilocks.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcilocks.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcilocks.p_vci(signal_vci_vcilocks);" + CR;
-
- ////////////////MWMR controller; hypothesis 1 per coprocessor
- // if(nb_cluster == 0){
- i=0;
- for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- //a coprocessor with FIFO interface
- netlist = netlist +copro.getCoprocName()+".p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist + copro.getCoprocName()+".p_"+i+"_ctrl(signal_fifo_"+i+"_ctrl);" + CR;
- //and its mwmr controller
- netlist = netlist + "mwmr"+i+".p_clk(signal_clk);" + CR;
- netlist = netlist + "mwmr"+i+".p_resetn(signal_resetn);" + CR;
- netlist = netlist + "mwmr"+i+".p_vci_initiator(signal_mwmr_"+i+"initiator);" + CR;
- netlist = netlist + "mwmr"+i+".p_vci_target(signal_mwmr_"+i+"_target);" + CR;
- netlist = netlist + copro.getCoprocName()+".p_"+i+"_ctrl(signal_fifo_"+i+"_ctrl);" + CR;
- }
-
-
- //If there is a spy, add logger or stats to vci interface
-
- i=0;
- for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
- int number = cpu.getNo_proc();
- if(cpu.getMonitored()==1){
- netlist=netlist+CR+
- "logger"+i+".p_clk(signal_clk);" +CR+
- "logger"+i+".p_resetn(signal_resetn);" +CR+
- "logger"+i+".p_vci(signal_vci_m["+number+"]);" +CR2;
- i++;
- }
-
- }
- int j=0;
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- if (ram.getMonitored()==1){
- int number = number = ram.getIndex();
- netlist += "logger"+i+".p_clk(signal_clk);" + CR;
- netlist += "logger"+i+".p_resetn(signal_resetn);" + CR;
- netlist += "logger"+i+".p_vci(signal_vci_vciram"+number+");" + CR2;
- i++;
- }
- else{
-
- if (ram.getMonitored()==2){
- int number = number = ram.getIndex();
- netlist += "mwmr_stats"+j+".p_clk(signal_clk);" + CR;
- netlist += "mwmr_stats"+j+".p_resetn(signal_resetn);" + CR;
- netlist += "mwmr_stats"+j+".p_vci(signal_vci_vciram"+number+");" + CR2;
- j++;
- }
- }
- }
-
- //generate trace file if marked trace option
-
- if(tracing){
- netlist += "sc_trace_file *tf;" + CR;
- netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
- netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
- netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
-
- netlist += "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");" + CR;
- netlist += "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");" + CR;
- netlist += "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
- netlist += "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
- netlist += "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");" + CR;
- netlist += "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");" + CR;
-
- for(i=0;i<TopCellGenerator.avatardd.getNb_init();i++){
- netlist += "sc_trace(tf,signal_vci_m["+ i +"] ,\"signal_vci_m["+ i +"]\");" + CR;
- }
-
- i=0;
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
-
- netlist += "sc_trace(tf,signal_vci_tty"+tty.getNo_tty()+",\"TTY"+tty.getNo_tty()+"\");" + CR;
- netlist += "sc_trace(tf,signal_xicu_irq["+ i +"] ,\"signal_xicu_irq["+ i +"]\");" + CR;
- i++;
- }
-
- netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
- netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
- netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- if (ram.getMonitored()==0){
- netlist += "sc_trace(tf,signal_vci_vciram"+ram.getIndex()+",\"Memory"+ram.getIndex()+"\");" + CR;
- }
- }
- }
- netlist = netlist + " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
- netlist = netlist + " signal_resetn = false;" + CR;
- netlist = netlist + " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
- netlist = netlist + " signal_resetn = true;" + CR;
- netlist = netlist + " sc_core::sc_start();" + CR;
- if(tracing){
- netlist += "sc_close_vcd_trace_file(tf);" + CR;
- }
- netlist = netlist + CR + " return EXIT_SUCCESS;"+ CR;
- netlist = netlist +"}" + CR;
- return netlist;
- }
-}
\ No newline at end of file
diff --git a/src/main/java/camstranslator/toTopcell/Signal.java b/src/main/java/camstranslator/toTopcell/Signal.java
deleted file mode 100755
index d06927e1ce56cdac85da57da1f05111562c386ba..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/Signal.java
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-/* This class generates the lines of the topcell where the signals are declared*/
-
-/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
-
-package ddtranslatorSoclib.toTopCell;
-
-import ddtranslatorSoclib.AvatarCoproMWMR;
-import ddtranslatorSoclib.AvatarRAM;
-import ddtranslatorSoclib.AvatarTTY;
-
-public class Signal {
-
- private final static String CR = "\n";
- private final static String CR2 = "\n\n";
-
- public static String getSignal() {
-
- String signal = CR2;
-
-signal +="////////////////////////////////////////////////////////////////////////
- // Model instantiation.
- ////////////////////////////////////////////////////////////////////////
-
-// TDF Signals
- sca_tdf::sca_signal
-
-signal +="// Digital Signals
-sc_core::sc_signal
-
-
-}
- return signal;
- }
-}
diff --git a/src/main/java/camstranslator/toTopcell/Simulation.java b/src/main/java/camstranslator/toTopcell/Simulation.java
deleted file mode 100755
index 135fb4c481e3c103be4a378f7d2552d40b8fe500..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/Simulation.java
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- * Daniela Genius, Lip6, UMR 7606
- *
- * ludovic.apvrille AT enst.fr
- * daniela.genius@lip6.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-/* authors: v1.0 Raja GATGOUT 2014
- v2.0 Daniela GENIUS, Julien HENON 2015 */
-
-package ddtranslatorSoclib.toTopCell;
-
-public class Simulation {
-
- private static String simulation;
-
- private final static String CR = "\n";
- private final static String CR2 = "\n\n";
-
- public Simulation(){
- }
-
- //Dans un premier temps, nous n'implémentons pas encore le tracing
-
- public static String getSimulation(){
- simulation = "
-////////////////////////////////////////////////////////////////////////
- // Tracing and simulation
- ////////////////////////////////////////////////////////////////////////
-
-
- try {
- sc_start(t_stop);
- } catch (const std::exception& e) {
- std::cerr << e.what() << std::endl;
- }
-
- sca_close_tabular_trace_file(tfp);
-
- sc_stop();
- return sc_report_handler::get_count(SC_ERROR);
- }"+CR2;
-
- return simulation;
- }
-}
diff --git a/src/main/java/camstranslator/toTopcell/TopCellGenerator.java b/src/main/java/camstranslator/toTopcell/TopCellGenerator.java
deleted file mode 100755
index 3942fc9b2d93a49e804325fd9b02bdbe0d2bb1d9..0000000000000000000000000000000000000000
--- a/src/main/java/camstranslator/toTopcell/TopCellGenerator.java
+++ /dev/null
@@ -1,146 +0,0 @@
-
-/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- Daniela Genius, Lip6, UMR 7606
-
- ludovic.apvrille AT enst.fr
- daniela.genius@lip6.fr
-
- This software is a computer program whose purpose is to allow the
- edition of TURTLE analysis, design and deployment diagrams, to
- allow the generation of RT-LOTOS or Java code from this diagram,
- and at last to allow the analysis of formal validation traces
- obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- from INRIA Rhone-Alpes.
-
- This software is governed by the CeCILL license under French law and
- abiding by the rules of distribution of free software. You can use,
- modify and/ or redistribute the software under the terms of the CeCILL
- license as circulated by CEA, CNRS and INRIA at the following URL
- "http://www.cecill.info".
-
- As a counterpart to the access to the source code and rights to copy,
- modify and redistribute granted by the license, users are provided only
- with a limited warranty and the software's author, the holder of the
- economic rights, and the successive licensors have only limited
- liability.
-
- In this respect, the user's attention is drawn to the risks associated
- with loading, using, modifying and/or developing or reproducing the
- software by the user in light of its specific status of free software,
- that may mean that it is complicated to manipulate, and that also
- therefore means that it is reserved for developers and experienced
- professionals having in-depth computer knowledge. Users are therefore
- encouraged to load and test the software's suitability as regards their
- requirements in conditions enabling the security of their systems and/or
- data to be ensured and, more generally, to use and operate it in the
- same conditions as regards security.
-
- The fact that you are presently reading this means that you have had
- knowledge of the CeCILL license and that you accept its terms.
-*/
-
-/* Generator of the top cell for SystemC simulation
-of heterogeneous platforms with SoCLib virtual component
- library ans SystemC AMS extension */
-
-/* authors:
- v1.0 Daniela GENIUS, Côme Demarigny 2017 */
-
-package ddtranslatorSoclib.toTopCell;
-
-import avatartranslator.AvatarRelation;
-import avatartranslator.AvatarSpecification;
-import ddtranslatorSoclib.*;
-import ddtranslatorSoclib.toSoclib.*;
-
-import java.io.*;
-import java.util.ArrayList;
-import java.util.List;
-
-public class TopCellGenerator
-{
- private static final String MAPPING_TXT = "mapping.txt";
- public static SystemCAMSSpecification scamsspec;
-
- public String VCIparameters;
- public String config;
- public String mainFile;
- public String src;
- public String top;
- public final String DOTH = ".h";
- public final String DOTCPP = ".cpp";
- public final String SYSTEM_INCLUDE = "#include \"systemc.h\"";
- public final String CR = "\n";
- public final String CR2 = "\n\n";
- public final String SCCR = ";\n";
- public final String EFCR = "}\n";
- public final String EFCR2 = "}\n\n";
- public final String EF = "}";
- public final String COTE = "";
- public final String NAME_RST = "signal_resetn";
- public final String TYPEDEF = "typedef";
-
- private final static String GENERATED_PATH = "generated_topcell" + File.separator;
- private boolean tracing;
- public TopCellGenerator(AvatarddSpecification dd, boolean _tracing, AvatarSpecification _avspec){
- avatardd = dd;
- tracing =_tracing;
- avspec =_avspec;
- }
-
- public String generateTopCell() {
- String icn;
-
- /* first test validity of the hardware platform*/
-
- /* if there is one VGMN, this is the central interconnect */
- if(TopCellGenerator.avatardd.getNbVgmn()>1){
- System.out.println("***Warning: No more than one central VGMN***");
- }
- if(TopCellGenerator.avatardd.getNbVgmn()==1){
- System.out.println("***VGMN based***");
- icn="vgmn";
- }
- else{
- System.out.println("***VGSB based ***");
- icn="vgsb";
- }
-
- String top = Header.getHeader() +
- Constants.getConstants() +
- Declaration.getDeclarations(avspec) +
- Signal.getSignal() +
- NetList.getNetlist(icn,tracing) +
- Simulation.getSimulation();
- return (top);
- }
-
- public List<String> readInMapping() {
- List<String> mappingLines = new ArrayList<String>();
- try {
- BufferedReader in = new BufferedReader(new FileReader(MAPPING_TXT));
- String line = null;
- while ((line = in.readLine()) != null) {
- System.out.println(" Line read : " + line);
- mappingLines.add(line); }
- in.close();
- } catch (IOException e) {
- e.printStackTrace();
- }
-
- return mappingLines;
- }
-
- public void saveFile(String path) {
- try {
- System.err.println(path + GENERATED_PATH + "top.cc");
- FileWriter fw = new FileWriter(path + GENERATED_PATH + "/top.cc");
- top = generateTopCell();
- fw.write(top);
- fw.close();
- } catch (IOException ex) {
- }
- }
-
-
-}
diff --git a/src/main/java/ui/window/JDialogAvatarExecutableCodeGeneration.java b/src/main/java/ui/window/JDialogAvatarExecutableCodeGeneration.java
index 4700b0ebd3a0fb9eb844c6e4f875c78f48d6e5a3..31e2ba5bc595fb150a0b86754a046c35f89a09ac 100644
--- a/src/main/java/ui/window/JDialogAvatarExecutableCodeGeneration.java
+++ b/src/main/java/ui/window/JDialogAvatarExecutableCodeGeneration.java
@@ -79,7 +79,7 @@ public class JDialogAvatarExecutableCodeGeneration extends javax.swing.JFrame im
//private String textSysC3 = "with";
private String textSysC4 = "Run code:";
private String textSysC5 = "Run code and trace events (if enabled at code generation):";
- private String textSysC6 = "Run code in soclib / mutekh:";
+ //private String textSysC6 = "Run code in soclib / mutekh:";
private String textSysC8 = "Show trace from file:";
private String textSysC9 = "Show trace from soclib file:";
@@ -352,12 +352,12 @@ public class JDialogAvatarExecutableCodeGeneration extends javax.swing.JFrame im
exe3 = new JTextField(pathExecute + " " + pathCode + File.separator + "trace.txt", 100);
jp03.add(exe3, c03);
- exesoclib = new JRadioButton(textSysC6, false);
- exesoclib.addActionListener(this);
- exegroup.add(exesoclib);
- jp03.add(exesoclib, c03);
- exe4 = new JTextField(pathExecuteSoclib, 100);
- jp03.add(exe4, c03);
+ //exesoclib = new JRadioButton(textSysC6, false);
+ //exesoclib.addActionListener(this);
+ //exegroup.add(exesoclib);
+ //jp03.add(exesoclib, c03);
+ //exe4 = new JTextField(pathExecuteSoclib, 100);
+ //jp03.add(exe4, c03);
exe.setSelected(selectedRun == 0);
exetrace.setSelected(selectedRun == 1);
@@ -496,7 +496,7 @@ public class JDialogAvatarExecutableCodeGeneration extends javax.swing.JFrame im
exe2.setEnabled(selectedRun == 0);
exe3.setEnabled(selectedRun == 1);
- exe4.setEnabled(selectedRun == 2);
+ //exe4.setEnabled(selectedRun == 2);
}
@@ -665,7 +665,7 @@ public class JDialogAvatarExecutableCodeGeneration extends javax.swing.JFrame im
if (selectedRun == 1) {
cmd = exe3.getText();
} else {
- cmd = exe4.getText();
+ //cmd = exe4.getText();
}
}