diff --git a/simulators/c++2/src_simulator/TMLTransaction.h b/simulators/c++2/src_simulator/TMLTransaction.h
index be386432218451f81eb09829ac4ff3829ee9553a..a4a3df15b468b092ad6952ffaea8f8b271e4aa77 100644
--- a/simulators/c++2/src_simulator/TMLTransaction.h
+++ b/simulators/c++2/src_simulator/TMLTransaction.h
@@ -81,7 +81,7 @@ class TMLTransaction {
/**
\return Start time
*/
- inline TMLTime getStartTime() const {return _startTime;}
+ inline TMLTime getStartTime() const {return _startTime;}
///Returns the start time of the operational part of the transaction
/**
\return Start time of the operational part
@@ -278,6 +278,7 @@ class TMLTransaction {
vcdTransVisState _transVcdOutputState;
//state of transaction for VCD output
bool _endState;
+
///previous end time for the cpu VCD output
// unsigned int _previousTransEndTime;
//device executes the current device
@@ -298,6 +299,7 @@ class TMLTransaction {
static MemPoolNoDel<TMLTransaction> memPool;
///Current Transaction ID
static ID _ID;
+
};
#endif
diff --git a/simulators/c++2/src_simulator/app/TMLChannel.cpp b/simulators/c++2/src_simulator/app/TMLChannel.cpp
index f014e8ad81c0a84b0febf39ba0187dff5f60e502..0f2bb5bafd489365fcb12cee6dd3c2f40bc99552 100755
--- a/simulators/c++2/src_simulator/app/TMLChannel.cpp
+++ b/simulators/c++2/src_simulator/app/TMLChannel.cpp
@@ -67,7 +67,7 @@ BusMaster* TMLChannel::getNextMaster(TMLTransaction* iTrans){
}
BusMaster* TMLChannel::getFirstMaster(TMLTransaction* iTrans){
- //std::cout<<"get First master"<<std::endl;
+ std::cout<<"get First master"<<std::endl;
//if (iTrans->getCommand()->getTask()==_writeTask){
//std::cout << "fima 1\n";
if (_masters==0 || _slaves==0 || _numberOfHops==0 ) {return 0;}
diff --git a/simulators/c++2/src_simulator/app/TMLTask.cpp b/simulators/c++2/src_simulator/app/TMLTask.cpp
index 44e942fdc466cf5631547629bd0f7f8916d380eb..4df24602a0f495474707dfdaf820d651f6f31b93 100755
--- a/simulators/c++2/src_simulator/app/TMLTask.cpp
+++ b/simulators/c++2/src_simulator/app/TMLTask.cpp
@@ -362,7 +362,7 @@ unsigned int TMLTask::getState() const{
}
TMLTransaction* TMLTask::getNextTransaction(TMLTime iEndSchedule) const{
- //std::cout<<"TMLTask get next trans"<<std::endl;
+ std::cout<<"TMLTask get next trans"<<std::endl;
return (_currCommand==0)?0:_currCommand->getCurrTransaction();
//return (_currCommand==0 || _isScheduled)?0:_currCommand->getCurrTransaction();
}
diff --git a/simulators/c++2/src_simulator/app/TMLWriteCommand.cpp b/simulators/c++2/src_simulator/app/TMLWriteCommand.cpp
index 7001e2e016529efcf98a6367fa1a4e5788682a9d..8f8a4c9a6b52da35d10a128ed9dd7ed2b8631923 100755
--- a/simulators/c++2/src_simulator/app/TMLWriteCommand.cpp
+++ b/simulators/c++2/src_simulator/app/TMLWriteCommand.cpp
@@ -50,13 +50,13 @@ TMLWriteCommand::TMLWriteCommand(ID iID, TMLTask* iTask, LengthFuncPointer iLeng
}
void TMLWriteCommand::execute(){
- //std::cout << "in write " << _channel << "\n";
- //std::cout << "Length of write:" << _length << std::endl;
+ std::cout << "in write " << _channel << "\n";
+ std::cout << "Length of write:" << _length << std::endl;
_channel->write();
//std::cout << "channel not zero\n";
- //std::cout << _currTransaction->getVirtualLength() << " samples written\n";
+ std::cout << _currTransaction->getVirtualLength() << " samples written\n";
_progress+=_currTransaction->getVirtualLength();
- //std::cout << "WriteCommand progress: " << _progress << std::endl << std::endl;
+ std::cout << "WriteCommand progress: " << _progress << std::endl << std::endl;
//_task->setEndLastTransaction(_currTransaction->getEndTime());
_task->addTransaction(_currTransaction);
//std::cout << "Trans written: " << _currTransaction->toString() << "\n";
diff --git a/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp b/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp
index 2b6d56954494eb0ed6cf5b32c9401f48d4985450..ee88335d2e58531c46ac4564cca2183e0a956fa6 100755
--- a/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp
+++ b/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp
@@ -61,7 +61,6 @@ void TMLbrbwChannel::testRead(TMLTransaction* iTrans){
}
void TMLbrbwChannel::write(){
- //std::cout<<"write!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"<<std::endl;
#ifdef LOSS_ENABLED
if (_maxNbOfLosses > _nbOfLosses){
TMLLength aLostBytes = _writeTrans->getVirtualLength() * _lossRate + _lossRemainder;
@@ -70,12 +69,12 @@ void TMLbrbwChannel::write(){
//aLostBytes /= 100;
aLostBytes = min(aLostBytes/100, _maxNbOfLosses - _nbOfLosses);
_content += _writeTrans->getVirtualLength() - aLostBytes;
- //std::cout << "Bytes to write: " << _writeTrans->getVirtualLength()-aLostBytes << "\n";
- //std::cout << "Bytes lost: " << aLostBytes << "\n";
+ std::cout << "Bytes to write: " << _writeTrans->getVirtualLength()-aLostBytes << "\n";
+ std::cout << "Bytes lost: " << aLostBytes << "\n";
_nbOfLosses += aLostBytes;
} else {
#endif
- //std::cout << "write all " << _writeTrans->getVirtualLength() << "\n";
+ std::cout << "write all " << _writeTrans->getVirtualLength() << "\n";
_content+=_writeTrans->getVirtualLength();
#ifdef LOSS_ENABLED
}
diff --git a/simulators/c++2/src_simulator/arch/Bus.cpp b/simulators/c++2/src_simulator/arch/Bus.cpp
index 4f5e782a26cde7b62ae7cf6a223701fbd53c6e19..ecafa4852a429a55971104ec7f6d6b956349f31f 100644
--- a/simulators/c++2/src_simulator/arch/Bus.cpp
+++ b/simulators/c++2/src_simulator/arch/Bus.cpp
@@ -91,7 +91,7 @@ void Bus::schedule(){
//Adds the transaction determined by the scheduling algorithm to the internal list of scheduled transactions
bool Bus::addTransaction(TMLTransaction* iTransToBeAdded){
- //std::cout << "Bus add trans ####" << _nextTransaction << "\n";
+ std::cout << "Bus add trans ####" << _nextTransaction << "\n";
_endSchedule = _nextTransaction->getEndTime();
//std::cout << "set end time to " << _endSchedule << "\n";
//_transactList.push_back(_nextTransaction);
@@ -107,7 +107,7 @@ bool Bus::addTransaction(TMLTransaction* iTransToBeAdded){
#endif
_nextTransaction = 0;
_schedulingNeeded=true;
- //std::cout << "End Bus add trans\n";
+ std::cout << "End Bus add trans\n";
return true;
}
@@ -257,14 +257,14 @@ void Bus::latencies2XML(std::ostringstream& glob, unsigned int id1, unsigned int
//Returns the next signal change (for vcd output)
void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
- //std::cout<<"bus getnext"<<std::endl;
+ std::cout<<"bus getnext"<<std::endl;
//std::ostringstream outp;
//std::cout << _transactList.size() << " elements in List of " << _name << std::endl;
if (iInit){
_posTrasactListVCD=_transactList.begin();
_previousTransEndTime=0;
_vcdOutputState=INIT_BUS;
- //std::cout<<"bus init"<<std::endl;
+ std::cout<<"bus init"<<std::endl;
}
if (_posTrasactListVCD == _transactList.end()){
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_BUS) << "bus" << _ID;
@@ -272,13 +272,13 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//oNoMoreTrans=true;
//return _previousTransEndTime;
new (oSigData) SignalChangeData(END_IDLE_BUS, _previousTransEndTime, this);
- //std::cout<<"bus end "<<std::endl;
+ std::cout<<"bus end "<<std::endl;
}else{
TMLTransaction* aCurrTrans=*_posTrasactListVCD;
//oNoMoreTrans=false;
switch (_vcdOutputState){
case END_READ_BUS:
- //std::cout<<"BUS END_READ_BUS"<<std::endl;
+ std::cout<<"BUS END_READ_BUS"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
@@ -297,7 +297,7 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return _previousTransEndTime;
break;
case END_WRITE_BUS:
- //std::cout<<"BUS END_WRTIE_BUS"<<std::endl;
+ std::cout<<"BUS END_WRTIE_BUS"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
@@ -316,7 +316,7 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return _previousTransEndTime;
break;
case INIT_BUS:
- //std::cout<<"BUS INIT_BUS"<<std::endl;
+ std::cout<<"BUS INIT_BUS"<<std::endl;
if (aCurrTrans->getStartTimeOperation()!=0){
_vcdOutputState=END_IDLE_BUS;
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_BUS) << "bus" << _ID;
@@ -326,7 +326,7 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
return;
}
case END_IDLE_BUS:
- //std::cout<<"BUS END_IDLE_BUS"<<std::endl;
+ std::cout<<"BUS END_IDLE_BUS"<<std::endl;
if (aCurrTrans->getCommand()->getTask()==aCurrTrans->getChannel()->getBlockedReadTask()){
_vcdOutputState=END_READ_BUS;
new (oSigData) SignalChangeData(END_READ_BUS, aCurrTrans->getStartTimeOperation(), this);
diff --git a/simulators/c++2/src_simulator/arch/CPU.cpp b/simulators/c++2/src_simulator/arch/CPU.cpp
index 980964ea42163a533d969b32c66daa15efc7f2ca..7eb14f6474a3de5ef686b9c814ad4caaf953ad75 100644
--- a/simulators/c++2/src_simulator/arch/CPU.cpp
+++ b/simulators/c++2/src_simulator/arch/CPU.cpp
@@ -51,7 +51,7 @@ double CPU::averageLoad (unsigned int n) const{
_maxEndTime=max(_maxEndTime,_endTime);
}
}
- //std::cout<<"max end time is "<<_maxEndTime<<std::endl;
+ std::cout<<"max end time is "<<_maxEndTime<<std::endl;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
if( (*i)->getTransactCoreNumber() == n ){
_averageLoad += (*i)->getEndTime() - (*i)->getStartTime();
@@ -124,8 +124,8 @@ void CPU::schedule2HTML(std::ofstream& myfile) const {
TMLTime aCurrTime = 0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
- //std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
- //std::cout<<"time : "<<_cycleTime<<std::endl;
+ std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
+ std::cout<<"time : "<<_cycleTime<<std::endl;
//std::cout << "CPU:calcSTL: html of CPU " << _name << ": " << (*i)->toString() << std::endl;
if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
TMLTransaction* aCurrTrans = *i;
diff --git a/simulators/c++2/src_simulator/arch/FPGA.cpp b/simulators/c++2/src_simulator/arch/FPGA.cpp
index 69f2fb247692a3956f9977e934f5fef23fdf40b8..7ac5dab1c1613171968b210e216a1445de2f6c52 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.cpp
+++ b/simulators/c++2/src_simulator/arch/FPGA.cpp
@@ -63,6 +63,9 @@ FPGA::FPGA( ID iID,
,_cyclesPerExecc(iCyclesPerExecc)
,_taskNumber(0)
,_currTaskNumber(0)
+ ,_reconfigNumber(0)
+ ,_maxEndTime(0)
+
{}
@@ -80,11 +83,15 @@ void FPGA::streamBenchmarks(std::ostream& s) const{
}
TMLTransaction* FPGA::getNextTransaction(){
+#ifdef DEBUG_FPGA
std::cout<<"fpga getNextTransaction"<<_name<<" ";
- #ifdef BUS_ENABLED
+#endif
+#ifdef BUS_ENABLED
if (_masterNextTransaction==0 || _nextTransaction==0){
+#ifdef DEBUG_FPGA
if(_masterNextTransaction == 0) std::cout<<"master is 0"<<std::endl;
if(_nextTransaction==0) std::cout<<"nexttrans is 0"<<std::endl;
+#endif
//if(_nextTransaction) std::cout<<_nextTransaction->toString()<<std::endl;
return _nextTransaction;
//return 0;
@@ -101,7 +108,9 @@ TMLTransaction* FPGA::getNextTransaction(){
aResult = aTempMaster->accessGranted();
// std::cout << "5" << std::endl;
}
+#ifdef DEBUG_FPGA
if(_nextTransaction)std::cout<<"haha1"<<_nextTransaction->toString()<<std::endl;
+#endif
return (aResult)?_nextTransaction:0;
}
#else
@@ -112,7 +121,9 @@ TMLTransaction* FPGA::getNextTransaction(){
}
void FPGA::calcStartTimeLength(){
+#ifdef DEBUG_FPGA
std::cout<<"fpga calStartTimeLength "<<std::endl;
+#endif
#ifdef BUS_ENABLED
@@ -133,11 +144,12 @@ void FPGA::calcStartTimeLength(){
#endif
//round to full cycles!!!
- TMLTime aStartTime = _nextTransaction->getRunnableTime();
+ TMLTime aStartTime = max(_endSchedule,_nextTransaction->getRunnableTime());
+#ifdef DEBUG_FPGA
std::cout<<"start time !!!!!!!!!!"<<_nextTransaction->toShortString()<<"is "<<aStartTime<<std::endl;
+#endif
//or setStartTime(0)???
_nextTransaction->setStartTime(aStartTime);
-
#ifdef BUS_ENABLED
if (_masterNextTransaction==0){
#endif
@@ -184,7 +196,9 @@ std::cout<<"fpga truncateNextTransAt"<<std::endl;
bool FPGA::addTransaction(TMLTransaction* iTransToBeAdded){
+#ifdef DEBUG_FPGA
std::cout<<"fpga addTransaction"<<std::endl;
+#endif
bool aFinish;
std::cout << "*************** LOOKING for master of" << _nextTransaction->toString() << std::endl;
if (_masterNextTransaction==0){
@@ -221,15 +235,30 @@ std::cout<<"fpga addTransaction"<<std::endl;
}
if (aFinish){
- //std::cout<<"I am in finish!!!"<<std::endl;
- _endSchedule=0;
+#ifdef DEBUG_FPGA
+ std::cout<<"I am in finish!!!"<<std::endl;
+#endif
+ //_endSchedule=0;
+ // _maxEndTime=max(_maxEndTime,_nextTransaction->getEndTime());
+#ifdef DEBUG_FPGA
+ std::cout<<"_maxEndTime is "<<_maxEndTime<<std::endl;
+#endif
+
+ if(_reconfigNumber>0)
+ _endSchedule=_maxEndTime+_reconfigNumber*_reconfigTime;
+ else{
+ _endSchedule=0;
+ _maxEndTime=max(_maxEndTime,_nextTransaction->getEndTime());
+ }
+#ifdef DEBUG_FPGA
+ std::cout<<"endschedule is!! "<<_endSchedule<<std::endl;
+#endif
_simulatedTime=max(_simulatedTime,_endSchedule);
_overallTransNo++; //NEW!!!!!!!!
_overallTransSize+=_nextTransaction->getOperationLength(); //NEW!!!!!!!!
//std::cout << "lets crash execute\n";
// std::cout<<_nextTransaction->toString()<<std::endl;
- if(_nextTransaction->getCommand()==0) std::cout<<"d"<<std::endl;
_nextTransaction->getCommand()->execute(); //NEW!!!!
//std::cout << "not crashed\n";
#ifdef TRANSLIST_ENABLED
@@ -249,23 +278,10 @@ std::cout<<"fpga addTransaction"<<std::endl;
void FPGA::schedule(){
std::cout << "fpga:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
- _scheduler->schedule(_endSchedule);
- TMLTransaction* aOldTransaction = _nextTransaction;
+ _reconfigNumber=_scheduler->schedule(_endSchedule);
+ TMLTransaction* aOldTransaction = _nextTransaction;
_nextTransaction=_scheduler->getNextTransaction(_endSchedule);
- /* TaskList::const_iterator iter_task=_taskList.begin();
- std::advance(iter_task,_transNumber);
- if(iter_task!=_taskList.end()){
- _nextTransaction=(*iter_task)->getNextTransaction(_endSchedule);
- if(_nextTransaction!=0 && _nextTransaction->getVirtualLength()==0){
- _nextTransaction=0;
- _transNumber=0;
- }
- else if(++iter_task==_taskList.end())
- _transNumber=0;
- else if(_nextTransaction->getCommand()->getProgress()==_nextTransaction->getLength())
- _transNumber++;
- }
- */
+
if (aOldTransaction!=0 && aOldTransaction!=_nextTransaction){ //NEW
if (_masterNextTransaction!=0) {
_masterNextTransaction->registerTransaction(0);
@@ -441,7 +457,9 @@ void FPGA::drawPieChart(std::ofstream& myfile) const {
_maxEndTime=max(_maxEndTime,_endTime);
}
}
+#ifdef DEBUG_FPGA
std::cout<<"max end time is "<<_maxEndTime<<std::endl;
+#endif
std::map <TMLTask*, double > transPercentage;
for( TransactionList::const_iterator i = _transactList.begin(); i!= _transactList.end(); ++i){
@@ -503,17 +521,21 @@ void FPGA::schedule2HTML(std::ofstream& myfile) {
TMLTime aCurrTime = 0;
unsigned int taskOccurTime = 0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+#ifdef DEBUG_FPGA
std::cout << (*i)-> getCommand()->getTask()->toString() <<std::endl;
std::cout<< _htmlCurrTask->toString()<<std::endl;
+#endif
if( (*i)-> getCommand()->getTask() == _htmlCurrTask ){
if(taskOccurTime==0){
_currTaskNumber++;
taskOccurTime++;
}
+#ifdef DEBUG_FPGA
std::cout<<"in!!"<<_htmlCurrTask->toString()<<std::endl;
+#endif
TMLTransaction* aCurrTrans = *i;
unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
- std::cout<<"blank is "<<aBlanks<<std::endl;
+ //std::cout<<"blank is "<<aBlanks<<std::endl;
if ( aBlanks > 0 ) {
writeHTMLColumn( myfile, aBlanks, "not", "idle time" );
}
@@ -523,7 +545,7 @@ void FPGA::schedule2HTML(std::ofstream& myfile) {
// Issue #4
TMLTask* task = aCurrTrans->getCommand()->getTask();
- std::cout<<"what is this task?"<<task->toString()<<std::endl;
+ // std::cout<<"what is this task?"<<task->toString()<<std::endl;
const std::string cellClass = determineHTMLCellClass( nextCellClassIndex );
writeHTMLColumn( myfile, aLength, cellClass, aCurrTrans->toShortString() );
@@ -549,10 +571,14 @@ void FPGA::schedule2HTML(std::ofstream& myfile) {
}
myfile << "</tr>" << std::endl << "</table>" << std::endl;
+#ifdef DEBUG_FPGA
std::cout<<"_taskNumer is ------------------------------------"<<_taskNumber<<std::endl;
std::cout<<"curr task number is ------------------------"<<_currTaskNumber<<std::endl;
+#endif
if(_currTaskNumber == _taskNumber){
+#ifdef DEBUG_FPGA
std::cout<<" i am showing the name of tasks!!!----------------------------------------------------------------------------------!"<<std::endl;
+#endif
myfile << "<table>" << std::endl << "<tr>" << std::endl;
for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
TMLTask* task = (*taskColIt).first;
@@ -565,5 +591,7 @@ void FPGA::schedule2HTML(std::ofstream& myfile) {
}
+#ifdef DEBUG_FPGA
std::cout<<"end in!!!"<<std::endl;
+#endif
}
diff --git a/simulators/c++2/src_simulator/arch/FPGA.h b/simulators/c++2/src_simulator/arch/FPGA.h
index 71cf7c29bea69f37fa9539e1bd6bf1c563b26b4b..28a92a4b9c825a12cbcec5e29fa4f730db9a7f5e 100644
--- a/simulators/c++2/src_simulator/arch/FPGA.h
+++ b/simulators/c++2/src_simulator/arch/FPGA.h
@@ -136,6 +136,7 @@ public:
inline void setHtmlCurrTask(TMLTask *t) { _htmlCurrTask=t;}
inline void setStartFlagHTML(bool s) {_startFlagHTML=s;}
inline void setEndFlagHTML(bool s) {_endFlagHTML=s;}
+ //inline void setMaxEndTime(TMLTime t) {_maxEndTime=t;}
double averageLoad (TMLTask* currTask) const;
void drawPieChart(std::ofstream& myfile) const;
void showPieChart(std::ofstream& myfile) const;
@@ -191,10 +192,13 @@ protected:
unsigned int _taskNumber;
//current number of tasks executed on FPGA
unsigned int _currTaskNumber;
+ unsigned int _reconfigNumber;
+ TMLTime _maxEndTime;
unsigned int nextCellClassIndex;
std::map<TMLTask*, std::string> taskCellClasses;
///State variable for the VCD output
vcdFPGAVisState _vcdOutputState;
+
};
#endif
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index 4028e122f6ba5486a59d096e248af328fc89befc..1a0a2e1422bd4e482bf79a107a2c51f11027d7fa 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -110,18 +110,20 @@ void MultiCoreCPU::initCore(){
TMLTime MultiCoreCPU::getMinEndSchedule(){
TMLTime minTime=multiCore[0];
for( TMLTime i = 0; i < multiCore.size(); i++){
- //std::cout<<"core number is: "<<i<<" end schedule is "<<multiCore[i]<<std::endl;
+ // std::cout<<"core number is: "<<i<<" end schedule is "<<multiCore[i]<<std::endl;
if( minTime >= multiCore[i]){
minTime=multiCore[i];
coreNumber=i;
}
}
- //std::cout<<"in getMinEndSchedule core number is "<<coreNumber<<std::endl;
+ // std::cout<<"in getMinEndSchedule core number is "<<coreNumber<<std::endl;
return minTime;
}
TMLTransaction* MultiCoreCPU::getNextTransaction(){
+#ifdef DEBUG_CPU
std::cout<<"getNextTransaction"<<_name<<std::endl;
+#endif
#ifdef BUS_ENABLED
if (_masterNextTransaction == 0 || _nextTransaction == 0){
return _nextTransaction;
@@ -149,12 +151,12 @@ std::cout<<"getNextTransaction"<<_name<<std::endl;
}
void MultiCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
- //std::cout<<"calcStartTimeLength"<<_name<<std::endl;
#ifdef DEBUG_CPU
+std::cout<<"calcStartTimeLength"<<_name<<std::endl;
std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
#endif
#ifdef BUS_ENABLED
- std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
+std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
//std::cout << " " << std::endl;
TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
//std::cout << "after get channel " << std::endl;
@@ -283,7 +285,9 @@ TMLTime MultiCoreCPU::truncateNextTransAt(TMLTime iTime){
}
bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
+#ifdef DEBUG_CPU
std::cout<<"addTransaction"<<_name<<std::endl;
+#endif
bool aFinish;
//TMLTransaction* aTransCopy=0;
if (_masterNextTransaction==0){
@@ -339,22 +343,21 @@ std::cout << "CPU:calcSTL: addtransaction of CPU " << _name << ": " << _nextTran
////test///
// unsigned int iCoreNumber=getCoreNumber();
static unsigned int time=0;
- std::cout<<"multicore number "<<coreNumber<<" end schedule "<<_endSchedule<<std::endl;
+ // std::cout<<"multicore number "<<coreNumber<<" end schedule "<<_endSchedule<<std::endl;
multiCore[coreNumber]=_endSchedule;
// std::cout<<"cycle time is "<<_cycleTime<<std::endl;
if (time < amountOfCore -1){
_endSchedule=0;
_nextTransaction->setTransactCoreNumber(coreNumber);
++coreNumber;
- std::cout<<"haha1: "<<coreNumber<<std::endl;
+
}else {
_nextTransaction->setTransactCoreNumber(coreNumber);
_endSchedule=getMinEndSchedule();
- std::cout<<"haha2: "<<coreNumber<<std::endl;
+
}
time++;
- std::cout <<"test transaction core number !!!! "<<_nextTransaction->getTransactCoreNumber()<<std::endl;
- std::cout << "set end schedule CPU: " << _endSchedule << "\n";
+
_simulatedTime=max(_simulatedTime,_endSchedule);
_overallTransNo++; //NEW!!!!!!!!
_overallTransSize+=_nextTransaction->getOperationLength(); //NEW!!!!!!!!
@@ -398,7 +401,7 @@ void MultiCoreCPU::schedule(){
//std::cout << "5\n";
if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
//std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
- else std::cout<<"no need calcStartTimeLength"<<std::endl;
+
std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
@@ -541,21 +544,20 @@ void MultiCoreCPU::latencies2XML(std::ostringstream& glob, unsigned int id1, uns
void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//static bool _end=false;
- std::cout<<"getNextSignalChangemulticore!!!---------"<<std::endl;
+
for( TransactionList::iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
- std::cout<<"transaction core number is "<< (*i)->getTransactCoreNumber()<<std::endl;
- std::cout<<"cpu core number "<< oSigData->_coreNumberVcd<<std::endl;
+
if( (*i)->getTransactCoreNumber() == oSigData->_coreNumberVcd){
- std::cout<<"bingo!!"<<(*i)->toShortString()<<std::endl;
- //if(_transactList.end()==0) std::cout<<"what???"<<std::endl;
+
+
//std::cout<<(*_transactList.end())->toShortString()<<std::endl;
if (iInit){
_posTrasactListVCD= i;
_previousTransEndTime=0;
(*i)->setTransVcdOutPutState(END_IDLE_TRANS);
- std::cout<<"init"<<std::endl;
+ //std::cout<<"init"<<std::endl;
if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()!=0){
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
//oSigChange=outp.str();
@@ -580,7 +582,7 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
switch (aCurrTrans->getTransVcdOutPutState()){
case END_TASK_TRANS:
- std::cout<<"END_TASK_CPU"<<std::endl;
+ //std::cout<<"END_TASK_CPU"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
@@ -594,16 +596,12 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
// std::cout<<"4444"<<std::endl;
if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
//outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
- std::cout<<"!!!~~~"<<(*_posTrasactListVCD)->toShortString()<<std::endl;
(*_posTrasactListVCD)->setTransVcdOutPutState(END_PENALTY_TRANS);
- std::cout<<"almost!!!"<<std::endl;
new (oSigData) SignalChangeData(END_PENALTY_TRANS, _previousTransEndTime, this);
}else{
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
aCurrTrans->setTransVcdOutPutState(END_IDLE_TRANS);
//if (_posTrasactListVCD == _transactList.end()) oNoMoreTrans=true;
- std::cout<<"what is previous time "<<_previousTransEndTime<<std::endl;
- std::cout<<"and this??"<<oSigData->_time<<std::endl;
// if(oSigData->_time != _previousTransEndTime) new (oSigData) SignalChangeData(END_PENALTY_TRANS, _previousTransEndTime, this);
new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
//_posTrasactListVCD = _transactList.end();
@@ -617,16 +615,15 @@ void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
break;
case END_PENALTY_TRANS:
- std::cout<<"END_PENALTY_CPU"<<std::endl;
+ // std::cout<<"END_PENALTY_CPU"<<std::endl;
//outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
//oSigChange=outp.str();
aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
//return aCurrTrans->getStartTimeOperation();
- std::cout<<"time in penalty is "<< aCurrTrans->getStartTimeOperation()<<std::endl;
new (oSigData) SignalChangeData(END_TASK_TRANS, aCurrTrans->getStartTimeOperation(), this);
break;
case END_IDLE_TRANS:
- std::cout<<"END_IDLE_CPU"<<std::endl;
+ // std::cout<<"END_IDLE_CPU"<<std::endl;
if (aCurrTrans->getPenalties()==0){
//outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
diff --git a/simulators/c++2/src_simulator/arch/OrderScheduler.cpp b/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
index ef5ca41d56aceb64c40132fbd902e8c66c997e22..363386ba5c2f75162bbd13773ed42e2b694fb8d0 100644
--- a/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
+++ b/simulators/c++2/src_simulator/arch/OrderScheduler.cpp
@@ -47,12 +47,12 @@ OrderScheduler::OrderScheduler(const std::string& iName, Priority iPrio, Workloa
}
TMLTime OrderScheduler::schedule(TMLTime iEndSchedule){
+ std::cout<<"order scheduler "<<std::endl;
TaskList::iterator i;
TMLTransaction *aMarkerPast=0, *aMarkerFuture=0,*aTempTrans;
TMLTime aTransTimeFuture=-1,aRunnableTime;
WorkloadSource *aSourcePast=0, *aSourceFuture=0; //NEW
for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
- (*i)->schedule(iEndSchedule);
aTempTrans=(*i)->getNextTransaction(iEndSchedule);
if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0){
aRunnableTime=aTempTrans->getRunnableTime();
@@ -81,6 +81,7 @@ TMLTime OrderScheduler::schedule(TMLTime iEndSchedule){
_nextTransaction=aMarkerPast;
_lastSource=aSourcePast; //NEW
}
+ std::cout<<"end order scheduler"<<std::endl;
return 0;
}
diff --git a/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp b/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..bd01cb5fadbc0ecd56881689d328f7ab58191ab8
--- /dev/null
+++ b/simulators/c++2/src_simulator/arch/ReconfigScheduler.cpp
@@ -0,0 +1,121 @@
+/*Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Niu Siyuan,
+Ludovic Apvrille, Renaud Pacalet
+ *
+ * ludovic.apvrille AT telecom-paristech.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ *
+ */
+#include<ReconfigScheduler.h>
+#include <TMLTransaction.h>
+#include <FPGA.h>
+
+ReconfigScheduler::ReconfigScheduler(const std::string& iName, Priority iPrio, const std::string iTaskOrder): WorkloadSource(iPrio), _name(iName), _taskOrder(iTaskOrder), _nextTransaction(0), _tempWorkloadList(0){}
+
+ReconfigScheduler::ReconfigScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources, const std::string iTaskOrder): WorkloadSource(iPrio, aSourceArray, iNbOfSources), _name(iName), _taskOrder(iTaskOrder), _nextTransaction(0), _lastSource(0), _tempWorkloadList(0) {
+}
+
+TMLTime ReconfigScheduler::schedule(TMLTime iEndSchedule){
+ std::cout<<"reconfig scheduler"<<std::endl;
+ TaskList::iterator i;
+ TMLTransaction *aMarkerPast=0, *aMarkerFuture=0,*aTempTrans;
+ TMLTask* aTempTask;
+ TMLTime aTransTimeFuture=-1,aRunnableTime;
+ WorkloadSource *aSourcePast=0, *aSourceFuture=0; //NEW
+ static unsigned int taskStart=0;
+ static unsigned int reconfigNumber=0;
+
+ if( _tempWorkloadList.empty()){
+ for(WorkloadList::iterator i=_workloadList.begin(); i != _workloadList.end(); ++i){
+ std::cout<<"temp for"<<std::endl;
+ if(taskStart>=_taskOrder.length()){
+ break;
+ }
+ aTempTrans=(*i)->getNextTransaction(iEndSchedule);
+ if(aTempTrans==0) continue;
+ aTempTask=aTempTrans->getCommand()->getTask();
+ std::string taskName=aTempTask->toString();
+ unsigned int indexTask=taskName.find_last_of("_");
+ unsigned int taskNameLength=taskName.length()-indexTask;
+ std::cout<<"taskName "<<taskName.substr(indexTask+1,taskNameLength)<<" task order "<<_taskOrder.substr(taskStart,taskNameLength-1)<<std::endl;
+ if(taskName.substr(indexTask+1,taskNameLength) == _taskOrder.substr(taskStart,taskNameLength-1)){
+ _tempWorkloadList.push_back(aTempTask);
+ std::cout<<"add task"<<std::endl;
+ taskStart+=taskNameLength;
+
+ }
+ }
+ }
+ if(_tempWorkloadList.empty()){
+ _nextTransaction=0;
+ return reconfigNumber ;
+ }
+
+ for(WorkloadList::iterator i=_tempWorkloadList.begin(); i != _tempWorkloadList.end(); ++i){
+ std::cout<<"schedule for"<<std::endl;
+ aTempTrans=(*i)->getNextTransaction(iEndSchedule);
+ if(aTempTrans==0) std::cout<<"temp trans is 0"<<std::endl;
+ else std::cout<<"temp trans is "<<aTempTrans->toShortString()<<std::endl;
+ if (aTempTrans!=0 && aTempTrans->getVirtualLength()!=0){
+ std::cout<<"erase"<<std::endl;
+ _nextTransaction=aTempTrans;
+ // _maxTransEndTime=max(_maxTransEndTime,_nextTransaction->getEndTime());
+ _tempWorkloadList.erase(i);
+ if(_taskOrder[taskStart-1]==';' && _tempWorkloadList.empty()){
+ // std::cout<<"plus 1 for ; "<<std::endl;
+ ++reconfigNumber;
+ //_endSchedule=maxEndTime;
+ //_maxEndTime=_maxTransEndTime;
+ }
+ break;
+ }
+
+ }
+
+
+ std::cout<<"end order scheduler"<<std::endl;
+ return reconfigNumber;
+
+
+
+}
+
+ReconfigScheduler::~ReconfigScheduler(){
+ std::cout << _name << ": Scheduler deleted\n";
+}
+
+void ReconfigScheduler::reset(){
+ WorkloadSource::reset();
+ _nextTransaction=0;
+}
diff --git a/simulators/c++2/src_simulator/arch/ReconfigScheduler.h b/simulators/c++2/src_simulator/arch/ReconfigScheduler.h
new file mode 100644
index 0000000000000000000000000000000000000000..bcca94bb7ee9b1b12a26d0c386afb01f89a092a4
--- /dev/null
+++ b/simulators/c++2/src_simulator/arch/ReconfigScheduler.h
@@ -0,0 +1,83 @@
+/*Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Niu Siyuan,
+Ludovic Apvrille, Renaud Pacalet
+ *
+ * ludovic.apvrille AT telecom-paristech.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ *
+ */
+#ifndef ReconfigSchedulerH
+#define ReconfigSchedulerH
+#include <WorkloadSource.h>
+
+class TMLTransaction;
+class FPGA;
+
+///Fixed priority based scheduler
+class ReconfigScheduler: public WorkloadSource{
+public:
+ ///Constructor
+ /**
+ \param iName Name of the scheduler
+ \param iPrio Priority of the scheduler
+ */
+ ReconfigScheduler(const std::string& iName, Priority iPrio, const std::string iTaskOrder);
+ ///Constructor
+ /**
+ \param iName Name of the scheduler
+ \param iPrio Priority of the scheduler
+ \param aSourceArray Array of pointers to workload ressources from which transactions may be received
+ \param iNbOfSources Length of the array
+ */
+ ReconfigScheduler(const std::string& iName, Priority iPrio, WorkloadSource** aSourceArray, unsigned int iNbOfSources, const std::string iTaskOrder);
+ ~ReconfigScheduler();
+ TMLTime schedule(TMLTime iEndSchedule);
+ inline TMLTransaction* getNextTransaction(TMLTime iEndSchedule) const {return _nextTransaction;}
+ inline std::string toString() const {return _name;}
+ void reset();
+ //void transWasScheduled(SchedulableDevice* iDevice);
+protected:
+ ///Name of the scheduler
+ std::string _name;
+ //task order decided by users
+ std::string _taskOrder;
+ ///Next transaction to be executed
+ TMLTransaction* _nextTransaction;
+ ///Last workload source to which ressource access was granted
+ WorkloadSource* _lastSource;
+ WorkloadList _tempWorkloadList;
+
+
+};
+#endif
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index 346ac1b21c0a9b2e4f7b4e6a10ebf24bad5c318a..d528b73267a381e33a9940b623bef4e6dd2938a9 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -197,7 +197,7 @@ double SchedulableDevice::averageLoad() const{
TMLTime _endTime= (*i)->getEndTime();
_maxEndTime=max(_maxEndTime,_endTime);
}
- //std::cout<<"max end time is "<<_maxEndTime<<std::endl;
+ std::cout<<"max end time is "<<_maxEndTime<<std::endl;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
_averageLoad += (*i)->getEndTime() - (*i)->getStartTime();
@@ -264,9 +264,9 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
TMLTime aCurrTime = 0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
- //std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
- //std::cout<<"time : "<<_cycleTime<<std::endl;
- //std::cout << "CPU:calcSTL: html of CPU " << _name << ": " << (*i)->toString() << std::endl;
+ std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
+ std::cout<<"time : "<<_cycleTime<<std::endl;
+ std::cout << "CPU:calcSTL: html of CPU " << _name << ": " << (*i)->toString() << std::endl;
//if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
TMLTransaction* aCurrTrans = *i;
unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
diff --git a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
index 9eb8cd517eddf5cd4e3d1e009902f9671cb8f7af..21a9873bc62c2473aee497c2b30a37732dc5ce78 100644
--- a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
@@ -88,7 +88,10 @@ SingleCoreCPU::~SingleCoreCPU(){
}
TMLTransaction* SingleCoreCPU::getNextTransaction(){
- //std::cout<<"getNextTransaction!!!!!"<<std::endl;
+#ifdef DEBUG_CPU
+ std::cout<<"getNextTransaction!!!!!"<<std::endl;
+#endif
+
#ifdef BUS_ENABLED
if (_masterNextTransaction==0 || _nextTransaction==0){
return _nextTransaction;
@@ -120,23 +123,23 @@ void SingleCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
#endif
#ifdef BUS_ENABLED
- //std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
- //std::cout << "get channel " << std::endl;
+ std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
+ std::cout << "get channel " << std::endl;
TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
- //std::cout << "after get channel " << std::endl;
+ std::cout << "after get channel " << std::endl;
if (aChannel==0) {
//std::cout << "no channel " << std::endl;
_masterNextTransaction=0;
} else {
- //std::cout << "get bus " << std::endl;
+ std::cout << "get bus " << std::endl;
_masterNextTransaction= getMasterForBus(aChannel->getFirstMaster(_nextTransaction));
- //std::cout << "after get first bus " << std::endl;
+ std::cout << "after get first bus " << std::endl;
if (_masterNextTransaction!=0){
- //std::cout << "before register transaction at bus " << _masterNextTransaction->toString() << std::endl;
+ std::cout << "before register transaction at bus " << _masterNextTransaction->toString() << std::endl;
_masterNextTransaction->registerTransaction(_nextTransaction);
- //std::cout << "Transaction registered at bus " << _masterNextTransaction->toString() << std::endl;
+ std::cout << "Transaction registered at bus " << _masterNextTransaction->toString() << std::endl;
} else {
- //std::cout << " NO MASTER NEXT TRANSACTION " << std::endl;
+ std::cout << " NO MASTER NEXT TRANSACTION " << std::endl;
}
}
#endif
@@ -144,7 +147,7 @@ void SingleCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
TMLTime aStartTime = max(_endSchedule,_nextTransaction->getRunnableTime());
TMLTime aReminder = aStartTime % _timePerCycle;
if (aReminder!=0) aStartTime+=_timePerCycle - aReminder;
- //std::cout << "CPU: set start time in CPU=" << aStartTime << " Reminder=" << aReminder <<"\n";
+ std::cout << "CPU: set start time in CPU=" << aStartTime << " Reminder=" << aReminder <<"\n";
_nextTransaction->setStartTime(aStartTime);
@@ -174,7 +177,9 @@ void SingleCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
}
void SingleCoreCPU::truncateAndAddNextTransAt(TMLTime iTime){
- //std::cout<<"cpu truncatenextTransct"<<std::endl;
+#ifdef DEBUG_CPU
+ std::cout<<"cpu truncatenextTransct"<<std::endl;
+#endif
//std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
//return truncateNextTransAt(iTime);
//not a problem if scheduling does not take place at time when transaction is actually truncated, tested
@@ -234,10 +239,13 @@ TMLTime SingleCoreCPU::truncateNextTransAt(TMLTime iTime){
}
bool SingleCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
- //std::cout<<"addTransaction"<<std::endl;
+#ifdef DEBUG_CPU
+std::cout<<"addTransaction"<<std::endl;
+#endif
+
bool aFinish;
//TMLTransaction* aTransCopy=0;
- //std::cout << "*************** LOOKING for master of" << _nextTransaction->toString() << std::endl;
+ std::cout << "*************** LOOKING for master of" << _nextTransaction->toString() << std::endl;
if (_masterNextTransaction==0){
aFinish=true;
#ifdef DEBUG_CPU
@@ -251,31 +259,31 @@ bool SingleCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
//std::cout << "*************** LOOKING for master of" << _nextTransaction->toString() << std::endl;
BusMaster* aFollowingMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
if (aFollowingMaster==0){
- //std::cout << "1\n";
+ std::cout << "1\n";
aFinish=true;
//aTransCopy = new TMLTransaction(*_nextTransaction);
//_nextTransaction = aTransCopy;
BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
- //std::cout << "2\n";
+ std::cout << "2\n";
Slave* aTempSlave= _nextTransaction->getChannel()->getNextSlave(_nextTransaction);
- //std::cout << "3\n";
+ std::cout << "3\n";
aTempMaster->addBusContention(_nextTransaction->getStartTime()-max(_endSchedule,_nextTransaction->getRunnableTime()));
while (aTempMaster!=0){
- //std::cout << "3a\n";
+ std::cout << "3a\n";
aTempMaster->addTransaction(_nextTransaction);
- //std::cout << "3b\n";
+ std::cout << "3b\n";
//if (aTempSlave!=0) aTempSlave->addTransaction(_nextTransaction);
if (aTempSlave!=0) aTempSlave->addTransaction(_nextTransaction); //NEW
- //std::cout << "4\n";
+ std::cout << "4\n";
aTempMaster =_nextTransaction->getChannel()->getNextMaster(_nextTransaction);
- //std::cout << "5\n";
+ std::cout << "5\n";
aTempSlave= _nextTransaction->getChannel()->getNextSlave(_nextTransaction);
}
- //std::cout << "6\n";
+ std::cout << "6\n";
} else {
- //std::cout << _name << " bus transaction next round" << std::endl;
+ std::cout << _name << " bus transaction next round" << std::endl;
_masterNextTransaction=aFollowingMaster;
- //std::cout << "7\n";
+ std::cout << "7\n";
_masterNextTransaction->registerTransaction(_nextTransaction);
aFinish=false;
}
@@ -311,7 +319,7 @@ bool SingleCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
void SingleCoreCPU::schedule(){
//std::cout <<"Hello\n";
- //std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+ std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
//_schedulingNeeded=false; 05/05/11
//std::cout << "1\n";
@@ -334,7 +342,7 @@ void SingleCoreCPU::schedule(){
}
//std::cout << "5\n";
if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
- //std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
+ std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
//std::string SingleCoreCPU::toString() const{
@@ -473,15 +481,15 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
}
if (_posTrasactListVCD == _transactList.end()){
- std::cout<<"end trans"<<std::endl;
+ //std::cout<<"end trans"<<std::endl;
new (oSigData) SignalChangeData(END_IDLE_CPU, _previousTransEndTime, this);
}
else{
TMLTransaction* aCurrTrans=*_posTrasactListVCD;
- std::cout<<"current trans is "<<aCurrTrans->toShortString()<<std::endl;
+ // std::cout<<"current trans is "<<aCurrTrans->toShortString()<<std::endl;
switch (_vcdOutputState){
case END_TASK_CPU:
- std::cout<<"END_TASK_CPU"<<std::endl;
+ //std::cout<<"END_TASK_CPU"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
@@ -489,7 +497,6 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
//outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
_vcdOutputState=END_PENALTY_CPU;
- std::cout<<"why???"<<std::endl;
new (oSigData) SignalChangeData(END_PENALTY_CPU, _previousTransEndTime, this);
}else{
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
@@ -501,7 +508,7 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return _previousTransEndTime;
break;
case END_PENALTY_CPU:
- std::cout<<"END_PENALTY_CPU"<<std::endl;
+ //std::cout<<"END_PENALTY_CPU"<<std::endl;
//outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
//oSigChange=outp.str();
_vcdOutputState=END_TASK_CPU;
@@ -509,7 +516,7 @@ void SingleCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
new (oSigData) SignalChangeData(END_TASK_CPU, aCurrTrans->getStartTimeOperation(), this);
break;
case END_IDLE_CPU:
- std::cout<<"END_IDLE_CPU"<<std::endl;
+ //std::cout<<"END_IDLE_CPU"<<std::endl;
if (aCurrTrans->getPenalties()==0){
//outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
_vcdOutputState=END_TASK_CPU;
@@ -542,7 +549,7 @@ void SingleCoreCPU::streamBenchmarks(std::ostream& s) const{
s << TAG_CPUo << " id=\"" << _ID << "\" name=\"" << _name << "\">" << std::endl;
if (_simulatedTime!=0) s << TAG_UTILo << (static_cast<float>(_busyCycles)/static_cast<float>(_simulatedTime)) << TAG_UTILc;
s << TAG_ENERGYo << ( (_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle) << TAG_ENERGYc;
- //std::cout<< "power consumption "<< ((_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle)<< std::endl;
+ std::cout<< "power consumption "<< ((_simulatedTime/_timePerCycle)*_static_consumPerCycle) + ((_busyCycles/_timePerCycle)*_dynamic_consumPerCycle)<< std::endl;
for(BusMasterList::const_iterator i=_busMasterList.begin(); i != _busMasterList.end(); ++i) (*i)->streamBenchmarks(s);
s << TAG_CPUc;
diff --git a/simulators/c++2/src_simulator/arch/WorkloadSource.h b/simulators/c++2/src_simulator/arch/WorkloadSource.h
index 185a914f4d1e68fc6c8df648a99b5b51a8746801..9857e43c85851472f3c40a0184648a0251b73d31 100644
--- a/simulators/c++2/src_simulator/arch/WorkloadSource.h
+++ b/simulators/c++2/src_simulator/arch/WorkloadSource.h
@@ -64,7 +64,7 @@ public:
WorkloadSource(Priority iPriority, WorkloadSource** aSourceArray, unsigned int iNbOfSources): _priority(iPriority), _srcArraySpecified(true){
for (unsigned int i=0;i<iNbOfSources;i++){
addWorkloadSource(aSourceArray[i]);
- //std::cout << "Workload source added " << aSourceArray[i]->toString() << "\n";
+ std::cout << "Workload source added " << aSourceArray[i]->toString() << "\n";
}
delete[] aSourceArray;
}
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index 201ddc0e1edd930c9324685036ab5e530d12fa97..8ac1118f63dd61f3721bdb403545de279c498d34 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -348,7 +348,9 @@ void Simulator::latencies2XML(std::ostringstream& glob, int id1, int id2) {
}
void Simulator::schedule2HTML(std::string& iTraceFileName) const {
+#ifdef DEBUG_HTML
std::cout<<"schedule2HTML--------------------------------------******************"<<std::endl;
+#endif
struct timeval aBegin,aEnd;
time_t aRawtime;
struct tm * aTimeinfo;
@@ -370,12 +372,11 @@ std::cout<<"schedule2HTML--------------------------------------*****************
myfile << SCHED_HTML_DOC; // <!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Strict//EN\"\n\"http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd\">\n
myfile << SCHED_HTML_BEG_HTML; // <html xmlns=\"http://www.w3.org/1999/xhtml\" xml:lang=\"en\" lang=\"en\">\n
myfile << SCHED_HTML_BEG_HEAD; // <head>\n
-
const std::string::size_type findSlash = iTraceFileName.find_last_of( "/" );
unsigned int indexSlash;
if ( findSlash == std::string::npos ) {
- indexSlash = 0;
+ indexSlash = -1;
//myfile<<"indexSlash=0\n";
}
else {
@@ -397,7 +398,7 @@ std::cout<<"schedule2HTML--------------------------------------*****************
cssfile.close();
myfile << SCHED_HTML_CSS_BEG_LINK;
- myfile << cssFullFileName;
+ myfile << cssFileName;
myfile << SCHED_HTML_CSS_END_LINK;
}
else {
@@ -459,8 +460,10 @@ std::cout<<"schedule2HTML--------------------------------------*****************
(*j)->setStartFlagHTML(true);
for(TaskList::const_iterator i = (*j)->getTaskList().begin(); i != (*j)->getTaskList().end(); ++i){
(*j)->setHtmlCurrTask(*i);
- //std::cout<<"begin fpga html "<<(*j)->toShortString()<<std::endl;
- //std::cout<<"task is !!!!!"<<(*i)->toString()<<std::endl;
+#ifdef DEBUG_HTML
+ std::cout<<"begin fpga html "<<(*j)->toShortString()<<std::endl;
+ std::cout<<"task is !!!!!"<<(*i)->toString()<<std::endl;
+#endif
(*j)->schedule2HTML(myfile);
(*j)->setStartFlagHTML(false);
}
@@ -492,7 +495,9 @@ std::cout<<"schedule2HTML--------------------------------------*****************
std::cout << "The HTML output took " << getTimeDiff(aBegin,aEnd) << "usec. File: " << iTraceFileName << std::endl;
}
void Simulator::schedule2VCD(std::string& iTraceFileName) const{
+#ifdef DEBUG_VCD
std::cout<<"schedule2VCD~~~~~~~~~~~~"<<std::endl;
+#endif
time_t aRawtime;
struct tm * aTimeinfo;
struct timeval aBegin,aEnd;
@@ -538,13 +543,14 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
}
}
else if((*i)->toShortString().substr(0,4) == "fpga"){
- std::cout<<"444"<<std::endl;
for(TaskList::const_iterator j = _simComp->getTaskList().begin(); j != _simComp->getTaskList().end(); j++){
aTopElement = new SignalChangeData();
aTopElement->_taskFPGA=(*j);
(*i)->getNextSignalChange(true, aTopElement);
if(aTopElement->_device){
+#ifdef DEBUG_VCD
std::cout<<"name of fpga is : "<< (*i)->toShortString() << "_" << (*j)->toString() << std::endl;
+#endif
myfile << "$var wire 1 " << (*i)->toShortString() << "_" << (*j)->toString() << " " << (*i)->toString() << "_" << (*j)->toString() << " $end\n";
aQueue.push(aTopElement);
}
@@ -569,14 +575,14 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
myfile << "$upscope $end\n$enddefinitions $end\n\n";
while (!aQueue.empty()){
- std::cout<<"this is queue"<<std::endl;
+ // std::cout<<"this is queue"<<std::endl;
aTopElement=aQueue.top();
if( aTopElement->_device->toShortString().substr(0,3) == "cpu")
- std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_core" << aTopElement->_coreNumberVcd<<std::endl;
+ std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_core" << aTopElement->_coreNumberVcd<<std::endl;
else if( aTopElement->_device->toShortString().substr(0,4) == "fpga")
std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<< "_" << aTopElement->_taskFPGA->toString()<<std::endl;
else
- std::cout<<"the member of queue is "<<aTopElement->_device->toShortString() <<std::endl;
+ std::cout<<"the member of queue is "<<aTopElement->_device->toShortString() <<std::endl;
while (aNextClockEvent < aTopElement->_time){
@@ -608,15 +614,17 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
aQueue.pop();
TMLTime aTime = aTopElement->_time;
aTopElement->_device->getNextSignalChange(false, aTopElement);
+#ifdef DEBUG_VCD
std::cout<<"aTime is "<<aTime<<std::endl;
std::cout<<"top element time is "<<aTopElement->_time<<std::endl;
+#endif
if (aTopElement->_time == aTime){
delete aTopElement;
- std::cout<<"delete"<<std::endl;
+ // std::cout<<"delete"<<std::endl;
}
else{
aQueue.push(aTopElement);
- std::cout<<"no delete"<<std::endl;
+ //std::cout<<"no delete"<<std::endl;
}
}
@@ -674,17 +682,16 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#endif
_simComp->setStopFlag(false,"");
for(TaskList::const_iterator i=_simComp->getTaskList().begin(); i!=_simComp->getTaskList().end();i++){
- //std::cout << "task preparation:" << (*i)->toString() << std::endl;
- //if ((*i)->getCurrCommand()!=0) std::cout<<(*i)->getCurrCommand()->toString() << std::endl;
if ((*i)->getCurrCommand()!=0) (*i)->getCurrCommand()->prepare(true);
- //std::cout << "task preparation done:" << (*i)->toString() << std::endl;
}
#ifdef EBRDD_ENABLED
for(EBRDDList::const_iterator i=_simComp->getEBRDDIterator(false); i!=_simComp->getEBRDDIterator(true);i++){
if ((*i)->getCurrCommand()!=0) (*i)->getCurrCommand()->prepare();
}
#endif
- //std::cout<<"simulate"<<std::endl;
+#ifdef DEBUG_SIMULATE
+ std::cout<<"simulate"<<std::endl;
+#endif
for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
for_each(_simComp->getFPGAList().begin(), _simComp->getFPGAList().end(),std::mem_fun(&FPGA::schedule));
@@ -695,16 +702,21 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
_wasReset=false;
#endif
while ( transLET!=0 && !_simComp->getStopFlag()){
-
- //std::cout<<"come in cpu"<<std::endl;
+#ifdef DEBUG_SIMULATE
+ std::cout<<"come in cpu"<<std::endl;
+#endif
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: scheduling decision: " << transLET->toString() << std::endl;
#endif
commandLET=transLET->getCommand();
- //std::cout<<"device is "<<deviceLET->getName()<<std::endl;
+#ifdef DEBUG_SIMULATE
+ std::cout<<"device is "<<deviceLET->getName()<<std::endl;
+#endif
bool x = deviceLET->addTransaction(0);
- //std::cout<<"in simulator end addTransactin"<<std::endl;
+#ifdef DEBUG_SIMULATE
+ std::cout<<"in simulator end addTransactin"<<std::endl;
+#endif
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: AFTER add trans: " << x << std::endl;
#endif
@@ -722,7 +734,9 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
depFPGA=depTask->getFPGA();
if(depCPU){
- //std::cout<<"lets start cpu"<<std::endl;
+#ifdef DEBUG_SIMULATE
+ std::cout<<"lets start cpu"<<std::endl;
+#endif
if (depCPU!=deviceLET){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: Tasks running on different CPUs" << std::endl;
@@ -766,7 +780,9 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
}
}
else{
+#ifdef DEBUG_SIMULATE
std::cout<<"lets start fpga"<<std::endl;
+#endif
if (depFPGA!=deviceLET){
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: Tasks running on different FPGAs" << std::endl;
@@ -820,7 +836,9 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
#endif
}
oLastTrans=transLET;
- //std::cout<<"task is !!!!!"<<oLastTrans->toString()<<std::endl;
+#ifdef DEBUG_SIMULATE
+ std::cout<<"task is !!!!!"<<oLastTrans->toString()<<std::endl;
+#endif
transLET=getTransLowestEndTime(deviceLET);
}