From c634bab022f99b1a6181a4a0bbdda9d81f1aa01b Mon Sep 17 00:00:00 2001
From: niusiyuan <siyuan.niu@telecom-paristech.fr>
Date: Thu, 4 Apr 2019 16:31:26 +0200
Subject: [PATCH] simulation_test merge
---
.../c++2/src_simulator/TMLTransaction.cpp | 2 +-
.../c++2/src_simulator/TMLTransaction.h | 15 ++
.../c++2/src_simulator/app/TMLChannel.cpp | 6 +-
.../c++2/src_simulator/app/TMLbrbwChannel.cpp | 1 +
simulators/c++2/src_simulator/arch/Bus.cpp | 9 +-
simulators/c++2/src_simulator/arch/CPU.h | 108 +++++++-
.../c++2/src_simulator/arch/MultiCoreCPU.cpp | 247 ++++++++++++------
.../c++2/src_simulator/arch/MultiCoreCPU.h | 18 +-
.../src_simulator/arch/SchedulableDevice.cpp | 11 +-
.../src_simulator/arch/SchedulableDevice.h | 5 +-
.../c++2/src_simulator/arch/SingleCoreCPU.cpp | 2 +-
.../c++2/src_simulator/sim/Simulator.cpp | 163 +++++++++---
.../DiploSimulatorCodeGenerator.java | 46 ++--
.../tomappingsystemc2/TML2MappingSystemC.java | 32 ++-
14 files changed, 517 insertions(+), 148 deletions(-)
diff --git a/simulators/c++2/src_simulator/TMLTransaction.cpp b/simulators/c++2/src_simulator/TMLTransaction.cpp
index 14a1066796..6b46b17489 100755
--- a/simulators/c++2/src_simulator/TMLTransaction.cpp
+++ b/simulators/c++2/src_simulator/TMLTransaction.cpp
@@ -46,7 +46,7 @@
MemPoolNoDel<TMLTransaction> TMLTransaction::memPool(BLOCK_SIZE_TRANS);
-TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),
+TMLTransaction::TMLTransaction():_runnableTime(0), _startTime(0), _length(0), _virtualLength(0), _command(0),_transactCoreNumber(0),_transVcdOutputState(END_IDLE_TRANS),
#ifdef PENALTIES_ENABLED
_idlePenalty(0), _taskSwitchingPenalty(0), //, _branchingPenalty(0),
#endif
diff --git a/simulators/c++2/src_simulator/TMLTransaction.h b/simulators/c++2/src_simulator/TMLTransaction.h
index bb82e10398..0dbe766c72 100644
--- a/simulators/c++2/src_simulator/TMLTransaction.h
+++ b/simulators/c++2/src_simulator/TMLTransaction.h
@@ -48,6 +48,13 @@
//class TMLCommand;
class TMLChannel;
+enum vcdTransVisState
+ {
+ END_IDLE_TRANS,
+ END_PENALTY_TRANS,
+ END_TASK_TRANS
+};
+
class TMLTransaction {
public:
///Constructor
@@ -241,6 +248,10 @@ class TMLTransaction {
inline void setStateID(ID iID) {_stateID=iID;}
inline ID getStateID() {return _stateID;}
inline void setTaskID(ID iID) {_taskID=iID;}
+ inline unsigned int getTransactCoreNumber() {return _transactCoreNumber;}
+ inline void setTransactCoreNumber(unsigned int num) {_transactCoreNumber=num;}
+ inline void setTransVcdOutPutState(vcdTransVisState n) {_transVcdOutputState=n;}
+ inline vcdTransVisState getTransVcdOutPutState() { return _transVcdOutputState;}
void toXML(std::ostringstream& glob, int deviceID, std::string deviceName) const;
@@ -255,6 +266,10 @@ class TMLTransaction {
TMLLength _virtualLength;
///Pointer to the command the transaction belongs to
TMLCommand* _command;
+ ///Core number of the transaction
+ unsigned int _transactCoreNumber;
+ ///State variable for the cpu VCD output
+ vcdTransVisState _transVcdOutputState;
#ifdef PENALTIES_ENABLED
///Idle penalty
TMLTime _idlePenalty;
diff --git a/simulators/c++2/src_simulator/app/TMLChannel.cpp b/simulators/c++2/src_simulator/app/TMLChannel.cpp
index da05937a11..0f2bb5bafd 100755
--- a/simulators/c++2/src_simulator/app/TMLChannel.cpp
+++ b/simulators/c++2/src_simulator/app/TMLChannel.cpp
@@ -67,9 +67,10 @@ BusMaster* TMLChannel::getNextMaster(TMLTransaction* iTrans){
}
BusMaster* TMLChannel::getFirstMaster(TMLTransaction* iTrans){
+ std::cout<<"get First master"<<std::endl;
//if (iTrans->getCommand()->getTask()==_writeTask){
//std::cout << "fima 1\n";
- if (_masters==0 || _slaves==0 || _numberOfHops==0) return 0;
+ if (_masters==0 || _slaves==0 || _numberOfHops==0 ) {return 0;}
//std::cout << "fima 2\n";
if (iTrans==_writeTrans){
//if (iTrans->getCommand()->getTask()==_writeTask){
@@ -78,9 +79,10 @@ BusMaster* TMLChannel::getFirstMaster(TMLTransaction* iTrans){
return _masters[_writeTransCurrHop];
}else{
//std::cout << "fima 4\n";
- if (_slaves[(_numberOfHops/2)]==0) return 0; //NEW!!!
+ if (_slaves[(_numberOfHops/2)]==0) {return 0;} //NEW!!!
//std::cout << "fima 5\n";
_readTransCurrHop=_numberOfHops-1;
+
return _masters[_readTransCurrHop];
}
}
diff --git a/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp b/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp
index ee88335d2e..16017733dc 100755
--- a/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp
+++ b/simulators/c++2/src_simulator/app/TMLbrbwChannel.cpp
@@ -61,6 +61,7 @@ void TMLbrbwChannel::testRead(TMLTransaction* iTrans){
}
void TMLbrbwChannel::write(){
+std::cout<<"write!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"<<std::endl;
#ifdef LOSS_ENABLED
if (_maxNbOfLosses > _nbOfLosses){
TMLLength aLostBytes = _writeTrans->getVirtualLength() * _lossRate + _lossRemainder;
diff --git a/simulators/c++2/src_simulator/arch/Bus.cpp b/simulators/c++2/src_simulator/arch/Bus.cpp
index 420ba0ffad..b23b737ebc 100644
--- a/simulators/c++2/src_simulator/arch/Bus.cpp
+++ b/simulators/c++2/src_simulator/arch/Bus.cpp
@@ -91,7 +91,7 @@ void Bus::schedule(){
//Adds the transaction determined by the scheduling algorithm to the internal list of scheduled transactions
bool Bus::addTransaction(TMLTransaction* iTransToBeAdded){
- //std::cout << "Bus add trans " << _nextTransaction << "\n";
+ std::cout << "Bus add trans ####" << _nextTransaction << "\n";
_endSchedule = _nextTransaction->getEndTime();
//std::cout << "set end time to " << _endSchedule << "\n";
//_transactList.push_back(_nextTransaction);
@@ -257,12 +257,14 @@ void Bus::latencies2XML(std::ostringstream& glob, unsigned int id1, unsigned int
//Returns the next signal change (for vcd output)
void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
+ std::cout<<"bus getnext"<<std::endl;
//std::ostringstream outp;
//std::cout << _transactList.size() << " elements in List of " << _name << std::endl;
if (iInit){
_posTrasactListVCD=_transactList.begin();
_previousTransEndTime=0;
_vcdOutputState=INIT_BUS;
+ std::cout<<"bus init"<<std::endl;
}
if (_posTrasactListVCD == _transactList.end()){
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_BUS) << "bus" << _ID;
@@ -270,11 +272,13 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//oNoMoreTrans=true;
//return _previousTransEndTime;
new (oSigData) SignalChangeData(END_IDLE_BUS, _previousTransEndTime, this);
+ std::cout<<"bus end "<<std::endl;
}else{
TMLTransaction* aCurrTrans=*_posTrasactListVCD;
//oNoMoreTrans=false;
switch (_vcdOutputState){
case END_READ_BUS:
+ std::cout<<"BUS END_READ_BUS"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
@@ -293,6 +297,7 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return _previousTransEndTime;
break;
case END_WRITE_BUS:
+ std::cout<<"BUS END_WRTIE_BUS"<<std::endl;
do{
_previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
_posTrasactListVCD++;
@@ -311,6 +316,7 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
//return _previousTransEndTime;
break;
case INIT_BUS:
+ std::cout<<"BUS INIT_BUS"<<std::endl;
if (aCurrTrans->getStartTimeOperation()!=0){
_vcdOutputState=END_IDLE_BUS;
//outp << VCD_PREFIX << vcdValConvert(END_IDLE_BUS) << "bus" << _ID;
@@ -320,6 +326,7 @@ void Bus::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
return;
}
case END_IDLE_BUS:
+ std::cout<<"BUS END_IDLE_BUS"<<std::endl;
if (aCurrTrans->getCommand()->getTask()==aCurrTrans->getChannel()->getBlockedReadTask()){
_vcdOutputState=END_READ_BUS;
new (oSigData) SignalChangeData(END_READ_BUS, aCurrTrans->getStartTimeOperation(), this);
diff --git a/simulators/c++2/src_simulator/arch/CPU.h b/simulators/c++2/src_simulator/arch/CPU.h
index 1c125bd2cd..eac87b3272 100755
--- a/simulators/c++2/src_simulator/arch/CPU.h
+++ b/simulators/c++2/src_simulator/arch/CPU.h
@@ -70,7 +70,7 @@ public:
\param iName Name of the device
\param iScheduler Pointer to the scheduler object
*/
- CPU(ID iID, std::string iName, WorkloadSource* iScheduler): SchedulableDevice(iID, iName, iScheduler), _lastTransaction(0)/*,_schedulingNeeded(false)*/{
+ CPU(ID iID, std::string iName, WorkloadSource* iScheduler, unsigned int iAmountOfCore): SchedulableDevice(iID, iName, iScheduler), _lastTransaction(0), amountOfCore(iAmountOfCore)/*,_schedulingNeeded(false)*/{
}
///Destructor
virtual ~CPU(){
@@ -111,6 +111,7 @@ public:
SchedulableDevice::writeObject(os);
return os;
}
+ inline unsigned int getAmoutOfCore(){ return amountOfCore;}
///Invalidate schedule of CPU
/*void setRescheduleFlag(){
_schedulingNeeded=true;
@@ -158,6 +159,109 @@ public:
std::cout << "Current Trans " << _name << ": ";
if (_nextTransaction==0) std::cout << "0\n"; else std::cout << _nextTransaction->toString() << "\n";
}*/
+ void schedule2HTML(std::ofstream& myfile) const {
+ myfile << "<h2><span>Scheduling for device: "<< _name << "</span></h2>" << std::endl;
+
+ if ( _transactList.size() == 0 ) {
+ myfile << "<h4>Device never activated</h4>" << std::endl;
+ }
+ else {
+ myfile << "<table>" << std::endl << "<tr>";
+
+ std::map<TMLTask*, std::string> taskCellClasses;
+ unsigned int nextCellClassIndex = 0;
+ TMLTime aCurrTime = 0;
+
+ for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
+ std::cout<<"time : "<<_cycleTime<<std::endl;
+ //std::cout << "CPU:calcSTL: html of CPU " << _name << ": " << (*i)->toString() << std::endl;
+ if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
+ TMLTransaction* aCurrTrans = *i;
+ unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
+
+ if ( aBlanks > 0 ) {
+ writeHTMLColumn( myfile, aBlanks, "not", "idle time" );
+ }
+
+ unsigned int aLength = aCurrTrans->getPenalties();
+
+ if ( aLength != 0 ) {
+ std::ostringstream title;
+ title << "idle:" << aCurrTrans->getIdlePenalty() << " switch:" << aCurrTrans->getTaskSwitchingPenalty();
+ writeHTMLColumn( myfile, aLength, "not", title.str() );
+ }
+
+ aLength = aCurrTrans->getOperationLength();
+
+ // Issue #4
+ TMLTask* task = aCurrTrans->getCommand()->getTask();
+ const std::string cellClass = determineHTMLCellClass( taskCellClasses, task, nextCellClassIndex );
+
+ writeHTMLColumn( myfile, aLength, cellClass, aCurrTrans->toShortString() );
+
+ aCurrTime = aCurrTrans->getEndTime();
+ }
+ }
+
+
+ myfile << "</tr>" << std::endl << "<tr>";
+
+ for ( unsigned int aLength = 0; aLength < aCurrTime; aLength++ ) {
+ myfile << "<th></th>";
+ }
+
+ myfile << "</tr>" << std::endl << "<tr>";
+
+ for ( unsigned int aLength = 0; aLength <= aCurrTime; aLength += 5 ) {
+ std::ostringstream spanVal;
+ spanVal << aLength;
+ writeHTMLColumn( myfile, 5, "sc", "", spanVal.str(), false );
+ //myfile << "<td colspan=\"5\" class=\"sc\">" << aLength << "</td>";
+ }
+
+ myfile << "</tr>" << std::endl << "</table>" << std::endl << "<table>" << std::endl << "<tr>";
+
+ for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
+ TMLTask* task = (*taskColIt).first;
+ // Unset the default td max-width of 5px. For some reason setting the max-with on a specific t style does not work
+ myfile << "<td class=\"" << taskCellClasses[ task ] << "\"></td><td style=\"max-width: unset;\">" << task->toString() << "</td><td class=\"space\"></td>";
+ }
+
+ myfile << "</tr>" << std::endl;
+
+ #ifdef ADD_COMMENTS
+ bool aMoreComments = true, aInit = true;
+ Comment* aComment;
+
+ while ( aMoreComments ) {
+ aMoreComments = false;
+ myfile << "<tr>";
+
+ for( std::map<TMLTask*, std::string>::iterator taskColIt = taskCellClasses.begin(); taskColIt != taskCellClasses.end(); ++taskColIt ) {
+ //for(TaskList::const_iterator j=_taskList.begin(); j != _taskList.end(); ++j){
+ TMLTask* task = (*taskColIt).first;
+ std::string aCommentString = task->getNextComment( aInit, aComment );
+
+ if ( aComment == 0 ) {
+ myfile << "<td></td><td></td><td class=\"space\"></td>";
+ }
+ else {
+ replaceAll(aCommentString,"<","<");
+ replaceAll(aCommentString,">",">");
+ aMoreComments = true;
+ myfile << "<td style=\"max-width: unset;\">" << aComment->_time << "</td><td><pre>" << aCommentString << "</pre></td><td class=\"space\"></td>";
+ }
+ }
+
+ aInit = false;
+ myfile << "</tr>" << std::endl;
+ }
+ #endif
+ myfile << "</table>" << std::endl;
+ }
+ }
+
protected:
///List of all tasks running on the CPU
TaskList _taskList;
@@ -165,6 +269,8 @@ protected:
TMLTransaction* _lastTransaction;
///List of bus masters
BusMasterList _busMasterList;
+ ///Amount of cores
+ unsigned int amountOfCore;
///Dirty flag of the current scheduling decision
//bool _schedulingNeeded;
};
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index caa144b335..7358e2b3e9 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -48,25 +48,38 @@
//#include <TransactionListener.h>
-MultiCoreCPU::MultiCoreCPU(ID iID, std::string iName, WorkloadSource* iScheduler, WorkloadSource* iScheduler2, TMLTime iTimePerCycle, unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc, unsigned int iPipelineSize, unsigned int iTaskSwitchingCycles, unsigned int iBranchingMissrate, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle, unsigned int ibyteDataSize): CPU(iID, iName, iScheduler), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle)
+MultiCoreCPU::MultiCoreCPU(ID iID,
+ std::string iName,
+ WorkloadSource* iScheduler,
+ TMLTime iTimePerCycle,
+ unsigned int iCyclesPerExeci,
+ unsigned int iCyclesPerExecc,
+ unsigned int iPipelineSize,
+ unsigned int iTaskSwitchingCycles,
+ unsigned int iBranchingMissrate,
+ unsigned int iChangeIdleModeCycles,
+ unsigned int iCyclesBeforeIdle,
+ unsigned int ibyteDataSize,
+ unsigned int iAmountOfCore): CPU(iID, iName, iScheduler, iAmountOfCore), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle), coreNumber(0)
#ifdef PENALTIES_ENABLED
- , _pipelineSize(iPipelineSize), _taskSwitchingCycles(iTaskSwitchingCycles),_brachingMissrate(iBranchingMissrate)
- , _changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
+ , _pipelineSize(iPipelineSize), _taskSwitchingCycles(iTaskSwitchingCycles),_brachingMissrate(iBranchingMissrate)
+ , _changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
#endif
- , _cyclesPerExeci(iCyclesPerExeci) /*, _busyCycles(0)*/
+ , _cyclesPerExeci(iCyclesPerExeci) /*, _busyCycles(0)*/
#ifdef PENALTIES_ENABLED
- , _timePerExeci(_cyclesPerExeci * _timePerCycle * (_pipelineSize * _brachingMissrate + 100 - _brachingMissrate) /100.0)
- ,_taskSwitchingTime(_taskSwitchingCycles*_timePerCycle)
- , _timeBeforeIdle(_cyclesBeforeIdle*_timePerCycle)
- , _changeIdleModeTime(_changeIdleModeCycles*_timePerCycle)
+ , _timePerExeci(_cyclesPerExeci * _timePerCycle * (_pipelineSize * _brachingMissrate + 100 - _brachingMissrate) /100.0)
+ ,_taskSwitchingTime(_taskSwitchingCycles*_timePerCycle)
+ , _timeBeforeIdle(_cyclesBeforeIdle*_timePerCycle)
+ , _changeIdleModeTime(_changeIdleModeCycles*_timePerCycle)
#else
- , _timePerExeci(_cyclesPerExeci*_timePerCycle)
+ , _timePerExeci(_cyclesPerExeci*_timePerCycle)
#endif
- //, _pipelineSizeTimesExeci(_pipelineSize * _timePerExeci)
- //,_missrateTimesPipelinesize(_brachingMissrate*_pipelineSize)
+ //, _pipelineSizeTimesExeci(_pipelineSize * _timePerExeci)
+ //,_missrateTimesPipelinesize(_brachingMissrate*_pipelineSize)
{
//std::cout << "Time per EXECIiiiiiiiiiiiiiiiiiiiiii: " << _timePerExeci << "\n";
//_transactList.reserve(BLOCK_SIZE);
+ initCore();
}
MultiCoreCPU::~MultiCoreCPU(){
@@ -76,7 +89,38 @@ MultiCoreCPU::~MultiCoreCPU(){
//delete _scheduler;
}
+///test///
+void MultiCoreCPU::initCore(){
+ for (unsigned int i = 0; i < amountOfCore; i++)
+ multiCore[i] = 0;
+}
+
+/*unsigned int MultiCoreCPU::getCoreNumber(){
+ unsigned int i;
+ for( i = 0; i < amountOfCore; i++){
+ if(multiCore[i] == 0){
+ multiCore[i]=-1;
+ break;
+ }
+ }
+ return i;
+}*/
+
+TMLTime MultiCoreCPU::getMinEndSchedule(){
+ TMLTime minTime=multiCore[0];
+ for( TMLTime i = 0; i < multiCore.size(); i++){
+ std::cout<<"core number is: "<<i<<" end schedule is "<<multiCore[i]<<std::endl;
+ if( minTime >= multiCore[i]){
+ minTime=multiCore[i];
+ coreNumber=i;
+ }
+ }
+ std::cout<<"in getMinEndSchedule core number is "<<coreNumber<<std::endl;
+ return minTime;
+}
+
TMLTransaction* MultiCoreCPU::getNextTransaction(){
+std::cout<<"getNextTransaction"<<_name<<std::endl;
#ifdef BUS_ENABLED
if (_masterNextTransaction == 0 || _nextTransaction == 0){
return _nextTransaction;
@@ -84,7 +128,7 @@ TMLTransaction* MultiCoreCPU::getNextTransaction(){
#ifdef DEBUG_CPU
std::cout << "CPU:getNT: " << _name << " has bus transaction on master " << _masterNextTransaction->toString() << std::endl;
#endif
- //std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
+ std::cout << "CRASH Trans:" << _nextTransaction->toString() << std::endl << "Channel: " << _nextTransaction->getChannel() << "\n";
BusMaster* aTempMaster = getMasterForBus(_nextTransaction->getChannel()->getFirstMaster(_nextTransaction));
//std::cout << "1 aTempMaster: " << aTempMaster << std::endl;
bool aResult = aTempMaster->accessGranted();
@@ -104,11 +148,13 @@ TMLTransaction* MultiCoreCPU::getNextTransaction(){
}
void MultiCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
+std::cout<<"calcStartTimeLength"<<_name<<std::endl;
#ifdef DEBUG_CPU
std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
#endif
#ifdef BUS_ENABLED
- //std::cout << "get channel " << std::endl;
+std::cout << "CPU:calcSTL: scheduling decision of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
+ //std::cout << " " << std::endl;
TMLChannel* aChannel=_nextTransaction->getCommand()->getChannel(0);
//std::cout << "after get channel " << std::endl;
if(aChannel == 0){
@@ -129,7 +175,7 @@ void MultiCoreCPU::calcStartTimeLength(TMLTime iTimeSlice){
TMLTime aStartTime = max(_endSchedule,_nextTransaction->getRunnableTime());
TMLTime aReminder = aStartTime % _timePerCycle;
if (aReminder!=0) aStartTime+=_timePerCycle - aReminder;
- std::cout << "CPU: set starttime in CPU=" << aStartTime << "\n";
+ std::cout << _name << "CPU: set starttime in CPU=" << aStartTime << "\n";
_nextTransaction->setStartTime(aStartTime);
@@ -222,7 +268,7 @@ TMLTime MultiCoreCPU::truncateNextTransAt(TMLTime iTime){
_nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
}
#else
- if (iTime <= _nextTransaction->getStartTime()) return 0; //before: <=
+ if (iTime <= _nextTransaction->getStartTime()) return 0; //before
TMLTime aNewDuration = iTime - _nextTransaction->getStartTime();
_nextTransaction->setVirtualLength(max((TMLTime)(aNewDuration /_timePerExeci), (TMLTime)1));
_nextTransaction->setLength(_nextTransaction->getVirtualLength() *_timePerExeci);
@@ -236,6 +282,7 @@ TMLTime MultiCoreCPU::truncateNextTransAt(TMLTime iTime){
}
bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
+std::cout<<"addTransaction"<<_name<<std::endl;
bool aFinish;
//TMLTransaction* aTransCopy=0;
if (_masterNextTransaction==0){
@@ -286,7 +333,26 @@ bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
#endif
//_nextTransaction->getCommand()->execute(); //NEW!!!!
std::cout << "CPU:addt: to be started" << std::endl;
+std::cout << "CPU:calcSTL: addtransaction of CPU " << _name << ": " << _nextTransaction->toString() << std::endl;
_endSchedule=_nextTransaction->getEndTime();
+ ////test///
+ // unsigned int iCoreNumber=getCoreNumber();
+ static unsigned int time=0;
+ std::cout<<"multicore number "<<coreNumber<<" end schedule "<<_endSchedule<<std::endl;
+ multiCore[coreNumber]=_endSchedule;
+ // std::cout<<"cycle time is "<<_cycleTime<<std::endl;
+ if (time < amountOfCore -1){
+ _endSchedule=0;
+ _nextTransaction->setTransactCoreNumber(coreNumber);
+ ++coreNumber;
+ std::cout<<"haha1: "<<coreNumber<<std::endl;
+ }else {
+ _nextTransaction->setTransactCoreNumber(coreNumber);
+ _endSchedule=getMinEndSchedule();
+ std::cout<<"haha2: "<<coreNumber<<std::endl;
+ }
+ time++;
+ std::cout <<"test transaction core number !!!! "<<_nextTransaction->getTransactCoreNumber()<<std::endl;
std::cout << "set end schedule CPU: " << _endSchedule << "\n";
_simulatedTime=max(_simulatedTime,_endSchedule);
_overallTransNo++; //NEW!!!!!!!!
@@ -310,7 +376,7 @@ bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
void MultiCoreCPU::schedule(){
//std::cout <<"Hello\n";
- //std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
+ std::cout << "CPU:schedule BEGIN " << _name << "+++++++++++++++++++++++++++++++++\n";
TMLTime aTimeSlice = _scheduler->schedule(_endSchedule);
//_schedulingNeeded=false; 05/05/11
//std::cout << "1\n";
@@ -331,6 +397,8 @@ void MultiCoreCPU::schedule(){
//std::cout << "5\n";
if (_nextTransaction!=0 && aOldTransaction != _nextTransaction) calcStartTimeLength(aTimeSlice);
//std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
+ else std::cout<<"no need calcStartTimeLength"<<std::endl;
+ std::cout << "CPU:schedule END " << _name << "+++++++++++++++++++++++++++++++++\n";
}
//std::string MultiCoreCPU::toString() const{
@@ -339,7 +407,7 @@ void MultiCoreCPU::schedule(){
std::string MultiCoreCPU::toShortString() const{
std::ostringstream outp;
- outp << "cpu" << _ID;
+ outp << "cpu" << _ID ;
return outp.str();
}
@@ -469,72 +537,95 @@ void MultiCoreCPU::latencies2XML(std::ostringstream& glob, unsigned int id1, uns
-//TMLTime MultiCoreCPU::getNextSignalChange(bool iInit, std::string& oSigChange, bool& oNoMoreTrans){
+
void MultiCoreCPU::getNextSignalChange(bool iInit, SignalChangeData* oSigData){
- //new (oSigData) SignalChangeData(RUNNING, aCurrTrans->getStartTimeOperation(), this);
- //std::ostringstream outp;
- //oNoMoreTrans=false;
- if (iInit){
- _posTrasactListVCD=_transactList.begin();
- _previousTransEndTime=0;
- _vcdOutputState=END_IDLE_CPU;
- if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()!=0){
- //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
- //oSigChange=outp.str();
- new (oSigData) SignalChangeData(END_IDLE_CPU, 0, this);
- //return 0
- return;
- }
- }
- if (_posTrasactListVCD == _transactList.end()){
- //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
- //oSigChange=outp.str();
- //oNoMoreTrans=true;
- //return _previousTransEndTime;
- new (oSigData) SignalChangeData(END_IDLE_CPU, _previousTransEndTime, this);
- }else{
- TMLTransaction* aCurrTrans=*_posTrasactListVCD;
- switch (_vcdOutputState){
- case END_TASK_CPU:
- do{
- _previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
- _posTrasactListVCD++;
- }while (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTimeOperation()==_previousTransEndTime);
- if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
- //outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
- _vcdOutputState=END_PENALTY_CPU;
- new (oSigData) SignalChangeData(END_PENALTY_CPU, _previousTransEndTime, this);
- }else{
- //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
- _vcdOutputState=END_IDLE_CPU;
- //if (_posTrasactListVCD == _transactList.end()) oNoMoreTrans=true;
- new (oSigData) SignalChangeData(END_IDLE_CPU, _previousTransEndTime, this);
+ static bool _end=false;
+ std::cout<<"getNextSignalChangemulticore!!!---------"<<std::endl;
+ for( TransactionList::iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ std::cout<<"transaction core number is "<< (*i)->getTransactCoreNumber()<<std::endl;
+ std::cout<<"cycle time is "<< this->_cycleTime<<std::endl;
+ if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
+ _posTrasactListVCD= i;
+ std::cout<<"bingo!!"<<(*i)->toShortString()<<std::endl;
+ if (iInit){
+ //_posTrasactListVCD= i;
+ _previousTransEndTime=0;
+ (*i)->setTransVcdOutPutState(END_IDLE_TRANS);
+ std::cout<<"init"<<std::endl;
+ if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()!=0){
+ //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
+ //oSigChange=outp.str();
+ new (oSigData) SignalChangeData(END_IDLE_TRANS, 0, this);
+ //return 0
+ return;
+ }
}
- //oSigChange=outp.str();
- //return _previousTransEndTime;
- break;
- case END_PENALTY_CPU:
- //outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
- //oSigChange=outp.str();
- _vcdOutputState=END_TASK_CPU;
- //return aCurrTrans->getStartTimeOperation();
- new (oSigData) SignalChangeData(END_TASK_CPU, aCurrTrans->getStartTimeOperation(), this);
- break;
- case END_IDLE_CPU:
- if (aCurrTrans->getPenalties()==0){
- //outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
- _vcdOutputState=END_TASK_CPU;
- new (oSigData) SignalChangeData(END_TASK_CPU, aCurrTrans->getStartTime(), this);
+ if (_end==true || _posTrasactListVCD == _transactList.end()){
+ //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
+ //oSigChange=outp.str();
+ //oNoMoreTrans=true;
+ //return _previousTransEndTime;
+ std::cout<<"end transact"<<std::endl;
+ new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
+ this->_cycleTime++;
+ _end=false;
+ break;
}else{
- //outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
- _vcdOutputState=END_PENALTY_CPU;
- new (oSigData) SignalChangeData(END_PENALTY_CPU, aCurrTrans->getStartTime(), this);
- }
- //oSigChange=outp.str();
- //return aCurrTrans->getStartTime();
- break;
+ //_posTrasactListVCD = i;
+ TMLTransaction* aCurrTrans=*_posTrasactListVCD;
+ switch (aCurrTrans->getTransVcdOutPutState()){
+ case END_TASK_TRANS:
+ std::cout<<"END_TASK_CPU"<<std::endl;
+ do{
+ _previousTransEndTime=(*_posTrasactListVCD)->getEndTime();
+ _posTrasactListVCD++;
+ }while (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTimeOperation()==_previousTransEndTime);
+ if (_posTrasactListVCD != _transactList.end() && (*_posTrasactListVCD)->getStartTime()==_previousTransEndTime){
+ //outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_PENALTY_TRANS);
+ new (oSigData) SignalChangeData(END_PENALTY_TRANS, _previousTransEndTime, this);
+ }else{
+ //outp << VCD_PREFIX << vcdValConvert(END_IDLE_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_IDLE_TRANS);
+ //if (_posTrasactListVCD == _transactList.end()) oNoMoreTrans=true;
+ new (oSigData) SignalChangeData(END_IDLE_TRANS, _previousTransEndTime, this);
+ _end=true;
+ }
+ //oSigChange=outp.str();
+ //return _previousTransEndTime;
+ // this->_cycleTime++;
+ break;
+ case END_PENALTY_TRANS:
+
+ std::cout<<"END_PENALTY_CPU"<<std::endl;
+ //outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
+ //oSigChange=outp.str();
+ aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
+ //return aCurrTrans->getStartTimeOperation();
+ new (oSigData) SignalChangeData(END_TASK_TRANS, aCurrTrans->getStartTimeOperation(), this);
+ break;
+ case END_IDLE_TRANS:
+ std::cout<<"END_IDLE_CPU"<<std::endl;
+ if (aCurrTrans->getPenalties()==0){
+ //outp << VCD_PREFIX << vcdValConvert(END_TASK_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_TASK_TRANS);
+ new (oSigData) SignalChangeData(END_TASK_TRANS, aCurrTrans->getStartTime(), this);
+ }else{
+ //outp << VCD_PREFIX << vcdValConvert(END_PENALTY_CPU) << "cpu" << _ID;
+ aCurrTrans->setTransVcdOutPutState(END_PENALTY_TRANS);
+ new (oSigData) SignalChangeData(END_PENALTY_TRANS, aCurrTrans->getStartTime(), this);
+ }
+ //oSigChange=outp.str();
+ //return aCurrTrans->getStartTime();
+ break;
+ }
+ }
}
+
}
+
+ //if (*_posTrasactListVCD != 0)
+ // std::cout<<"pos trans is !!!!!"<<(*_posTrasactListVCD)->toString()<<std::endl;
//return 0;
}
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
index 4e9f7b938f..7f062e9fdb 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
@@ -77,7 +77,7 @@ public:
\param iCyclesBeforeIdle Idle cycles which elapse before entering idle mode
\param ibyteDataSize Machine word length
*/
- MultiCoreCPU(ID iID, std::string iName, WorkloadSource* iScheduler, WorkloadSource* iScheduler2,TMLTime iTimePerCycle, unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc, unsigned int iPipelineSize, unsigned int iTaskSwitchingCycles, unsigned int iBranchingMissrate, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle, unsigned int ibyteDataSize);
+ MultiCoreCPU(ID iID, std::string iName, WorkloadSource* iScheduler,TMLTime iTimePerCycle, unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc, unsigned int iPipelineSize, unsigned int iTaskSwitchingCycles, unsigned int iBranchingMissrate, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle, unsigned int ibyteDataSize, unsigned int iAmountOfCore);
///Destructor
virtual ~MultiCoreCPU();
///Determines the next CPU transaction to be executed
@@ -145,6 +145,20 @@ protected:
BusMaster* _masterNextTransaction;
///1/Processor frequency
TMLTime _timePerCycle;
+ ///test////
+ unsigned int coreNumber;
+ //first parameter is the core number
+ ///second parameter is the end schedule in the core
+ std::map <unsigned int, unsigned int> multiCore;
+ ///initialization of all cores
+ void initCore();
+ ///get the avaliable core
+ unsigned int getCoreNumber();
+ //inline void setCoreNumber(unsigned int n) { coreNumber=n;}
+ ///return the minimum time of the end schedule in all cores
+ TMLTime getMinEndSchedule();
+ ///end
+
#ifdef PENALTIES_ENABLED
///Pipeline size
unsigned int _pipelineSize;
@@ -170,7 +184,7 @@ protected:
TMLTime _changeIdleModeTime;
#endif
///State variable for the VCD output
- vcdCPUVisState _vcdOutputState;
+ //vcdCPUVisState _vcdOutputState;
};
#endif
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
index 01ab6a13a6..3736944243 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.cpp
@@ -51,7 +51,8 @@ SchedulableDevice::SchedulableDevice( ID iID,
_deleteScheduler(true),
_busyCycles(0),
_static_consumPerCycle (15),
- _dynamic_consumPerCycle (35) {
+ _dynamic_consumPerCycle (35),
+ _cycleTime(0) {
_transactList.reserve( BLOCK_SIZE_TRANS );
}
@@ -183,7 +184,7 @@ std::string SchedulableDevice::determineHTMLCellClass( std::map<TMLTask*, std::
return taskColors[ task ];
}
-void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
+void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
myfile << "<h2><span>Scheduling for device: "<< _name << "</span></h2>" << std::endl;
if ( _transactList.size() == 0 ) {
@@ -197,6 +198,10 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
TMLTime aCurrTime = 0;
for( TransactionList::const_iterator i = _transactList.begin(); i != _transactList.end(); ++i ) {
+ std::cout<<"get transaction core number is: "<<(*i)->getTransactCoreNumber()<<std::endl;
+ std::cout<<"time : "<<_cycleTime<<std::endl;
+ std::cout << "CPU:calcSTL: html of CPU " << _name << ": " << (*i)->toString() << std::endl;
+ //if( (*i)->getTransactCoreNumber() == this->_cycleTime ){
TMLTransaction* aCurrTrans = *i;
unsigned int aBlanks = aCurrTrans->getStartTime() - aCurrTime;
@@ -221,7 +226,9 @@ void SchedulableDevice::schedule2HTML(std::ofstream& myfile) const {
writeHTMLColumn( myfile, aLength, cellClass, aCurrTrans->toShortString() );
aCurrTime = aCurrTrans->getEndTime();
+ // }
}
+
myfile << "</tr>" << std::endl << "<tr>";
diff --git a/simulators/c++2/src_simulator/arch/SchedulableDevice.h b/simulators/c++2/src_simulator/arch/SchedulableDevice.h
index 0d37a9f564..022937405b 100644
--- a/simulators/c++2/src_simulator/arch/SchedulableDevice.h
+++ b/simulators/c++2/src_simulator/arch/SchedulableDevice.h
@@ -148,6 +148,8 @@ public:
static TMLTime getOverallTransNo() { return _overallTransNo; }
static TMLTime getOverallTransSize() { return _overallTransSize; }
+ inline void setCycleTime (unsigned int t) { _cycleTime =t; }
+ inline unsigned int getCycleTime() { return _cycleTime; }
protected:
///Unique ID of the device
@@ -171,9 +173,10 @@ protected:
///Busy cycles since simulation start
TMLTime _busyCycles;
unsigned int _static_consumPerCycle;
- unsigned int _dynamic_consumPerCycle;
+ unsigned int _dynamic_consumPerCycle;
static TMLTime _overallTransNo;
static TMLTime _overallTransSize;
+ unsigned int _cycleTime;
static void writeHTMLColumn( std::ofstream& myfile,
const unsigned int colSpan,
diff --git a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
index 6db43dc279..2f33ab17d8 100644
--- a/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/SingleCoreCPU.cpp
@@ -59,7 +59,7 @@ SingleCoreCPU::SingleCoreCPU( ID iID,
unsigned int iBranchingMissrate,
unsigned int iChangeIdleModeCycles,
unsigned int iCyclesBeforeIdle,
- unsigned int ibyteDataSize ) : CPU( iID, iName, iScheduler ), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle)
+ unsigned int ibyteDataSize ) : CPU( iID, iName, iScheduler, 1), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle)
#ifdef PENALTIES_ENABLED
, _pipelineSize(iPipelineSize), _taskSwitchingCycles(iTaskSwitchingCycles),_brachingMissrate(iBranchingMissrate)
, _changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
diff --git a/simulators/c++2/src_simulator/sim/Simulator.cpp b/simulators/c++2/src_simulator/sim/Simulator.cpp
index 43f3fe4674..044d7f6c1a 100644
--- a/simulators/c++2/src_simulator/sim/Simulator.cpp
+++ b/simulators/c++2/src_simulator/sim/Simulator.cpp
@@ -289,6 +289,7 @@ void Simulator::latencies2XML(std::ostringstream& glob, int id1, int id2) {
}
void Simulator::schedule2HTML(std::string& iTraceFileName) const {
+std::cout<<"schedule2HTML--------------------------------------******************"<<std::endl;
struct timeval aBegin,aEnd;
gettimeofday(&aBegin,NULL);
@@ -297,6 +298,7 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
}
std::ofstream myfile(iTraceFileName.c_str());
+ myfile<<iTraceFileName.c_str()<<std::endl;
if (myfile.is_open()) {
// DB: Issue #4
@@ -309,23 +311,24 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
if ( findSlash == std::string::npos ) {
indexSlash = 0;
+ myfile<<"indexSlash=0\n";
}
else {
indexSlash = findSlash;
}
const std::string ext( EXT_HTML );
- const std::string cssFileName = iTraceFileName.substr( indexSlash + 1, iTraceFileName.length() - indexSlash - ext.length() - 1 ) + EXT_CSS;
-
+ const std::string cssFileName = iTraceFileName.substr( indexSlash + 1, iTraceFileName.length() - indexSlash - ext.length() - 1 ) + EXT_CSS;
+ myfile<<"length is "<< iTraceFileName.length() - indexSlash - ext.length() - 1<<std::endl;
const std::string cssFullFileName = iTraceFileName.substr( 0, indexSlash + 1 ) + cssFileName;
std::ofstream cssfile( cssFullFileName.c_str() );
-
+ myfile<<"full name is "<<cssFullFileName<<std::endl;
if ( cssfile.is_open() ) {
cssfile << SCHED_HTML_CSS_CONTENT;
cssfile.close();
myfile << SCHED_HTML_CSS_BEG_LINK;
- myfile << cssFileName;
+ myfile << cssFullFileName;
myfile << SCHED_HTML_CSS_END_LINK;
}
else {
@@ -343,7 +346,14 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
//for(CPUList::const_iterator i=_simComp->getCPUIterator(false); i != _simComp->getCPUIterator(true); ++i){
for(CPUList::const_iterator i=_simComp->getCPUList().begin(); i != _simComp->getCPUList().end(); ++i){
- (*i)->schedule2HTML(myfile);
+ for(unsigned int j = 0; j < (*i)->getAmoutOfCore(); j++) {
+ std::cout<<"core number is "<<(*i)->getAmoutOfCore()<<std::endl;
+ (*i)->schedule2HTML(myfile);
+ (*i)->setCycleTime((*i)->getCycleTime()+1);
+ std::cout<<"~~~~~~~~~~~~~~~~~~"<<std::endl;
+ }
+ if((*i)->getAmoutOfCore() == 1)
+ (*i)->setCycleTime(0);
}
//for(BusList::const_iterator j=_simComp->getBusIterator(false); j != _simComp->getBusIterator(true); ++j){
for(BusList::const_iterator j=_simComp->getBusList().begin(); j != _simComp->getBusList().end(); ++j){
@@ -365,6 +375,7 @@ void Simulator::schedule2HTML(std::string& iTraceFileName) const {
}
void Simulator::schedule2VCD(std::string& iTraceFileName) const{
+ std::cout<<"schedule2VCD~~~~~~~~~~~~"<<std::endl;
time_t aRawtime;
struct tm * aTimeinfo;
struct timeval aBegin,aEnd;
@@ -381,7 +392,8 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
if (myfile.is_open()){
//std::cout << "File is open" << std::endl;
SignalChangeQueue aQueue;
- std::string aSigString;
+ SignalChangeQueue aQueueCPU;
+ //std::string aSigString;
//bool aNoMoreTrans;
//TraceableDevice* actDevice;
TMLTime aCurrTime=-1;
@@ -390,7 +402,7 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
myfile << "$date\n" << asctime(aTimeinfo) << "$end\n\n$version\nDaniel's TML simulator\n$end\n\n";
myfile << "$timescale\n5 ns\n$end\n\n$scope module Simulation $end\n";
//std::cout << "Before 1st loop" << std::endl;
- //for (TraceableDeviceList::const_iterator i=_simComp->getVCDIterator(false); i!= _simComp->getVCDIterator(true); ++i){
+
for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
//TraceableDevice* a=*i;
// a->streamBenchmarks(std::cout);
@@ -398,56 +410,142 @@ void Simulator::schedule2VCD(std::string& iTraceFileName) const{
//std::cout << "in 1st loop " << a << std::endl;
//std::cout << "device: " << (*i)->toString() << std::endl;
//myfile << "$var integer 3 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
- myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
- //std::cout << "get next signal change" << std::endl;
- //aTime = (*i)->getNextSignalChange(true, aSigString, aNoMoreTrans);
- aTopElement = new SignalChangeData();
- (*i)->getNextSignalChange(true, aTopElement);
- aQueue.push(aTopElement);
- //std::cout << "push" << std::endl;
- //aQueue.push(new SignalChangeData(aSigString, aTime, (aNoMoreTrans)?0:(*i)));
+
+ if ((*i)->toShortString().substr(0,3) == "cpu"){
+ for(unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore(); j++) {
+ myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() <<"_Core"<<(j+1)<< " $end\n";
+ aTopElement = new SignalChangeData();
+ (*i)->getNextSignalChange(true, aTopElement);
+ aQueueCPU.push(aTopElement);
+ myfile << "$var integer 32 clk Clock $end\n";
+ myfile << "$upscope $end\n$enddefinitions $end\n\n";
+ while (!aQueueCPU.empty()){
+ //static unsigned int count = 0;
+
+ std::cout<<"this is CPU queue"<<std::endl;
+ aTopElement=aQueueCPU.top();
+ std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<<std::endl;
+
+ while (aNextClockEvent < aTopElement->_time){
+ myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
+ aNextClockEvent+=CLOCK_INC;
+ }
+ if (aCurrTime!=aTopElement->_time){
+ aCurrTime=aTopElement->_time;
+ myfile << "#" << aCurrTime << "\n";
+ }
+ if (aNextClockEvent == aTopElement->_time){
+ myfile << "b" << vcdTimeConvert(aNextClockEvent) << " clk\n";
+ aNextClockEvent+=CLOCK_INC;
+ }
+ //myfile << aTopElement->_sigChange << "\n";
+ myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
+ aQueueCPU.pop();
+ TMLTime aTime = aTopElement->_time;
+
+ //std::cout<<"lets get next signal : )"<<std::endl;
+ //if (aTopElement->_device->toShortString().substr(0,3) == "cpu")
+ // std::cout<<"!!!!!"<<(dynamic_cast<CPU*>(aTopElement->_device))->getCycleTime()<<std::endl;
+ std::cout<<"The cycle is cpu is ~~~!!"<<dynamic_cast<CPU*>(aTopElement->_device)->getCycleTime()<<std::endl;
+ aTopElement->_device->getNextSignalChange(false, aTopElement);
+ //dynamic_cast<CPU*>(aTopElement->_device)->setCycleTime((++count)% (dynamic_cast<CPU*>(aTopElement->_device)->getAmoutOfCore()));
+ std::cout<<"aTime is "<<aTime<<std::endl;
+ std::cout<<"top element time is "<<aTopElement->_time<<std::endl;
+ if (aTopElement->_time == aTime){
+ delete aTopElement;
+ std::cout<<"delete"<<std::endl;
+ }
+ else{
+ aQueueCPU.push(aTopElement);
+ std::cout<<"no delete"<<std::endl;
+ }
+ }
+ // (dynamic_cast<CPU*>(*i))->setCycleTime( (dynamic_cast<CPU*>(*i))->getCycleTime()+1);
+ }
+ }
+ else{
+ myfile << "$var wire 1 " << (*i)->toShortString() << " " << (*i)->toString() << " $end\n";
+ aTopElement = new SignalChangeData();
+ (*i)->getNextSignalChange(true, aTopElement);
+ aQueue.push(aTopElement);
+ }
}
+
+
+ // (dynamic_cast<CPU*>(*i))->setCycleTime( (dynamic_cast<CPU*>(*i))->getCycleTime()+1);
+
+
+
+
+ //if sucess, make it as a fonction !!!! change
+ /* for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
+ if ((*i)->toShortString().substr(0,3) == "cpu"){
+ for(unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore(); j++) {
+ (dynamic_cast<CPU*>(*i))->setCycleTime(0);
+ }
+ }
+ }*/
+
myfile << "$var integer 32 clk Clock $end\n";
myfile << "$upscope $end\n$enddefinitions $end\n\n";
- //std::cout << "Before 2nd loop" << std::endl;
+ //TMLTime aTimeCPU=0;
+
+
+
while (!aQueue.empty()){
+ std::cout<<"this is queue"<<std::endl;
aTopElement=aQueue.top();
+ std::cout<<"the member of queue is "<<aTopElement->_device->toShortString()<<std::endl;
+
while (aNextClockEvent < aTopElement->_time){
- myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
- aNextClockEvent+=CLOCK_INC;
+ myfile << "#" << aNextClockEvent << "\nr" << aNextClockEvent << " clk\n";
+ aNextClockEvent+=CLOCK_INC;
}
if (aCurrTime!=aTopElement->_time){
- aCurrTime=aTopElement->_time;
- myfile << "#" << aCurrTime << "\n";
+ aCurrTime=aTopElement->_time;
+ myfile << "#" << aCurrTime << "\n";
}
if (aNextClockEvent == aTopElement->_time){
- myfile << "b" << vcdTimeConvert(aNextClockEvent) << " clk\n";
- aNextClockEvent+=CLOCK_INC;
+ myfile << "b" << vcdTimeConvert(aNextClockEvent) << " clk\n";
+ aNextClockEvent+=CLOCK_INC;
}
//myfile << aTopElement->_sigChange << "\n";
myfile << vcdValConvert(aTopElement->_sigChange) << aTopElement->_device->toShortString() << "\n";
aQueue.pop();
TMLTime aTime = aTopElement->_time;
aTopElement->_device->getNextSignalChange(false, aTopElement);
- if (aTopElement->_time == aTime)
- delete aTopElement;
- else
- aQueue.push(aTopElement);
+ std::cout<<"aTime is "<<aTime<<std::endl;
+ std::cout<<"top element time is "<<aTopElement->_time<<std::endl;
+ if (aTopElement->_time == aTime){
+ delete aTopElement;
+ std::cout<<"delete"<<std::endl;
+ }
+ else{
+ aQueue.push(aTopElement);
+ std::cout<<"no delete"<<std::endl;
+ }
+ }
+
//actDevice=aTopElement->_device;
//if (actDevice!=0) aTime = actDevice->getNextSignalChange(false, aSigString, aNoMoreTrans);
//delete aTopElement;
//aQueue.pop();
//if (actDevice!=0) aQueue.push(new SignalChangeData(aSigString, aTime, (aNoMoreTrans)?0:actDevice));
- }
+
myfile << "#" << aCurrTime+1 << "\n";
std::cout << "Simulated cycles: " << aCurrTime << std::endl;
//for (TraceableDeviceList::const_iterator i=_simComp->getVCDIterator(false); i!= _simComp->getVCDIterator(true); ++i){
+ ///////test//////////
for (TraceableDeviceList::const_iterator i=_simComp->getVCDList().begin(); i!= _simComp->getVCDList().end(); ++i){
+ if ((*i)->toShortString().substr(0,3)=="cpu"){
+ for (unsigned int j = 0; j < (dynamic_cast<CPU*>(*i))->getAmoutOfCore();j++){
+ myfile << "0" << (*i)->toShortString() << "\n";
+ }
+ }
//myfile << VCD_PREFIX << "100 " << (*i)->toShortString() << "\n";
- myfile << "0" << (*i)->toShortString() << "\n";
+ else myfile << "0" << (*i)->toShortString() << "\n";
//std::cout << "Utilization of component " << (*i)->toString() << ": " << ((float)(*i)->getBusyCycles()) / ((float)aCurrTime) << std::endl;
}
-
myfile.close();
}
else
@@ -490,9 +588,10 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
//std::cout << "after loop2" << std::endl;
//for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::setRescheduleFlag));
//for_each(_simComp->getCPUIterator(false), _simComp->getCPUIterator(true),std::mem_fun(&CPU::schedule));
+ std::cout<<"simulate"<<std::endl;
for_each(_simComp->getCPUList().begin(), _simComp->getCPUList().end(),std::mem_fun(&CPU::schedule));
//std::cout << "after schedule" << std::endl;
- transLET=getTransLowestEndTime(cpuLET);
+ transLET=getTransLowestEndTime(cpuLET);
//std::cout << "after getTLET" << std::endl;
#ifdef LISTENERS_ENABLED
if (_wasReset) NOTIFY_SIM_STARTED();
@@ -511,7 +610,11 @@ bool Simulator::simulate(TMLTransaction*& oLastTrans){
std::cout << "cpuLET= " << cpuLET->toString() << std::endl;
std::cout << "kernel:simulate:cpuLET printed" << std::endl;
#endif
+ std::cout<<"in simulator begin addTransaction "<<std::endl;
bool x = cpuLET->addTransaction(0);
+ // cpuLET->setCycleTime(0);
+ std::cout<<"in simulator end addTransactin "<<std::endl;
+
//std::cout << "kernel:simulate: x=" << x << std::endl;
#ifdef DEBUG_KERNEL
std::cout << "kernel:simulate: AFTER add trans: " << x << std::endl;
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
index 9e0732bf04..11109e4240 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
@@ -178,7 +178,7 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
header += "#include <AliasConstraint.h>\n#include <EqConstraint.h>\n#include <LogConstraint.h>\n#include <PropLabConstraint.h>\n";
header += "#include <PropRelConstraint.h>\n#include <SeqConstraint.h>\n#include <SignalConstraint.h>\n#include <TimeMMConstraint.h>\n";
header += "#include <TimeTConstraint.h>\n";
- header += "#include <CPU.h>\n#include <SingleCoreCPU.h>\n#include <RRScheduler.h>\n#include <RRPrioScheduler.h>\n#include <PrioScheduler.h>\n#include <Bus.h>\n";
+ header += "#include <CPU.h>\n#include <SingleCoreCPU.h>\n#include <MultiCoreCPU.h>\n#include <RRScheduler.h>\n#include <RRPrioScheduler.h>\n#include <PrioScheduler.h>\n#include <Bus.h>\n";
header += "#include <Bridge.h>\n#include <Memory.h>\n#include <TMLbrbwChannel.h>\n#include <TMLnbrnbwChannel.h>\n";
header += "#include <TMLbrnbwChannel.h>\n#include <TMLEventBChannel.h>\n#include <TMLEventFChannel.h>\n#include <TMLEventFBChannel.h>\n";
header += "#include <TMLTransaction.h>\n#include <TMLCommand.h>\n#include <TMLTask.h>\n";
@@ -216,18 +216,32 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
}
//TraceManager.addDev("cores " + exNode.nbOfCores);
+
- for (int cores = 0; cores < exNode.nbOfCores; cores++) {
+ /*for (int cores = 0; cores < exNode.nbOfCores; cores++) {
final String cpuInstName = namesGen.cpuInstanceName(exNode, cores);
declaration += "CPU* " + cpuInstName + " = new SingleCoreCPU(" + exNode.getID() + ", \"" + namesGen.cpuName(exNode, cores) + "\", " + schedulerInstName + ", ";
declaration += exNode.clockRatio + ", " + exNode.execiTime + ", " + exNode.execcTime + ", " + exNode.pipelineSize + ", " + exNode.taskSwitchingTime + ", " + exNode.branchingPredictionPenalty + ", " + exNode.goIdleTime + ", " + exNode.maxConsecutiveIdleCycles + ", " + exNode.byteDataSize + ")" + SCCR;
if (cores != 0) {
declaration += cpuInstName + "->setScheduler(" + schedulerInstName + ",false)" + SCCR;
- }
-
+ }*/
+ final String cpuInstName = namesGen.cpuInstanceName(exNode, exNode.nbOfCores);
+ if (exNode.nbOfCores == 1) {
+ declaration += "CPU* " + exNode.getName() + "_" + exNode.nbOfCores + " = new SingleCoreCPU(" + exNode.getID() + ", \"" + exNode.getName() + "_" + exNode.nbOfCores + "\", "
+ + exNode.getName() + "_scheduler" + ", ";
+
+ declaration += exNode.clockRatio + ", " + exNode.execiTime + ", " + exNode.execcTime + ", " + exNode.pipelineSize + ", "
+ + exNode.taskSwitchingTime + ", " + exNode.branchingPredictionPenalty + ", " + exNode.goIdleTime + ", " + exNode.maxConsecutiveIdleCycles + ", " + exNode.byteDataSize + ")" + SCCR;
+ } else {
+ declaration += "CPU* " + exNode.getName() + "_" + exNode.nbOfCores + " = new MultiCoreCPU(" + exNode.getID() + ", \"" + exNode.getName() + "_" + exNode.nbOfCores + "\", " + exNode.getName() + "_scheduler" + ", ";
+
+ declaration += exNode.clockRatio + ", " + exNode.execiTime + ", " + exNode.execcTime + ", " + exNode.pipelineSize + ", " + exNode.taskSwitchingTime + ", " + exNode.branchingPredictionPenalty + ", " + exNode.goIdleTime + ", " + exNode.maxConsecutiveIdleCycles + ", " + exNode.byteDataSize +", " + exNode.nbOfCores + ")" + SCCR;
+ }
+
+
declaration += "addCPU(" + cpuInstName + ")" + SCCR;
- }
+ //}
} else if (node instanceof HwA) {
final HwA hwaNode = (HwA) node;
final String schedulerInstName = namesGen.rrSchedulerInstanceName(hwaNode);
@@ -320,18 +334,18 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
noOfCores = 1;
}
- for (int cores = 0; cores < noOfCores; cores++) {
+ //for (int cores = 0; cores < noOfCores; cores++) {
final String nodeInstanceName;
if (node instanceof HwCPU || node instanceof HwA) {
- nodeInstanceName = namesGen.executionNodeInstanceName((HwExecutionNode) node, cores);
+ nodeInstanceName = namesGen.executionNodeInstanceName((HwExecutionNode) node, noOfCores);
} else {
nodeInstanceName = namesGen.bridgeInstanceName((HwBridge) node);
}
- final String busMasterInstName = namesGen.busMasterInstanceName(node, cores, link.bus);
+ final String busMasterInstName = namesGen.busMasterInstanceName(node, 0, link.bus);
- declaration += "BusMaster* " + busMasterInstName + " = new BusMaster(\"" + namesGen.busMasterName(node, cores, link.bus) + "\", " + link.getPriority() + ", " + link.bus.pipelineSize + ", array(" + link.bus.pipelineSize;
+ declaration += "BusMaster* " + busMasterInstName + " = new BusMaster(\"" + namesGen.busMasterName(node, 0, link.bus) + "\", " + link.getPriority() + ", " + link.bus.pipelineSize + ", array(" + link.bus.pipelineSize;
for (int i = 0; i < link.bus.pipelineSize; i++) {
declaration += ", (SchedulableCommDevice*) " + namesGen.schedComDeviceInstanceName(link.bus, i);
@@ -340,7 +354,7 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
declaration += "))" + SCCR;
declaration += nodeInstanceName + "->addBusMaster(" + busMasterInstName + ")" + SCCR;
- }
+ //}
}
}
}
@@ -473,10 +487,12 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
if (link.hwnode instanceof HwCPU) { //|| (link.hwnode instanceof HwA)){
final HwCPU cpu = (HwCPU) link.hwnode;
- for (int cores = 0; cores < cpu.nbOfCores; cores++) {
+ /*for (int cores = 0; cores < cpu.nbOfCores; cores++) {
devices += ", (WorkloadSource*) " + namesGen.workloadSourceInstanceName(cpu, cores, bus);
numDevices++;
- }
+ }*/
+ devices += ", (WorkloadSource*) " + namesGen.workloadSourceInstanceName(cpu, 0, bus);
+ numDevices ++;
} else {
devices += ", (WorkloadSource*) " + namesGen.workloadSourceInstanceName(link.hwnode, 0, bus);
numDevices++;
@@ -524,10 +540,10 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
final HwCPU hwCpu = (HwCPU) node;
declaration += hwCpu.nbOfCores;
- for (int cores = 0; cores < hwCpu.nbOfCores; cores++) {
+ /*for (int cores = 0; cores < hwCpu.nbOfCores; cores++) {
declaration += "," + namesGen.cpuInstanceName(hwCpu, cores);
- }
-
+ }*/
+ declaration += "," + namesGen.cpuInstanceName(hwCpu, hwCpu.nbOfCores);
// declaration+= "),1" + CR;
} else if (node instanceof HwA) {
final HwA hwAcc = (HwA) node;
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java b/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
index b91a3940a8..86dc71144b 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
@@ -163,7 +163,7 @@ public class TML2MappingSystemC implements IDiploSimulatorCodeGenerator {
header += "#include <AliasConstraint.h>\n#include <EqConstraint.h>\n#include <LogConstraint.h>\n#include <PropLabConstraint.h>\n";
header += "#include <PropRelConstraint.h>\n#include <SeqConstraint.h>\n#include <SignalConstraint.h>\n#include <TimeMMConstraint.h>\n";
header += "#include <TimeTConstraint.h>\n";
- header += "#include <CPU.h>\n#include <SingleCoreCPU.h>\n#include <RRScheduler.h>\n#include <RRPrioScheduler.h>\n#include <PrioScheduler.h>\n#include <Bus.h>\n";
+ header += "#include <CPU.h>\n#include <SingleCoreCPU.h>\n#include <MultiCoreCPU.h>\n#include <RRScheduler.h>\n#include <RRPrioScheduler.h>\n#include <PrioScheduler.h>\n#include <Bus.h>\n";
header += "#include <Bridge.h>\n#include <Memory.h>\n#include <TMLbrbwChannel.h>\n#include <TMLnbrnbwChannel.h>\n";
header += "#include <TMLbrnbwChannel.h>\n#include <TMLEventBChannel.h>\n#include <TMLEventFChannel.h>\n#include <TMLEventFBChannel.h>\n";
header += "#include <TMLTransaction.h>\n#include <TMLCommand.h>\n#include <TMLTask.h>\n";
@@ -195,16 +195,20 @@ public class TML2MappingSystemC implements IDiploSimulatorCodeGenerator {
//declaration += "RRScheduler* " + exNode.getName() + "_scheduler = new RRScheduler(\"" + exNode.getName() + "_RRSched\", 0, 5, " + (int) Math.ceil(((float)exNode.execiTime)*(1+((float)exNode.branchingPredictionPenalty)/100)) + " ) " + SCCR;
declaration += "RRScheduler* " + exNode.getName() + "_scheduler = new RRScheduler(\"" + exNode.getName() + "_RRSched\", 0, " + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime) + ", " + (int) Math.ceil((float) (exNode.clockRatio * Math.max(exNode.execiTime, exNode.execcTime) * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100) + " ) " + SCCR;
//TraceManager.addDev("cores " + exNode.nbOfCores);
- for (int cores = 0; cores < exNode.nbOfCores; cores++) {
- //for(int cores=0; cores<1; cores++){
- //if (tmlmapping.isAUsedHwNode(node)) {
- declaration += "CPU* " + exNode.getName() + cores + " = new SingleCoreCPU(" + exNode.getID() + ", \"" + exNode.getName() + "_" + cores + "\", " + exNode.getName() + "_scheduler" + ", ";
-
+ if (exNode.nbOfCores == 1) {
+ declaration += "CPU* " + exNode.getName() + exNode.nbOfCores + " = new SingleCoreCPU(" + exNode.getID() + ", \"" + exNode.getName() + "_" + exNode.nbOfCores + "\", "
+ + exNode.getName() + "_scheduler" + ", ";
+
+ declaration += exNode.clockRatio + ", " + exNode.execiTime + ", " + exNode.execcTime + ", " + exNode.pipelineSize + ", "
+ + exNode.taskSwitchingTime + ", " + exNode.branchingPredictionPenalty + ", " + exNode.goIdleTime + ", " + exNode.maxConsecutiveIdleCycles + ", " + exNode.byteDataSize + ")" + SCCR;
+ } else {
+ declaration += "CPU* " + exNode.getName() + exNode.nbOfCores + " = new MultiCoreCPU(" + exNode.getID() + ", \"" + exNode.getName() + "_" + exNode.nbOfCores + "\", " + exNode.getName() + "_scheduler" + ", ";
+
declaration += exNode.clockRatio + ", " + exNode.execiTime + ", " + exNode.execcTime + ", " + exNode.pipelineSize + ", " + exNode.taskSwitchingTime + ", " + exNode.branchingPredictionPenalty + ", " + exNode.goIdleTime + ", " + exNode.maxConsecutiveIdleCycles + ", " + exNode.byteDataSize + ")" + SCCR;
- if (cores != 0)
- declaration += node.getName() + cores + "->setScheduler(" + exNode.getName() + "_scheduler,false)" + SCCR;
- declaration += "addCPU(" + node.getName() + cores + ")" + SCCR;
- }
+ }
+
+ declaration += "addCPU(" + node.getName() + exNode.nbOfCores + ")" + SCCR;
+
}
if (node instanceof HwA) {
HwA hwaNode = (HwA) node;
@@ -278,16 +282,16 @@ public class TML2MappingSystemC implements IDiploSimulatorCodeGenerator {
if (node instanceof HwCPU) noOfCores = ((HwCPU) node).nbOfCores;
else noOfCores = 1;
//noOfCores=2;
- for (int cores = 0; cores < noOfCores; cores++) {
+ //for (int cores = 0; cores < noOfCores; cores++) {
String nodeName = node.getName();
- if ((node instanceof HwCPU) || (node instanceof HwA))
- nodeName += cores;
+ if (node instanceof HwCPU)
+ nodeName += ((HwCPU)node).nbOfCores;
declaration += "BusMaster* " + nodeName + "_" + link.bus.getName() + "_Master = new BusMaster(\"" + nodeName + "_" + link.bus.getName() + "_Master\", " + link.getPriority() + ", " + link.bus.pipelineSize + ", array(" + link.bus.pipelineSize;
for (int i = 0; i < link.bus.pipelineSize; i++)
declaration += ", (SchedulableCommDevice*)" + link.bus.getName() + "_" + i;
declaration += "))" + SCCR;
declaration += nodeName + "->addBusMaster(" + nodeName + "_" + link.bus.getName() + "_Master)" + SCCR;
- }
+ //}
}
}
}
--
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