diff --git a/src/ddtranslatorSoclib/AvatarRAM.java b/src/ddtranslatorSoclib/AvatarRAM.java
index 84163dd210eb42b4b5a82a91f5eea5fdef769ccf..522f4464c5fec07d74e4fc2dbf5a629dfc086e40 100755
--- a/src/ddtranslatorSoclib/AvatarRAM.java
+++ b/src/ddtranslatorSoclib/AvatarRAM.java
@@ -18,7 +18,7 @@ public class AvatarRAM extends AvatarComponent{
public int monitored;
LinkedList<AvatarChannel> channelMapped ;
- //DG 4.4. we add a field cluster_index, for the time when a cluster will have more than one RAM
+
public AvatarRAM(String _memoryName, int _index, int _dataSize, int _no_ram, int _no_cluster, int _monitored) {
memoryName = _memoryName;
index = _index;
@@ -65,6 +65,10 @@ public class AvatarRAM extends AvatarComponent{
return dataSize;
}
+ public void setDataSize(int _dataSize){
+ dataSize = _dataSize;
+ }
+
public int getMonitored(){
return monitored;
}
diff --git a/src/ddtranslatorSoclib/AvatarVgmn.java b/src/ddtranslatorSoclib/AvatarVgmn.java
index d6fc10f26b749523098d297d7a94104ee7a5b010..133511bd9794122b9706cc6c598afe73cdd8ef11 100755
--- a/src/ddtranslatorSoclib/AvatarVgmn.java
+++ b/src/ddtranslatorSoclib/AvatarVgmn.java
@@ -42,6 +42,14 @@ public class AvatarVgmn extends AvatarComponent{
return minLatency;
}
+ public void setFifoDepth(int nb){
+ fifoDepth=nb;
+ }
+
+ public void setMinLatency(int nb){
+ minLatency=nb;
+ }
+
public void setNbOfAttachedInitiators(int nb){
nbOfAttachedInitiators = nb;
}
diff --git a/src/ddtranslatorSoclib/AvatarddSpecification.java b/src/ddtranslatorSoclib/AvatarddSpecification.java
index 8d87d6000ad384d057de4749026466458dce5fd3..03bd033ef16774c4eb2f4c06c016f018c5ee3e38 100755
--- a/src/ddtranslatorSoclib/AvatarddSpecification.java
+++ b/src/ddtranslatorSoclib/AvatarddSpecification.java
@@ -105,8 +105,10 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
LinkedList<AvatarRAM> rams = new LinkedList<AvatarRAM>();
for (AvatarComponent ram : components )
{
- if (ram instanceof AvatarRAM){
- rams.add((AvatarRAM)ram);
+ if (ram instanceof AvatarRAM){
+
+ rams.add((AvatarRAM)ram);
+
}
}
return rams;
@@ -126,9 +128,10 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
LinkedList<AvatarVgmn> vgmns = new LinkedList<AvatarVgmn>();
for (AvatarComponent vgmn : components )
{
- if (vgmn instanceof AvatarVgmn)
+ if (vgmn instanceof AvatarVgmn){
vgmns.add((AvatarVgmn)vgmn);
-
+
+ }
}
return vgmns;
}
diff --git a/src/ddtranslatorSoclib/toTopCell/Declaration.java b/src/ddtranslatorSoclib/toTopCell/Declaration.java
index 5ddad6b6d35dda2652ea4fc594424c5ed0e2604e..b8851227f6e0c7ce6ffa1303fb835bb94ea2e43f 100755
--- a/src/ddtranslatorSoclib/toTopCell/Declaration.java
+++ b/src/ddtranslatorSoclib/toTopCell/Declaration.java
@@ -112,10 +112,10 @@ public class Declaration {
}
if(nb_clusters==0){
- declaration += "caba::VciLocks<vci_param> vci_locks(\"vci_locks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
}
else{
- declaration += "caba::VciLocks<vci_param> vci_locks(\"vci_locks\", IntTab(0,3), maptab);" + CR;
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,3), maptab);" + CR;
}
if(nb_clusters==0){
@@ -127,8 +127,8 @@ public class Declaration {
//target address depends on number of TTYs and RAMs
if(nb_clusters==0){
- declaration += "caba::VciRam<vci_param>mwmr_ram(\"mwmr_ram\",IntTab("+(TopCellGenerator.avatardd.getNb_target()+3+i)+"),maptab);" + CR2;
- declaration += "caba::VciRam<vci_param>mwmrd_ram(\"mwmrd_ram\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+4+i)+"),maptab);" + CR2;
+ // declaration += "caba::VciRam<vci_param>mwmr_ram(\"mwmr_ram\",IntTab("+(TopCellGenerator.avatardd.getNb_target()+3+i)+"),maptab);" + CR2;
+ // declaration += "caba::VciRam<vci_param>mwmrd_ram(\"mwmrd_ram\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+4+i)+"),maptab);" + CR2;
}
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
@@ -166,8 +166,7 @@ if(nb_clusters==0){
System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
- declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+6)+
- ");" + CR2;
+ declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
int i=0;
@@ -217,8 +216,9 @@ if(nb_clusters==0){
}
}
}
-
+
//if BUS was not last in input file, update here
+
bus.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
bus.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
}
@@ -226,8 +226,15 @@ if(nb_clusters==0){
for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
-
- declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+6)+
+ /* The user might have forgotten to specify the following, thus set default values */
+
+ if(vgmn.getMinLatency()<2)
+ vgmn.setMinLatency(10); //default value; must be > 2
+ if(vgmn.getFifoDepth()<2)
+ vgmn.setFifoDepth(8); //default value; must be > 2
+
+
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+
"," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
int i=0;
diff --git a/src/ddtranslatorSoclib/toTopCell/Deployinfo.java b/src/ddtranslatorSoclib/toTopCell/Deployinfo.java
index 63a3064ba09cbe9218525732a830957b193b529f..d7d03bc7aebfd5c86886e9dc9a288094434a23b3 100755
--- a/src/ddtranslatorSoclib/toTopCell/Deployinfo.java
+++ b/src/ddtranslatorSoclib/toTopCell/Deployinfo.java
@@ -1,12 +1,11 @@
/* This class generates the deployment info for the ldscript*/
-/* authors: v1.0 Raja Daniela GENIUS 2015 */
+/* authors: v1.0 Daniela GENIUS 2015 modified for clustered architecture 08/2016 */
-/* It requires information about the mapping of channels on memory banks*/
-/* channels and RAM segments are numbered canonically for generation, theit names are thus NOT those in the Deployment Diagram; this is done to simplify generation, as the name also appears in the main.c of the application and is generated canonically there, too (example "section_channel0") */
+/*
-/* here is an example :
+/* here is an example of an ldscript :
#define CHANNEL_0_NAME channel0
#define CHANNEL_1_NAME channel1
@@ -39,37 +38,74 @@ public class Deployinfo {
private final static String CR2 = "\n\n";
/* for the moment, this is specific to PowerPC */
-
+
public static String getDeployInfo() {
+
+ int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- int calculated_addr = 2130706432;// 0x7f000000 currently fixed for power pc
-
String deployinfo = CR;
- int i=1;
+
+ /* we will have to dimension the segments according to the number of clusters, number of RAMS etc. */
+
+ /* first, determine the "step" between segments */
+
+ int size;
+
+ /* there can be many RAMS, but then must be smaller dimensioned */
+
+ int i=0;
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- //String string_adress_start = Integer.toHexString(calculated_addr);
+
+ /* data memory always starts at 0x10000000 */
+ int address_start = 268435456;
String string_adress_start = Integer.toHexString(i*268435456);
- // if((ram.getNo_ram()==0)&&(!(ram.getChannels().isEmpty()))){
-
- //deployinfo = "#define DEPLOY_RAM" + i + "_NAME mem_ram"+ CR;
-
- // }
- // else{
- deployinfo += "#define CACHED_RAM" + ram.getNo_ram() + "_NAME cram" + ram.getNo_ram() + CR;
- //}
- deployinfo = deployinfo + "#define CACHED_RAM" + ram.getNo_ram() + "_ADDR 0x" + (string_adress_start) + CR; // attention this must be hexadecimal
- //DG 30.08.
- //int size = 65536;//ram.getDataSize();
+
+ /* segment size is either given by the user or a default value is calculated */
+ if(ram.getDataSize()==0){
+
+ if((nb_clusters<16)||(TopCellGenerator.avatardd.getAllRAM().size()<16)){
+ size = 268435456;
+
+ }
+ else {//smaller segments
+ size = 134217728;
+ } // to be refined, a la DSX
+ }
+ else{
+ size = ram.getDataSize();
+ }
+ ram.setDataSize(size);
+ //ram.setDataSize(0);
+ size = ram.getDataSize(); // this is the hardware RAM size
+
+ System.out.println("***hardware RAM size"+size);
+
+ String string_size_half = (Integer.toHexString(size/2)); //segments on this are half uram, half cram
+
+ deployinfo += "#define CACHED_RAM" + ram.getNo_ram() + "_NAME cram" + ram.getNo_ram() + CR;
+
+ deployinfo = deployinfo + "#define CACHED_RAM" + ram.getNo_ram() + "_ADDR 0x" + Integer.toHexString(address_start+i*size) + CR;
- int size = ram.getDataSize();
+// 31.08. simplifie
- String string_size = (Integer.toHexString(size/2));//half is uram, half is cram
- deployinfo = deployinfo + "#define CACHED_RAM" + ram.getNo_ram() + "_SIZE 0x"+ string_size + CR;
+ //deployinfo = deployinfo + "#define CACHED_RAM" + ram.getNo_ram() + "_ADDR 0x" + (ram.getNo_ram()+1)+ "0000000" + CR;
+
+ deployinfo = deployinfo + "#define CACHED_RAM" + ram.getNo_ram() + "_SIZE 0x"+ string_size_half + CR;
deployinfo += "#define DEPLOY_RAM" + ram.getNo_ram() + "_NAME uram" + ram.getNo_ram() + CR;
-
- deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_ADDR 0x" + (Integer.toHexString((i*268435456+2097152))) + CR; // attention this must be hexadecimal
- deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_SIZE 0x"+ string_size + CR;
+
+ int cacheability_bit= 2097152; //0x00200000
+
+ // deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_ADDR 0x" + Integer.toHexString(address_start+i*size+size/2) + CR;
+
+deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_ADDR 0x" + Integer.toHexString(address_start+i*size+size/2+cacheability_bit) + CR;
+
+// 31.08. simplifie
+
+//deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_ADDR 0x"+ (ram.getNo_ram()+1)+ "0200000" + CR;
+
+ deployinfo = deployinfo + "#define DEPLOY_RAM" + ram.getNo_ram() + "_SIZE 0x"+ (string_size_half) + CR;
+
i++;
}
return deployinfo;
@@ -89,12 +125,12 @@ public class Deployinfo {
deployinfo_map=deployinfo_map+ "} > uram"+ram.getNo_ram()+"\\"+ CR;
i++;
}
- //DG ajoute 19.05. explicit mapping of locks
+
i=0;
for (AvatarChannel channel : ram.getChannels()) {
deployinfo_map = deployinfo_map +"\n .lock"+i+" : { \\" + CR;
deployinfo_map = deployinfo_map + "*(section_lock"+i+ ")\\"+ CR;
- // deployinfo_map=deployinfo_map+ "} > vci_locks\\"+ CR;
+ // if(use_vcilocks) deployinfo_map=deployinfo_map+ "} > vci_locks\\"+ CR;
deployinfo_map=deployinfo_map+ "} > uram0\\"+ CR;//DG 27.06. no ramlocks
i++;
}
diff --git a/src/ddtranslatorSoclib/toTopCell/Header.java b/src/ddtranslatorSoclib/toTopCell/Header.java
index 3de33749da5adbf836e1ff4eaa4610aea8eb53dd..60bd683f5373eb8a12e200a64834126676d59cfb 100755
--- a/src/ddtranslatorSoclib/toTopCell/Header.java
+++ b/src/ddtranslatorSoclib/toTopCell/Header.java
@@ -18,7 +18,8 @@ int nb_clusters=5;
}
public static String getHeader() {
int with_vgsb=TopCellGenerator.avatardd.getAllBus().size();
- header = "//-------------------------------Header------------------------------------" + CR2
+
+ header = "//-------------------------------Header------------------------------------" + CR2
+ "#include <iostream>" + CR
+ "#include <cstdlib>" + CR
+ "#include <vector>" + CR
diff --git a/src/ddtranslatorSoclib/toTopCell/MappingTable.java b/src/ddtranslatorSoclib/toTopCell/MappingTable.java
index fa7eee69d3e10e8c68258b16830c97bccae84cd8..6843ab004b0d9fbce35600a52411a6110fec62a5 100755
--- a/src/ddtranslatorSoclib/toTopCell/MappingTable.java
+++ b/src/ddtranslatorSoclib/toTopCell/MappingTable.java
@@ -17,7 +17,7 @@ public class MappingTable {
public static String getMappingTable() {
int l=0;
int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
-
+ System.out.println("Number of clusters : "+ nb_clusters);
if(nb_clusters == 0){
mapping = CR2 + "//-----------------------mapping table------------------------" + CR2;
mapping = mapping + "// ppc segments" + CR2;
@@ -57,30 +57,55 @@ public class MappingTable {
mapping = mapping + "maptab.add(Segment(\"vci_rttimer\", 0xd6000000, 0x00000100, IntTab(5), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0xe0000000, 0x00001000, IntTab(6), false));" + CR2;
- /* here we have a loop over the CHANNEL segments specified in the deployment diagram and we calculate their addresses in a loop; more refined methods may be proposed later */
-
- int j=0;
-
+
+ int address_start = 268435456;
+ int j=0; int i=0;
+ int size;
//if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+ for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
+
+ if(ram.getDataSize()==0){
+
+ if((nb_clusters<16)||(TopCellGenerator.avatardd.getAllRAM().size()<16)){
+ size = 1073741824;
+ }
+ else {//smaller segments
+ size = 268435456;
+ } // to be refined, a la DSX
+ }
+ else{
+ size = ram.getDataSize();
+ }
+ ram.setDataSize(size);
+ //ram.setDataSize(0);
+ size = ram.getDataSize(); // this is the hardware RAM size
+
+ int cacheability_bit= 2097152; //0x00200000
/* Boot Ram segments 0,1,2 */
if(ram.getNo_ram() ==0){
ram.setNo_target(2);//in the following assign target number 2
//mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+(ram.getNo_target())+"), true));" + CR;
//mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, 0x00100000, IntTab("+(ram.getNo_target())+"), false));" + CR;
- mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, "+ram.getDataSize()+", IntTab("+(ram.getNo_target())+"), true));" + CR;
- mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, "+ram.getDataSize()+", IntTab("+(ram.getNo_target())+"), false));" + CR;
+
+ /* mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, "+ram.getDataSize()+", IntTab("+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, "+ram.getDataSize()+", IntTab("+(ram.getNo_target())+"), false));" + CR;*/
+
+ mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +Integer.toHexString(address_start+i*size)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*size+cacheability_bit+ram.getDataSize()/2)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), false));" + CR;
+
+
}
else{
ram.setNo_target(7+j);
//mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+(ram.getNo_target())+"), true));" + CR;
//mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, 0x00100000, IntTab("+(ram.getNo_target())+"), false));" + CR;
- mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, "+ram.getDataSize()+", IntTab("+(ram.getNo_target())+"), true));" + CR;
- mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, "+ram.getDataSize()+", IntTab("+(ram.getNo_target())+"), false));" + CR;
+ mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*size)+ ", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" + Integer.toHexString(address_start+i*size+size/2+cacheability_bit) + " , 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+(ram.getNo_target())+"), false));" + CR;
j++;
}
- }
+ i++;
+ }
int m=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
/* we calculate the target number of one or several (multi-) ttys which come after the j rams and the 7 compulsory targets */
@@ -184,7 +209,7 @@ public class MappingTable {
int CLUSTER_SIZE = 0x40000000;*/
- int SEG_RAM_BASE = 268435456;
+
int SEG_ICU_BASE = 287309824;
int SEG_ICU_SIZE = 20;
@@ -200,11 +225,22 @@ public class MappingTable {
int SEG_TTY_BASE = 337641472;
int SEG_TTY_SIZE = 16;
- int CLUSTER_SIZE = 1073741824;
+ //int CLUSTER_SIZE = 1073741824;
+ //int CLUSTER_SIZE = calculated
+
+ int CLUSTER_SIZE;
+
+ if(nb_clusters<16) {
+ CLUSTER_SIZE = 268435456;}
+ else {
+ CLUSTER_SIZE = 134217728;
+ }// to be refined, cf DSX -> dynamically adapt
+
+ /* RAM adresses always start at 0x10000000 dec 268435456*/
+
+ int SEG_RAM_BASE = 268435456;
+ int cluster = 0;
- //uint32_t ram_base = SEG_RAM_BASE + c * CLUSTER_SIZE;
-
- int cluster = 0;
// mapping += "maptab.add(Segment(\"cram0\", "+ (SEG_RAM_BASE + cluster * CLUSTER_SIZE)+", 0x"+SEG_RAM0_SIZE+", IntTab(0,10), true));" + CR;
// mapping += "maptab.add(Segment(\"uram0\", "+ (SEG_RAM_BASE+0x00200000)+", 0x"+SEG_RAM0_SIZE+", IntTab(0,11), false));" + CR;
@@ -223,14 +259,17 @@ public class MappingTable {
mapping += "maptab.add(Segment(\"dma" + cluster + "\", 0x"+ Integer.toHexString(SEG_DMA_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_DMA_SIZE)+", IntTab("+cluster +","+2+"), false));" + CR;
mapping += "maptab.add(Segment(\"timer" + cluster + "\", 0x"+ Integer.toHexString(SEG_TIM_BASE + cluster * CLUSTER_SIZE)+", 0x"+Integer.toHexString(SEG_TIM_SIZE)+", IntTab("+cluster +","+3+"), true));" + CR;
-//later we will add DMA etc.
+
}
- //currently one ram and one TTY per cluster
-
+ int cacheability_bit= 2097152; //0x00200000
+ //RAM base address is SEG_RAM_BASE + CLUSTER_NUMBER * CLUSTER_SIZE;
+
+ // this is the memory space covered by the RAMs of a cluster
+
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x"+Integer.toHexString(SEG_RAM_BASE+ ram.getNo_cluster()*CLUSTER_SIZE)+", "+Integer.toHexString(ram.getDataSize())+", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), true));" + CR;
- mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x"+Integer.toHexString(SEG_RAM_BASE + ram.getNo_cluster()*CLUSTER_SIZE+0x00200000)+", 0x"+Integer.toHexString(ram.getDataSize())+", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x"+Integer.toHexString(SEG_RAM_BASE+ ram.getNo_cluster()*CLUSTER_SIZE)+", "+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), true));" + CR;
+ mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x"+Integer.toHexString(SEG_RAM_BASE + ram.getNo_cluster()*CLUSTER_SIZE+cacheability_bit)+", 0x"+Integer.toHexString(ram.getDataSize()/2)+", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), true));" + CR;
}
int nb_ram=1; //currently 1 ram per cluster
diff --git a/src/ddtranslatorSoclib/toTopCell/NetList.java b/src/ddtranslatorSoclib/toTopCell/NetList.java
index aa723359de0ada6673f9753536123153173e1fa3..1c71a31cac3b1839b7897e1eedcf887d9abef4bd 100755
--- a/src/ddtranslatorSoclib/toTopCell/NetList.java
+++ b/src/ddtranslatorSoclib/toTopCell/NetList.java
@@ -142,7 +142,7 @@ public class NetList {
}
//MWMR RAM added transparently
- netlist = netlist +"mwmr_ram.p_clk(" + NAME_CLK + ");" + CR;
+ /* netlist = netlist +"mwmr_ram.p_clk(" + NAME_CLK + ");" + CR;
netlist = netlist +"mwmr_ram.p_resetn(" + NAME_RST + ");" + CR;
netlist = netlist +"mwmr_ram.p_vci(signal_vci_mwmr_ram);" + CR2;
netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+4)+"](signal_vci_mwmr_ram);" + CR2;
@@ -151,7 +151,7 @@ public class NetList {
netlist = netlist +"mwmrd_ram.p_clk(" + NAME_CLK + ");" + CR;
netlist = netlist +"mwmrd_ram.p_resetn(" + NAME_RST + ");" + CR;
netlist = netlist +"mwmrd_ram.p_vci(signal_vci_mwmrd_ram);" + CR2;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+5)+"](signal_vci_mwmrd_ram);" + CR2;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+5)+"](signal_vci_mwmrd_ram);" + CR2;*/
}
/* clustered version */
@@ -193,10 +193,12 @@ public class NetList {
netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
}else{ /* vgsb */
netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
}
}else{
/* cluster case */
@@ -246,7 +248,7 @@ public class NetList {
}
}
i++;
- //One ICU per cluster would be more efficient
+ //One ICU per cluster per default
no_irq_tty+=6;//if there is more than one tty, irq >5
}
@@ -294,7 +296,13 @@ public class NetList {
netlist = netlist + "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");" + CR;
netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
netlist = netlist + "vcifdtrom.end_node();" + CR2;
-
+
+ //////////////// locks
+
+ netlist = netlist + "vcilocks.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcilocks.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcilocks.p_vci(signal_vci_vcilocks);" + CR;
+
//int j;
/* netlist for connecting the monitoring infrastructure */
/* Which VCI interfaces are marked for full log, with a spy sign? */
@@ -354,8 +362,8 @@ public class NetList {
netlist += "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" + CR;
netlist += "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");" + CR;
netlist += "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");" + CR;
- netlist += "sc_trace(tf, signal_vci_mwmr_ram ,\"signal_vci_mwmr_ram\");" + CR;
- netlist += "sc_trace(tf, signal_vci_mwmrd_ram ,\"signal_vci_mwmrd_ram\");" + CR;
+ //netlist += "sc_trace(tf, signal_vci_mwmr_ram ,\"signal_vci_mwmr_ram\");" + CR;
+ //netlist += "sc_trace(tf, signal_vci_mwmrd_ram ,\"signal_vci_mwmrd_ram\");" + CR;
netlist += "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");" + CR;
netlist += "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");" + CR;
netlist += "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
diff --git a/src/ddtranslatorSoclib/toTopCell/Signal.java b/src/ddtranslatorSoclib/toTopCell/Signal.java
index efdf4f04ba733a6e9182fd491f48601ca40969f1..76dc78cec255773e91648aeaf9d306e9dae379f6 100755
--- a/src/ddtranslatorSoclib/toTopCell/Signal.java
+++ b/src/ddtranslatorSoclib/toTopCell/Signal.java
@@ -28,8 +28,8 @@ public class Signal {
signal = signal +" caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");"+ CR;
-signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
-signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
+//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
+//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccessi;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccesst;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_bdi;"+ CR;