Commit d0ec4747 authored by Ludovic Apvrille's avatar Ludovic Apvrille
Browse files

Update on test for NoC and updates in TTool

parent 00458acd
......@@ -203,6 +203,9 @@ public class TMAP2Network<E> {
- Channels must be mapped on at least one route to be taken into account
*/
public String removeAllRouterNodes() {
TraceManager.addDev("\n** Removing all routers **\n");
int i, j;
//TMLModeling<E> tmlm = new TMLModeling<>();
......@@ -281,7 +284,8 @@ public class TMAP2Network<E> {
}
}
}
// the NoC is fully mapped. Let's print it!
// The NoC is fully mapped. Let's print it!
TraceManager.addDev("\nNoc:\n" + noc.toString() + "\n\n");
......@@ -290,6 +294,7 @@ public class TMAP2Network<E> {
// then, we map to the local memory only channels between tasks on the same CPU
// Other tasks, i.e. communicating thu the NoC, are put in a special list
tmlmapping.emptyCommunicationMapping();
List<TMLChannel> channelsCommunicatingViaNoc = new ArrayList<>();
List<tmltranslator.TMLChannel> allChannels = tmlm.getChannels();
for(TMLChannel chan: allChannels) {
......@@ -302,6 +307,7 @@ public class TMAP2Network<E> {
HwNode mem = tmla.getHwNodeByName(originNode.getName() + "__mem");
if (bus != null ) tmlmapping.addCommToHwCommNode(chan, (HwCommunicationNode)bus);
if (mem != null ) tmlmapping.addCommToHwCommNode(chan, (HwCommunicationNode)mem);
} else {
channelsCommunicatingViaNoc.add(chan);
}
......
......@@ -782,10 +782,10 @@ public class TranslatedRouter<E> {
tmla.makeHwLink(busNIOUT, memNIOUT);
// We must connect this mem out to the main bridge
// To so so, we create a bus
// To do so, we create a bus
HwBus busOUTToMainBridge = new HwBus("busOUTToMainBridge" + getPositionNaming());
tmla.addHwNode(busOUTToMainBridge);
tmla.makeHwLink(busOUTToMainBridge, memNIOUT);
tmla.makeHwLink(busOUTToMainBridge, busNIOUT);
tmla.makeHwLink(busOUTToMainBridge, mainBridge);
// fake task on CPU
......
......@@ -90,6 +90,8 @@ public class DiplodocusNoCTest extends AbstractTest {
TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
syntax.checkSyntax();
assertEquals(syntax.hasErrors(), 0);
// Check if models contain the expected nb of NoCs
......
// Master clock frequency - in MHz
MASTERCLOCKFREQUENCY 200
NODE BUS Bus01
SET Bus01 byteDataSize 4
SET Bus01 pipelineSize 1
SET Bus01 arbitration 0
SET Bus01 sliceTime 10000
SET Bus01 burstSize 100
SET Bus01 clockDivider 1
NODE MEMORY Memory01
SET Memory01 byteDataSize 4
SET Memory01 clockDivider 1
NODE MEMORY Memory11
SET Memory11 byteDataSize 4
SET Memory11 clockDivider 1
NODE MEMORY Memory10
SET Memory10 byteDataSize 4
SET Memory10 clockDivider 1
NODE MEMORY Memory00
SET Memory00 byteDataSize 4
SET Memory00 clockDivider 1
NODE CPU CPU01
SET CPU01 nbOfCores 1
SET CPU01 byteDataSize 4
......@@ -20,6 +44,8 @@ NODE BUS Bus00
SET Bus00 byteDataSize 4
SET Bus00 pipelineSize 1
SET Bus00 arbitration 0
SET Bus00 sliceTime 10000
SET Bus00 burstSize 100
SET Bus00 clockDivider 1
NODE CPU CPU00
......@@ -76,20 +102,34 @@ NODE BUS Bus10
SET Bus10 byteDataSize 4
SET Bus10 pipelineSize 1
SET Bus10 arbitration 0
SET Bus10 sliceTime 10000
SET Bus10 burstSize 100
SET Bus10 clockDivider 1
NODE BUS Bus11
SET Bus11 byteDataSize 4
SET Bus11 pipelineSize 1
SET Bus11 arbitration 0
SET Bus11 sliceTime 10000
SET Bus11 burstSize 100
SET Bus11 clockDivider 1
NODE BUS Bus01
SET Bus01 byteDataSize 4
SET Bus01 pipelineSize 1
SET Bus01 arbitration 0
SET Bus01 clockDivider 1
NODE LINK link_Memory01_to_Bus01
SET link_Memory01_to_Bus01 node Memory01
SET link_Memory01_to_Bus01 bus Bus01
SET link_Memory01_to_Bus01 priority 0
NODE LINK link_Memory11_to_Bus11
SET link_Memory11_to_Bus11 node Memory11
SET link_Memory11_to_Bus11 bus Bus11
SET link_Memory11_to_Bus11 priority 0
NODE LINK link_Memory10_to_Bus10
SET link_Memory10_to_Bus10 node Memory10
SET link_Memory10_to_Bus10 bus Bus10
SET link_Memory10_to_Bus10 priority 0
NODE LINK link_Memory00_to_Bus00
SET link_Memory00_to_Bus00 node Memory00
SET link_Memory00_to_Bus00 bus Bus00
SET link_Memory00_to_Bus00 priority 0
NODE LINK link_NoC0_to_Bus01
SET link_NoC0_to_Bus01 node NoC0
SET link_NoC0_to_Bus01 bus Bus01
......
......@@ -11,12 +11,18 @@ TMLMAPPING
SET noc_2x2_3flows__FunctionReceive0_2 priority 0
MAP CPU00 noc_2x2_3flows__FunctionSend0_0
SET noc_2x2_3flows__FunctionSend0_0 priority 0
MAP CPU11 noc_2x2_3flows__FunctionReceive0_1
SET noc_2x2_3flows__FunctionReceive0_1 priority 0
MAP CPU11 noc_2x2_3flows__FunctionReceive0_0
SET noc_2x2_3flows__FunctionReceive0_0 priority 0
MAP CPU10 noc_2x2_3flows__FunctionSend0_2
SET noc_2x2_3flows__FunctionSend0_2 priority 0
MAP CPU11 noc_2x2_3flows__FunctionReceive0_1
SET noc_2x2_3flows__FunctionReceive0_1 priority 0
MAP CPU10 noc_2x2_3flows__FunctionSend0_1
SET noc_2x2_3flows__FunctionSend0_1 priority 0
MAP CPU10 noc_2x2_3flows__FunctionSend0_2
SET noc_2x2_3flows__FunctionSend0_2 priority 0
MAP Memory01 noc_2x2_3flows__tx0_1__noc_2x2_3flows__rx0_1
SET noc_2x2_3flows__tx0_1__noc_2x2_3flows__rx0_1 priority 0
MAP Memory10 noc_2x2_3flows__tx0_2__noc_2x2_3flows__rx0_2
SET noc_2x2_3flows__tx0_2__noc_2x2_3flows__rx0_2 priority 0
MAP Memory00 noc_2x2_3flows__tx0_0__noc_2x2_3flows__rx0_0
SET noc_2x2_3flows__tx0_0__noc_2x2_3flows__rx0_0 priority 0
ENDTMLMAPPING
// TML Application - FORMAT 0.1
// Application: /Users/ludovicapvrille/TTool/modeling/ISAE/noc_test_vcs_periodic.xml
// Generated: Tue Jul 23 22:14:38 CEST 2019
// TML Application - FORMAT 0.2
// Application: /Users/ludovicapvrille/TTool/modeling/test/noc_test_series.xml
// Generated: Tue May 10 18:13:22 CEST 2022
// PRAGMAS
// Channels
CHANNEL noc_2x2_3flows__tx0_0__noc_2x2_3flows__rx0_0 BRBW 4 8 OUT noc_2x2_3flows__FunctionSend0_0 IN noc_2x2_3flows__FunctionReceive0_0
......
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