diff --git a/modeling/DIPLODOCUS/SmartCardProtocol.xml b/modeling/DIPLODOCUS/SmartCardProtocol.xml
index 6f0629647a60f9902eb3cd175020138b5b7bbd2d..f1d8ba59ee4ec791c836887b54c20bd894797fb0 100755
--- a/modeling/DIPLODOCUS/SmartCardProtocol.xml
+++ b/modeling/DIPLODOCUS/SmartCardProtocol.xml
@@ -7262,8 +7262,8 @@ the smart card and the terminal
 <TGConnectingPoint num="22" id="1803" />
 <TGConnectingPoint num="23" id="1804" />
 <extraparam>
-<info stereotype="CPURRPB" nodeName="CPU1" />
-<attributes nbOfCores="1" byteDataSize="4"  schedulingPolicy="1"  sliceTime="10000"  goIdleTime="10"  maxConsecutiveIdleCycles="10"  pipelineSize="5"  taskSwitchingTime="20"  branchingPredictionPenalty="2"  cacheMiss="5" execiTime="1" execcTime="1" clockRatio="2" operation="" MECType="0" encryption="0"/>
+<info stereotype="CPUSP" nodeName="CPU1" />
+<attributes nbOfCores="1" byteDataSize="4"  schedulingPolicy="2"  sliceTime="10000"  goIdleTime="10"  maxConsecutiveIdleCycles="10"  pipelineSize="5"  taskSwitchingTime="20"  branchingPredictionPenalty="2"  cacheMiss="5" execiTime="1" execcTime="1" clockRatio="2" operation="" MECType="0" encryption="0"/>
 </extraparam>
 </COMPONENT>
 <SUBCOMPONENT type="1101" id="1780" index="9" uid="a0842fd5-3e78-483b-b8bd-0b0d8bc7e157" >
diff --git a/simulators/c++2/Makefile b/simulators/c++2/Makefile
index 884ab3bb2ea5bc3272f8f442fc756c333b471452..a1f09d922e5f9bb06c40a874a104541bfa0098f2 100755
--- a/simulators/c++2/Makefile
+++ b/simulators/c++2/Makefile
@@ -24,7 +24,7 @@ OS := $(shell uname)
 
 MODULE = run
 include Makefile.src
-SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLDelayCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/ServerHelp.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/OrderScheduler.cpp arch/ReconfigScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
+SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLDelayCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/ServerHelp.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/StrictPrioScheduler.cpp arch/RRScheduler.cpp arch/OrderScheduler.cpp arch/ReconfigScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
 
 SRCS_base_DIR = src_simulator
 SRCS_generated = .
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
index 9d353815b13162650698007901470683315be730..d9105d221908cb8e8b7c0c605daafb03c0dfd967 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
@@ -198,7 +198,8 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
         header += "#include <PropRelConstraint.h>\n#include <SeqConstraint.h>\n#include <SignalConstraint.h>\n#include <TimeMMConstraint.h>\n";
         header += "#include <TimeTConstraint.h>\n";
         header += "#include <CPU.h>\n#include <SingleCoreCPU.h>\n#include <MultiCoreCPU.h>\n#include <FPGA.h>\n#include <RRScheduler.h>\n#include "
-                + "<RRPrioScheduler.h>\n" + "#include <OrderScheduler.h>\n" + "#include <PrioScheduler.h>\n#include <Bus.h>\n";
+                + "<RRPrioScheduler.h>\n#include <StrictPrioScheduler.h>\n" + "#include <OrderScheduler.h>\n" + "#include <PrioScheduler" +
+                ".h>\n#include <Bus.h>\n";
         header += "#include <ReconfigScheduler.h>\n";
         header += "#include <Bridge.h>\n#include <Memory.h>\n#include <TMLbrbwChannel.h>\n#include <TMLnbrnbwChannel.h>\n";
         header += "#include <TMLbrnbwChannel.h>\n#include <TMLEventBChannel.h>\n#include <TMLEventFChannel.h>\n#include <TMLEventFBChannel.h>\n";
@@ -234,7 +235,15 @@ public class DiploSimulatorCodeGenerator implements IDiploSimulatorCodeGenerator
                     declaration += "RRPrioScheduler* " + schedulerInstName + " = new RRPrioScheduler(\"" + namesGen.prioSchedulerName(exNode)
                             + "\", 0," + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime) + ", "
                             + (int) Math.ceil((float) (exNode.clockRatio * Math.max(exNode.execiTime, exNode.execcTime)
-                                    * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100)
+                            * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100)
+                            + " ) " + SCCR;
+
+                } else if   (exNode.getType().equals("CPUSP")) {
+                    schedulerInstName = namesGen.prioSchedulerInstanceName(exNode);
+                    declaration += "StrictPrioScheduler* " + schedulerInstName + " = new StrictPrioScheduler(\"" + namesGen.prioSchedulerName(exNode)
+                            + "\", 0," + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime) + ", "
+                            + (int) Math.ceil((float) (exNode.clockRatio * Math.max(exNode.execiTime, exNode.execcTime)
+                            * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100)
                             + " ) " + SCCR;
                 } else {
                     // tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime
diff --git a/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java b/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
index a0815eb0e290a33f06933780b16923cbde3cbd57..47d57c1ef3e596050c24183bd947dcdab57278b8 100644
--- a/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
+++ b/src/main/java/tmltranslator/tomappingsystemc2/TML2MappingSystemC.java
@@ -192,9 +192,11 @@ public class TML2MappingSystemC implements IDiploSimulatorCodeGenerator {
                 HwCPU exNode = (HwCPU) node;
                 if (exNode.getType().equals("CPURRPB"))
                     declaration += "RRPrioScheduler* " + exNode.getName() + "_scheduler = new RRPrioScheduler(\"" + exNode.getName() + "_PrioSched" + "\",0, " + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime) + ", " + (int) Math.ceil((float) (exNode.clockRatio * Math.max(exNode.execiTime, exNode.execcTime) * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100) + " ) " + SCCR;
+                else if (exNode.getType().equals("CPUSP"))
+                    declaration += "StrictScheduler* " + exNode.getName() + "_scheduler = new StrictPrioScheduler(\"" + exNode.getName() +
+                            "_StrictPrioSched" +
+                            "\",0, " + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime) + ", " + (int) Math.ceil((float) (exNode.clockRatio * Math.max(exNode.execiTime, exNode.execcTime) * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100) + " ) " + SCCR;
                 else
-                    //tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime
-                    //declaration += "RRScheduler* " + exNode.getName() + "_scheduler = new RRScheduler(\"" + exNode.getName() + "_RRSched\", 0, 5, " + (int) Math.ceil(((float)exNode.execiTime)*(1+((float)exNode.branchingPredictionPenalty)/100)) + " ) " + SCCR;
                     declaration += "RRScheduler* " + exNode.getName() + "_scheduler = new RRScheduler(\"" + exNode.getName() + "_RRSched\", 0, " + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * exNode.sliceTime) + ", " + (int) Math.ceil((float) (exNode.clockRatio * Math.max(exNode.execiTime, exNode.execcTime) * (exNode.branchingPredictionPenalty * exNode.pipelineSize + 100 - exNode.branchingPredictionPenalty)) / 100) + " ) " + SCCR;
                 //TraceManager.addDev("cores " + exNode.nbOfCores);
                 if (exNode.nbOfCores == 1) {
@@ -212,6 +214,7 @@ public class TML2MappingSystemC implements IDiploSimulatorCodeGenerator {
                 declaration += "addCPU(" + node.getName() + exNode.nbOfCores + ")" + SCCR;
 
             }
+
             if (node instanceof HwA) {
                 HwA hwaNode = (HwA) node;
                 declaration += "RRScheduler* " + hwaNode.getName() + "_scheduler = new RRScheduler(\"" + hwaNode.getName() + "_RRSched\", 0, " + (tmlmapping.getTMLArchitecture().getMasterClockFrequency() * HwA.DEFAULT_SLICE_TIME) + ", " + (int) Math.ceil((float) (hwaNode.clockRatio * Math.max(hwaNode.execiTime, hwaNode.execcTime) * (HwA.DEFAULT_BRANCHING_PREDICTION_PENALTY * HwA.DEFAULT_PIPELINE_SIZE + 100 - HwA.DEFAULT_BRANCHING_PREDICTION_PENALTY)) / 100) + " ) " + SCCR;