From d6366e9ea409ffe8ab02a9d34ceee9d73f07b821 Mon Sep 17 00:00:00 2001
From: niusiyuan <siyuan.niu@telecom-paristech.fr>
Date: Thu, 14 Mar 2019 11:13:12 +0100
Subject: [PATCH] task division ok html no
---
.../c++2/src_simulator/arch/MultiCoreCPU.cpp | 24 ++++++++++++-------
.../c++2/src_simulator/arch/MultiCoreCPU.h | 3 ++-
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
index 917940b2d1..592168b2eb 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.cpp
@@ -60,7 +60,7 @@ MultiCoreCPU::MultiCoreCPU(ID iID,
unsigned int iChangeIdleModeCycles,
unsigned int iCyclesBeforeIdle,
unsigned int ibyteDataSize,
- unsigned int iAmountOfCore): CPU(iID, iName, iScheduler, iAmountOfCore), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle)
+ unsigned int iAmountOfCore): CPU(iID, iName, iScheduler, iAmountOfCore), /*_lastTransaction(0),*/ _masterNextTransaction(0), _timePerCycle(iTimePerCycle), coreNumber(0)
#ifdef PENALTIES_ENABLED
, _pipelineSize(iPipelineSize), _taskSwitchingCycles(iTaskSwitchingCycles),_brachingMissrate(iBranchingMissrate)
, _changeIdleModeCycles(iChangeIdleModeCycles), _cyclesBeforeIdle(iCyclesBeforeIdle)
@@ -95,7 +95,7 @@ void MultiCoreCPU::initCore(){
multiCore[i] = 0;
}
-unsigned int MultiCoreCPU::getCoreNumber(){
+/*unsigned int MultiCoreCPU::getCoreNumber(){
unsigned int i;
for( i = 0; i < amountOfCore; i++){
if(multiCore[i] == 0){
@@ -104,13 +104,15 @@ unsigned int MultiCoreCPU::getCoreNumber(){
}
}
return i;
-}
+}*/
TMLTime MultiCoreCPU::getMinEndSchedule(){
TMLTime minTime=multiCore[0];
for( TMLTime i = 1; i < multiCore.size(); i++){
- if( minTime > multiCore[i])
+ if( minTime > multiCore[i]){
minTime=multiCore[i];
+ coreNumber=i;
+ }
}
return minTime;
}
@@ -327,16 +329,20 @@ bool MultiCoreCPU::addTransaction(TMLTransaction* iTransToBeAdded){
std::cout << "CPU:addt: to be started" << std::endl;
_endSchedule=_nextTransaction->getEndTime();
////test///
- unsigned int iCoreNumber=getCoreNumber();
- multiCore[iCoreNumber]=_endSchedule;
- if (iCoreNumber != (amountOfCore -1)){
+ // unsigned int iCoreNumber=getCoreNumber();
+ unsigned static time=0;
+ multiCore[coreNumber]=_endSchedule;
+ if (time < amountOfCore -1){
_endSchedule=0;
+ _nextTransaction->setTransactCoreNumber(coreNumber);
+ ++coreNumber;
}
else {
_endSchedule=getMinEndSchedule();
- initCore();
+ _nextTransaction->setTransactCoreNumber(coreNumber);
+ //initCore();
}
- _nextTransaction->setTransactCoreNumber(iCoreNumber);
+ time++;
std::cout <<"test transaction core number !!!! "<<_nextTransaction->getTransactCoreNumber()<<std::endl;
std::cout << "set end schedule CPU: " << _endSchedule << "\n";
_simulatedTime=max(_simulatedTime,_endSchedule);
diff --git a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
index ee67b7bd9d..d52ead6eb5 100644
--- a/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
+++ b/simulators/c++2/src_simulator/arch/MultiCoreCPU.h
@@ -146,9 +146,10 @@ protected:
///1/Processor frequency
TMLTime _timePerCycle;
///test////
+ unsigned int coreNumber;
//first parameter is the core number
///second parameter is the end schedule in the core
- std::map <unsigned int, int> multiCore;
+ std::map <unsigned int, unsigned int> multiCore;
///initialization of all cores
void initCore();
///get the avaliable core
--
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