diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/metadata/my_hwa.sd
similarity index 73%
rename from MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd
rename to MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/metadata/my_hwa.sd
index dfcbdc2e048dad01e42f015fa79f863158fe305b..00ae307f8ed3751b236a2193a36f03f7b8a82e1a 100644
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/metadata/my_hwa0.sd
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/metadata/my_hwa.sd
@@ -1,13 +1,13 @@
-Module('caba:MyHWA0',
- classname = 'dsx::caba::MyHWA0',
+Module('caba:MyHWA',
+ classname = 'dsx::caba::MyHWA',
header_files = [
- "my_hwa0.h",
+ "my_hwa.h",
],
interface_files = [
],
implementation_files = [
- "my_hwa0.cpp",
+ "my_hwa.cpp",
],
ports = [
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/include/my_hwa.h
similarity index 68%
rename from MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h
rename to MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/include/my_hwa.h
index 785ede2fc51a0a70da87f81a178122b7dd8f50f4..1ca12c419c2256b59557f483f6609a1ec42f16a6 100644
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa1.h
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/include/my_hwa.h
@@ -1,5 +1,5 @@
-#ifndef _HWA1_H
-#define _HWA1_H
+#ifndef _HWA_H
+#define _HWA_H
#include <systemc>
@@ -7,13 +7,13 @@
namespace dsx { namespace caba {
-class MyHWA1
+class MyHWA
: public dsx::caba::FifoVirtualCoprocessorWrapper
{
public:
- ~MyHWA1();
- MyHWA1(sc_core::sc_module_name insname);
+ ~MyHWA();
+ MyHWA(sc_core::sc_module_name insname);
private:
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/anoc_copro_wrapper.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/src/anoc_copro_wrapper.cpp
similarity index 100%
rename from MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/anoc_copro_wrapper.cpp
rename to MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/src/anoc_copro_wrapper.cpp
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/src/my_hwa.cpp
similarity index 84%
rename from MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp
rename to MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/src/my_hwa.cpp
index b6ba89a325d62f5c2009f176d3cea9831392cfd9..06b3fc98b47ea3a5686acc25acb8803dc55b5cea 100644
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa1.cpp
+++ b/MPSoC/soclib/soclib/module/streaming_component/my_hwa/caba/source/src/my_hwa.cpp
@@ -2,15 +2,15 @@
namespace dsx { namespace caba {
-#define tmpl(...) __VA_ARGS__ MyHWA1
+#define tmpl(...) __VA_ARGS__ MyHWA
-tmpl(/**/)::~MyHWA1()
+tmpl(/**/)::~MyHWA()
{
}
//intArray(1,1) there is one element (here an integer) of size 4 OCTETs/Quentin: attention cela a change c'est un MOT dans la version VM
-tmpl(/**/)::MyHWA1(sc_core::sc_module_name insname)
+tmpl(/**/)::MyHWA(sc_core::sc_module_name insname)
:dsx::caba::FifoVirtualCoprocessorWrapper(insname, stringArray(NULL), NULL, stringArray("input", NULL), intArray(1,4))
{
}
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h
deleted file mode 100644
index 4e1d1a14edfe70bcf0d587f7fece6007271f23b0..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/include/my_hwa0.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _HWA0_H
-#define _HWA0_H
-
-#include <systemc>
-
-#include "fifo_virtual_copro_wrapper.h"
-
-namespace dsx { namespace caba {
-
-class MyHWA0
- : public dsx::caba::FifoVirtualCoprocessorWrapper
-{
-
- public:
- ~MyHWA0();
- MyHWA0(sc_core::sc_module_name insname);
-
-
- private:
- void * task_func(); // Task code
-
-};
-
-}}
-#endif
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp
deleted file mode 100644
index 20c731c9d5a4204e2ff491696edde752f4e5637b..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa0/caba/source/src/my_hwa0.cpp
+++ /dev/null
@@ -1,32 +0,0 @@
-
-namespace dsx { namespace caba {
-
-
-#define tmpl(...) __VA_ARGS__ MyHWA0
-
-tmpl(/**/)::~MyHWA0()
-{
-}
-
- //intArray(1,1) there is one element (here an integer) of size 4 OCTETs/Quentin: attention cela a change c'est un MOT dans la version VM
-tmpl(/**/)::MyHWA0(sc_core::sc_module_name insname)
- :dsx::caba::FifoVirtualCoprocessorWrapper(insname, stringArray("output", NULL), intArray(1,4), stringArray(NULL), NULL)
-{
-}
-
-tmpl(void *)::task_func() {
- struct mwmr_s *output;
-// mwmr_t output = SRL_GET_MWMR(output);
- uint32_t data;
-
- while (true) {
- for (int32_t i = 0; i < 8; i++) {
- out=i;
- mwmr_write(output, &data, 4; // Write integers 0 to 7 to output
- }
-
- }
-}
-
-}}
-
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd
deleted file mode 100644
index dfcbdc2e048dad01e42f015fa79f863158fe305b..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa0.sd
+++ /dev/null
@@ -1,25 +0,0 @@
-Module('caba:MyHWA0',
- classname = 'dsx::caba::MyHWA0',
- header_files = [
- "my_hwa0.h",
-
- ],
- interface_files = [
- ],
- implementation_files = [
- "my_hwa0.cpp",
-
- ],
- ports = [
- ],
- uses = [
- Uses('caba:fifo_virtual_copro_wrapper'),
- ],
- instance_parameters = [
- ],
- tmpl_parameters = [
- ],
- extensions = [
- ],
-)
-
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd
deleted file mode 100644
index b0b32c5d02b89461309026540679146eb791a8d9..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/metadata/my_hwa1.sd
+++ /dev/null
@@ -1,25 +0,0 @@
-Module('caba:MyHWA1',
- classname = 'dsx::caba::MyHWA1',
- header_files = [
- "my_hwa1.h",
-
- ],
- interface_files = [
- ],
- implementation_files = [
- "my_hwa1.cpp",
-
- ],
- ports = [
- ],
- uses = [
- Uses('caba:fifo_virtual_copro_wrapper'),
- ],
- instance_parameters = [
- ],
- tmpl_parameters = [
- ],
- extensions = [
- ],
-)
-
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h
deleted file mode 100644
index 4e1d1a14edfe70bcf0d587f7fece6007271f23b0..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/include/my_hwa0.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _HWA0_H
-#define _HWA0_H
-
-#include <systemc>
-
-#include "fifo_virtual_copro_wrapper.h"
-
-namespace dsx { namespace caba {
-
-class MyHWA0
- : public dsx::caba::FifoVirtualCoprocessorWrapper
-{
-
- public:
- ~MyHWA0();
- MyHWA0(sc_core::sc_module_name insname);
-
-
- private:
- void * task_func(); // Task code
-
-};
-
-}}
-#endif
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp
deleted file mode 100644
index b4c4efdd6e200e1b778cf95e66b0dc903e1cc817..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/anoc_copro_wrapper.cpp
+++ /dev/null
@@ -1,658 +0,0 @@
-/* -*- c++ -*-
- *
- * SOCLIB_LGPL_HEADER_BEGIN
- *
- * This file is part of SoCLib, GNU LGPLv2.1.
- *
- * SoCLib is free software; you can redistribute it and/or modify it
- * under the terms of the GNU Lesser General Public License as published
- * by the Free Software Foundation; version 2.1 of the License.
- *
- * SoCLib is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with SoCLib; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- * SOCLIB_LGPL_HEADER_END
- *
- *
- * Copyright (c) CEA-LETI, MINATEC, 2008
- *
- * Authors :
- *
- * History :
- *
- * Comment :
- *
- */
-
-#include "anoc_copro_wrapper.h"
-namespace soclib { namespace caba {
-using soclib::common::alloc_elems;
-using soclib::common::dealloc_elems;
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Constructor
-anoc_copro_wrapper::anoc_copro_wrapper(sc_module_name module_name_,
- t_uint16 nb_cores_,
- t_uint16 nb_fifo_in_,
- t_uint16 nb_fifo_out_,
- t_uint16 n_config_,
- t_uint16 n_status_,
- t_uint32 clk_period_) :
- sc_module(module_name_),
- p_from_MWMR(alloc_elems<FifoInput<uint32_t> >("p_from_MWMR", nb_fifo_in_)),
- p_to_MWMR(alloc_elems<FifoOutput<uint32_t> >("p_to_MWMR", nb_fifo_out_ )),
- p_config(alloc_elems<sc_in<uint32_t> >("p_config", n_config_)),
- p_status(alloc_elems<sc_out<uint32_t> >("p_status", n_status_)),
- nb_cores(nb_cores_),
- nb_fifo_in(nb_fifo_in_),
- nb_fifo_out(nb_fifo_out_),
- clk_period(clk_period_)
-{
- core_fifo_in = new t_uint16[nb_fifo_in];
- for(int i=0; i<nb_fifo_in; i++) {
- if(nb_cores>1) {
-// core_fifo_in[i] = core_fifo_in_[i];
- } else {
- core_fifo_in[i] = 0; // monocore, core_fifo_in_=NULL
- }
- }
- core_fifo_out = new t_uint16[nb_fifo_out];
- for(int i=0; i<nb_fifo_out; i++) {
- if(nb_cores>1) {
-// core_fifo_out[i] = core_fifo_out_[i];
- } else {
- core_fifo_out[i] = 0; // monocore, core_fifo_out_=NULL
- }
- }
-
- cfg_flag_core_finished = new bool [nb_cores];
- for(int i = 0; i < nb_cores; i++) {
- cfg_flag_core_finished[i]=true;
- }
-
-
- // create ni => core ports
-#ifdef TLM_TRANS_RECORD
- char port_in[80];
- char port_out[80];
- char port_debug[80];
-#endif
- char port_out_name[80];
- char port_in_name[80];
-
-#ifdef TLM_TRANS_RECORD
- sprintf(port_in,"%s_IN", basename());
- sprintf(port_out,"%s_OUT", basename());
- sprintf(port_debug,"%s_DEBUG", basename());
-#endif // TLM_TRANS_RECORD
-
- ni_exec_out = new ni_exec_out_port*[nb_cores];
- for(int i=0;i<nb_cores;i++) {
- sprintf(port_out_name,"ni_exec_out_port_%i", i);
- ni_exec_out[i] = new ni_exec_out_port((char *) port_out_name, "exec", "eoc");
- ni_exec_out[i]->put_if_bind(*this); // for the status target sub-port
- }
-
- ni_cfg_dump_out = new ni_cfg_dump_out_port("ni_cfg_dump_out_port", "cfg_dump", "dump_data");
- ni_cfg_dump_out->put_if_bind(*this); // for the status target sub-port
-
-
- t_uint16 fifo_id[nb_cores];
- for (int i=0; i<nb_cores; i++) {
- fifo_id[i]=0;
- }
- ni_input_fifo_out = new ni_data_out_port*[nb_fifo_in];
- for(int i=0;i<nb_fifo_in;i++) {
- sprintf(port_out_name,"ni_input_fifo_out_port_%i", i);
-#ifdef TLM_TRANS_RECORD
- sprintf(port_out,"%s_input_fifo_out_%i", basename(), i);
- ni_input_fifo_out[i] = new ni_data_out_port((char *) port_out_name, (char *)port_out, fifo_id[core_fifo_in[i]]);
-#else
- ni_input_fifo_out[i] = new ni_data_out_port((char *) port_out_name, fifo_id[core_fifo_in[i]]);
-#endif // TLM_TRANS_RECORD
- fifo_id[core_fifo_in[i]]++;
- ni_input_fifo_out[i]->put_if_bind(*this); // for the status target sub-port
- }
-
- // create core => ni ports
- for (int i=0; i<nb_cores; i++) {
- fifo_id[i]=0;
- }
- ni_output_fifo_in = new ni_data_in_port*[nb_fifo_out];
- for(int i=0;i<nb_fifo_out;i++) {
- sprintf(port_in_name,"ni_output_fifo_in_port_%i", i);
-#ifdef TLM_TRANS_RECORD
- sprintf(port_in,"%s_output_fifo_in_%i", basename(), i);
- ni_output_fifo_in[i] = new ni_data_in_port((char *) port_in_name, (char *)port_in, fifo_id[core_fifo_out[i]]);
-#else
- ni_output_fifo_in[i] = new ni_data_in_port((char *) port_in_name, fifo_id[core_fifo_out[i]]);
-#endif // TLM_TRANS_RECORD
- fifo_id[core_fifo_out[i]]++;
- ni_output_fifo_in[i]->put_if_bind(*this); // for the status target sub-port
- }
-
- ni_released_in = new ni_released_in_port*[nb_fifo_in];
- for(int i=0;i<nb_fifo_in;i++) {
- sprintf(port_in_name,"ni_released_in_port_%i", i);
-#ifdef TLM_TRANS_RECORD
- sprintf(port_in,"%s_released_in_%i", basename(), i);
- ni_released_in[i] = new ni_released_in_port((char *) port_in_name, (char *)port_in);
-#else
- ni_released_in[i] = new ni_released_in_port((char *) port_in_name);
-#endif // TLM_TRANS_RECORD
- ni_released_in[i]->put_if_bind(*this); // for the status target sub-port
- }
-
- ni_available_in = new ni_available_in_port*[nb_fifo_out];
- for(int i=0;i<nb_fifo_out;i++) {
- sprintf(port_in_name,"ni_available_in_port_%i", i);
-#ifdef TLM_TRANS_RECORD
- sprintf(port_in,"%s_available_in_%i", basename(), i);
- ni_available_in[i] = new ni_available_in_port((char *) port_in_name, (char *)port_in);
-#else
- ni_available_in[i] = new ni_available_in_port((char *) port_in_name);
-#endif // TLM_TRANS_RECORD
- ni_available_in[i]->put_if_bind(*this); // for the status target sub-port
- }
-
- ni_status_in = new ni_status_in_port*[nb_cores];
- for(int i=0;i<nb_cores;i++) {
- sprintf(port_in_name,"ni_status_in_port_%i", i);
-#ifdef TLM_TRANS_RECORD
- sprintf(port_in,"%s_status_in_%i", basename(), i);
- ni_status_in[i] = new ni_status_in_port((char *) port_in_name, (char *)port_in);
-#else
- ni_status_in[i] = new ni_status_in_port((char *) port_in_name);
-#endif // TLM_TRANS_RECORD
- ni_status_in[i]->put_if_bind(*this); // for the status target sub-port
- }
-
-
- /***********************************************/
- // internal programmation
-
- /***********************************************/
- // internal state variables
-
- last_status = new t_uint32[nb_cores];
- for(int i=0; i<nb_cores; i++) {
- last_status[i] = 0;
- }
-
- tab_out_data_fifo_out = new t_uint32[nb_fifo_out];
- flag_tab_out_data_fifo_out = new bool[nb_fifo_out];
- tab_available_data_fifo_out = new t_uint32[nb_fifo_out];
- for (int i = 0; i < nb_fifo_out; i++) {
- tab_out_data_fifo_out[i] = 0;
- flag_tab_out_data_fifo_out[i] = false;
- tab_available_data_fifo_out[i]=0;
- }
- tab_fifo_in_accept = new bool[nb_fifo_in];
- for (int i = 0; i < nb_fifo_in; i++) {
- // fifo accept is initialised to true: ready to accept a new value
- tab_fifo_in_accept[i] = true;
- }
-
-
- /***********************************************/
- // threads & methods
- SC_METHOD(rtl_to_tlm);
- sensitive << rtl_to_tlm_event;
- dont_initialize();
-
- SC_METHOD(tlm_to_rtl);
- sensitive << p_clk.neg();
- dont_initialize();
-
- EXPRINT(ni, 2,"anoc_copro_wrapper CREATED");
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Destructor
-anoc_copro_wrapper::~anoc_copro_wrapper() {
-
- cout << "-------------- DELETE " << name() << " -------------- " << endl;
-
-
-
- delete core_fifo_in;
- delete core_fifo_out;
- for(int i=0;i<nb_cores;i++) {
- delete ni_exec_out[i];
- }
- delete ni_exec_out;
- delete ni_cfg_dump_out;
- for(int i=0;i<nb_fifo_in;i++) {
- delete ni_input_fifo_out[i];
- }
- delete ni_input_fifo_out;
- for(int i=0;i<nb_fifo_out;i++) {
- delete ni_output_fifo_in[i];
- }
- delete ni_output_fifo_in;
- for(int i=0;i<nb_fifo_in;i++) {
- delete ni_released_in[i];
- }
- delete ni_released_in;
- for(int i=0;i<nb_fifo_out;i++) {
- delete ni_available_in[i];
- }
- delete ni_available_in;
- for(int i=0;i<nb_cores;i++) {
- delete ni_status_in[i];
- }
- delete ni_status_in;
-
-}
-
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive DUMP DATA transaction (remote call)
-void anoc_copro_wrapper::put(const ni_dump_data_transaction &transaction) {
- //Not yet implemented
-#ifdef _ANOC_COPRO_DEBUG
- printf("DUMP DATA transaction\n");
-#endif
-}
-
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive RELEASED transaction (remote call)
-void anoc_copro_wrapper::put(const ni_released_transaction &transaction) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("RELEASED transaction\n");
-#endif
- t_uint16 fifo_id = 0;
- t_uint16 source_id;
- t_uint16 core_id;
- t_uint32 size_released;
- bool fifo_ok = false;
-
- source_id = transaction.get_source_id();
- core_id = transaction.get_core_id();
- size_released = transaction.get_data();
-
- int j=0;
- for(int i=0; i<nb_fifo_in; i++) {
- if(core_fifo_in[i]==core_id) {
- if(j==source_id) {
- fifo_id = i;
- fifo_ok=true;
- }
- j++;
- }
- }
-
- if(fifo_ok) {
- EXPRINT(ni, 1,"Receive released ("<< size_released <<") from fifo: " << fifo_id);
-// tab_available_size_fifo_in[fifo_id]+=size_released;
- } else {
- EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for released from CORE " << core_id);
- exit(0);
- }
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive AVAILABLE transaction (remote call)
-void anoc_copro_wrapper::put(const ni_available_transaction &transaction) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("AVAILABLE transaction\n");
-#endif
- t_uint16 fifo_id = 0;
- t_uint16 source_id;
- t_uint16 core_id;
- t_uint32 available_data;
- bool fifo_ok = false;
-
- source_id = transaction.get_source_id();
- core_id = transaction.get_core_id();
- available_data = transaction.get_data();
-
- int j=0;
- for(int i=0; i<nb_fifo_out; i++) {
- if(core_fifo_out[i]==core_id) {
- if(j==source_id) {
- fifo_id = i;
- fifo_ok=true;
- }
- j++;
- }
- }
- if(fifo_ok) {
- EXPRINT(ni, 1,"Receive available (" << available_data << ") from fifo: " << fifo_id);
- tab_available_data_fifo_out[fifo_id] = available_data;
- } else {
- EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for avaivable from CORE " << core_id);
- exit(0);
- }
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive WRITE DATA transaction (remote call)
-void anoc_copro_wrapper::put(const ni_write_data_transaction &transaction) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("Received DATA transaction\n");
-#endif
-
- t_uint16 fifo_id = 0;
- t_uint16 source_id;
- t_uint16 core_id;
- t_uint32 data;
- bool fifo_ok = false;
-
- source_id = transaction.get_source_id();
- core_id = transaction.get_core_id();
- data = transaction.get_data();
-
- int j=0;
- for(int i=0; i<nb_fifo_out; i++) {
- if(core_fifo_out[i]==core_id) {
- if(j==source_id) {
- fifo_id = i;
- fifo_ok=true;
- }
- j++;
- }
- }
-
- if(fifo_ok) {
- EXPRINT(ni, 1,"Receive write data: " << data << " from fifo: " << fifo_id);
- tab_out_data_fifo_out[fifo_id] = data;
- flag_tab_out_data_fifo_out[fifo_id] = true;
- //Requires a data update on the RTL ports
- write_data_update = true;
- } else {
- EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for write data from CORE " << core_id);
- exit(0);
- }
-
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Write DATA ACCEPT transaction for fifo out
-void anoc_copro_wrapper::write_data_accept_fifo_out(int num_fifo) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("DATA ACCEPT transaction\n");
-#endif
- ni_accept_data_transaction accept_trans;
- ni_output_fifo_in[num_fifo]->put(&accept_trans);
-}
-
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive ACCEPT DATA transaction (remote call)
-void anoc_copro_wrapper::put(const ni_accept_data_transaction &transaction) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("ACCEPT DATA transaction\n");
-#endif
- t_uint16 source_id;
- t_uint16 fifo_id = 0;
- t_uint16 core_id;
- bool fifo_ok=false;
-
- source_id = transaction.get_source_id();
- core_id = transaction.get_core_id();
-
- int j=0;
- for(int i=0; i<nb_fifo_in; i++) {
- if(core_fifo_in[i]==core_id) {
- if(j==source_id) {
- fifo_id = i;
- fifo_ok=true;
- }
- j++;
- }
- }
-
- if(fifo_ok) {
- EXPRINT(ni, 1,"Receive accept data from fifo: " << fifo_id); //FIXPRINT
- tab_fifo_in_accept[fifo_id] = true;
- //Requires to update the accept_data (Ivan)
- accept_data_update = true;
- } else {
- EXPRINT(ni, 0,"ERROR : invalid source id " << source_id << " for accept data from CORE " << core_id );
- exit(0);
- }
-
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Write WRITE DATA transaction for fifo in
-void anoc_copro_wrapper::write_data_fifo_in(int num_fifo, t_uint32 data) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("WRITE DATA transaction\n");
-#endif
-
- ni_write_data_transaction data_trans;
- data_trans.set_data(data);
- EXPRINT(ni, 1,"Write data " << data << " in fifo_in[" << num_fifo << "]"); //FIXPRINT
- ni_input_fifo_out[num_fifo]->put(&data_trans);
-
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive STATUS transaction (remote call)
-void anoc_copro_wrapper::put(const ni_status_transaction &transaction) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("STATUS transaction\n");
-#endif
-
- t_uint16 core_id;
- core_id = transaction.get_core_id();
- if(core_id>=nb_cores) {
- EXPRINT(ni, 0,"ERROR : Invalid core id for status");
- exit(0);
- }
-
- last_status[core_id] = transaction.get_status();
- //Requires to update the status port
- status_update = true;
-
- EXPRINT(ni, 0,"New status from CORE " << core_id <<" : " << last_status[core_id]); //FIXPRINT
-
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-/// Receive EOC transaction (remote call)
-void anoc_copro_wrapper::put(const ni_eoc_transaction &transaction) {
-#ifdef _ANOC_COPRO_DEBUG
- printf("EOC transaction\n");
-#endif
-
- t_uint16 core_id;
- core_id = transaction.get_core_id();
- if(core_id>=nb_cores) {
- EXPRINT(ni, 0,"ERROR : Invalid core_id for eoc");
- exit(0);
- }
-
- EXPRINT(ni, 0,"CORE " << core_id << " has finished"); //FIXPRINT
- cfg_flag_core_finished[core_id] = true;
- //Requires to update the eoc
- eoc_update = true;
-
-}
-
-/*******************************************************************************/
-/*******************************************************************************/
-// Update the RTL signals when a TLM transcation arrive
-/// Sensitive_neg << p_clk
-void anoc_copro_wrapper::tlm_to_rtl() {
- //Output FIFOs
- //////////////
- // The Data port need to be updated ?
-// if (write_data_update == true) {
-// printf("write_data_update, %i\n",(int)flag_tab_out_data_fifo_out[0]);
-// for(int i=0; i<nb_fifo_out; i++) {
-// p_to_MWMR[i].w = flag_tab_out_data_fifo_out[i];
-// p_to_MWMR[i].data = tab_out_data_fifo_out[i];
-// }
-// //the Data is correctly updated
-// write_data_update = false;
-// }
- //Input FIFOs
- /////////////
- // The Accept port need to be updated ?
-// if (accept_data_update == true) {
-// for(int i=0; i<nb_fifo_in; i++) {
-// p_from_MWMR[i].r = tab_fifo_in_accept[i];
-// }
-// //the Data is correctly updated
-// accept_data_update = false;
-// }
- //Status port
- /////////////
- // The Accept port need to be updated ?
- if (status_update == true) {
- for (int i=0; i<nb_cores; i++) {
- p_status[i+1] = last_status[i];
- }
- status_update = false;
- }
- //EOC port
- /////////////
- if (eoc_update == true) {
- uint32_t value = 0;
- for (int i=0; i<nb_cores; i++) {
- if (cfg_flag_core_finished[i] == true) {
- value += 1 << i;
- }
- }
- p_status[0] = value;
- eoc_update = false;
- }
-
- //Core configuration
- ////////////////////
- p_core_config.r = true;
-
- //Start the rtl_to_tlm process
- rtl_to_tlm_event.notify(clk_period/4,SC_PS);
-}
-
-
-/*******************************************************************************/
-/*******************************************************************************/
-// Generate a TLM transaction when the RTL signals change
-/// Sensitive_pos << 3/4*p_clk
-void anoc_copro_wrapper::rtl_to_tlm() {
-
- //Output FIFOs
- //////////////
- //Test if a Send signal is active
- for(int i=0; i<nb_fifo_out; i++) {
- //A FIFO was ready to send data ?
- p_to_MWMR[i].w = false;
- if (flag_tab_out_data_fifo_out[i]) {
- //Chech if the accept signal is High
- if (p_to_MWMR[i].wok.read() == true) {
- //The FIFO data is correcly transfered
- p_to_MWMR[i].w = true;
- p_to_MWMR[i].data = tab_out_data_fifo_out[i];
-
- //Invalidate the send signal
- flag_tab_out_data_fifo_out[i] = false;
- //Requires to update the Data port
- write_data_update = true;
- //Send the TLM Accept transaction to the Core
- if (tab_available_data_fifo_out[i] > 1 )
- write_data_accept_fifo_out(i);
- }
- } else if (tab_available_data_fifo_out[i] > 0 ) {
- //New data can be read?
- //Send the TLM Accept transaction to the Core
- write_data_accept_fifo_out(i);
- }
- }
-
- //Input FIFOs
- /////////////
- //Test if a new Data is present on the Input FIFOs
- for(int i=0; i<nb_fifo_in; i++) {
- p_from_MWMR[i].r = tab_fifo_in_accept[i];
- if (p_from_MWMR[i].rok.read() == true) {
- //I am ready to accept this new data?
- if (tab_fifo_in_accept[i] == true) {
- //Read the data and send a TLM transcation
- p_from_MWMR[i].r = true;
- t_uint32 data = (t_uint32)p_from_MWMR[i].data.read();
- write_data_fifo_in(i, data);
- //Lower the ROK signal
- tab_fifo_in_accept[i] = false;
- //Requires a Accept RTL port update
- accept_data_update = true;
- }
- }
- }
-
- //Exec port
- ///////////////
- //RTL signals changed?
- if (exec_last != p_config[0].read()) {
- ni_exec_transaction exec_trans;
- //Test bit by bit to identify the source
- for(int i=0; i<nb_cores; i++) {
- if (((exec_last & (1<<i)) == 0) && ((p_config[0].read() & (1<<i)) == 1)) {
- //A new lot_id is ready to be executed on core 'i'
- EXPRINT(ni, 1,"CORE configuration event");
- //Get the slot_id
- t_uint16 slot_id = (t_uint16)p_config[i+1].read();
- EXPRINT(ni, 0,"CORE " << i << " execute configuration on slot id " << slot_id);
- // write exec config
- exec_trans.set_slot_id(slot_id);
- ni_exec_out[i]->put(&exec_trans);
- //The CORE is nolonger finished
- cfg_flag_core_finished[i] = false;
- //Requires a RTL signal update
- eoc_update = true;
- }
- }
- exec_last = p_config[0].read();
- }
-
- //Core config address
- /////////////////////
- if (last_address != p_config[5].read()) {
- //The address have been changed
- current_address = p_config[5].read();
- last_address = p_config[5].read();
- }
-
-
- //Core configuration
- ////////////////////
- if (p_core_config.rok.read() == true) {
- //A new configuration data is ready
- ni_cfg_transaction cfg_trans;
- t_uint32 data = p_core_config.data.read();
- cfg_trans.set_data(data);
- cfg_trans.set_address(current_address);
-#ifdef _ANOC_COPRO_DEBUG
- printf("Ivan: Config data: %.8x on address %.8x\n", data, current_address);
-#endif
- ni_cfg_dump_out->put(&cfg_trans);
- current_address++;
- }
-
-}
-}}
-
-
diff --git a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp b/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp
deleted file mode 100644
index 20c731c9d5a4204e2ff491696edde752f4e5637b..0000000000000000000000000000000000000000
--- a/MPSoC/soclib/soclib/module/streaming_component/my_hwa1/caba/source/src/my_hwa0.cpp
+++ /dev/null
@@ -1,32 +0,0 @@
-
-namespace dsx { namespace caba {
-
-
-#define tmpl(...) __VA_ARGS__ MyHWA0
-
-tmpl(/**/)::~MyHWA0()
-{
-}
-
- //intArray(1,1) there is one element (here an integer) of size 4 OCTETs/Quentin: attention cela a change c'est un MOT dans la version VM
-tmpl(/**/)::MyHWA0(sc_core::sc_module_name insname)
- :dsx::caba::FifoVirtualCoprocessorWrapper(insname, stringArray("output", NULL), intArray(1,4), stringArray(NULL), NULL)
-{
-}
-
-tmpl(void *)::task_func() {
- struct mwmr_s *output;
-// mwmr_t output = SRL_GET_MWMR(output);
- uint32_t data;
-
- while (true) {
- for (int32_t i = 0; i < 8; i++) {
- out=i;
- mwmr_write(output, &data, 4; // Write integers 0 to 7 to output
- }
-
- }
-}
-
-}}
-
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
index ffc368f4fbae54bb7321bacce4996d323947729d..b30cd441329d2284bb4e9420938c033ddea27b14 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Declaration.java
@@ -51,395 +51,537 @@ import avatartranslator.AvatarRelation;
import avatartranslator.AvatarBlock;
import avatartranslator.AvatarSignal;
import avatartranslator.AvatarSpecification;
+import myutil.TraceManager;
-public class Declaration {
+public class Declaration
+{
public static AvatarSpecification avspec;
private static String CR = "\n";
- private static String CR2 = "\n\n";
-
- public static String generateName(AvatarRelation _ar, int _index) {
- return _ar.block1.getName() + "_" + _ar.getSignal1(_index).getName() + "__" + _ar.block2.getName() + "_" + _ar.getSignal2(_index).getName();
+ private static String CR2 = "\n\n";
+
+ public static String generateName (AvatarRelation _ar, int _index)
+ {
+ return _ar.block1.getName () + "_" +
+ _ar.getSignal1 (_index).getName () + "__" +
+ _ar.block2.getName () + "_" + _ar.getSignal2 (_index).getName ();
}
-
- public static String getDeclarations(AvatarSpecification _avspec) {
- avspec =_avspec;
-
- String declaration = "//----------------------------Instantiation-------------------------------" + CR2;
-
-
- int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar().size();
-
- boolean trace_caba=true;
-
- if(nb_clusters==0){
- declaration += CR
- + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);" + CR;
- }
- else{
- declaration += CR
- + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);" + CR;
- }
- if(nb_clusters==0){
- declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);" + CR;
- }
- else{
- declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);" + CR;
- }
-
- if(nb_clusters==0){
- declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);" + CR;
-}
- else{
- declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);" + CR;
- }
-
- if(nb_clusters==0){
- declaration = declaration + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());" + CR;
- }
- else{
- declaration = declaration + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());" + CR;
- }
-
- if(nb_clusters==0){
- declaration = declaration + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);" + CR2;
- }
- else{
- declaration = declaration + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);" + CR2;
- }
-
- if(nb_clusters==0){
- declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);" + CR;
- }
- else{
- declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);" + CR;
- }
-
- int last_tty=0;
- if(nb_clusters==0){
- int i=0;
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
- declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab(" + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
- i++;
- last_tty=tty.getNo_target()+1;
- }
-
- //target address depends on number of TTYs and RAMs
-
- if(nb_clusters==0){
- // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
- // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(last_tty+3)+"), maptab);" + CR;
- }
- else{
- // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
- }
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
- if(ram.getIndex()==0){
- declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab(2), maptab);" + CR;
- }
- else{
- declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab("
- + ram.getNo_target() + "), maptab);" + CR;
- }
- }
- else{
- int i=0;
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
- declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab("+ tty.getNo_cluster()+"," + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
- i++;}
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
- declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab("+ram.getNo_cluster()+","
- + ram.getNo_target() + "), maptab);" + CR2;
- }
- if(nb_clusters==0){
- /*declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+(TopCellGenerator.avatardd.getNb_target())+"));" + CR;
- declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("+(TopCellGenerator.avatardd.getNb_target()+1)+"), \"soclib0\");" + CR;
- declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" + CR;*/
-
-declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+last_tty +"));" + CR;
- declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("+(last_tty +1)+"), \"soclib0\");" + CR;
- declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(last_tty +2)+"),\"block0.iso\", 2048);" + CR;
-
- //only non-clustered version
- int hwa_no=0;
- //int target_no = TopCellGenerator.avatardd.getNb_target();
- int target_no = (last_tty +4);//DG 5.9.
- int init_no = TopCellGenerator.avatardd.getNb_init();
- for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- // declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
-
- declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "_wrapper(\"" + copro.getCoprocName()+ "_wrapper\", maptab, IntTab("+(init_no-1)+"), IntTab("+target_no+ "),"+copro.getPlaps()+","+copro.getFifoToCoprocDepth()+","+copro.getFifoFromCoprocDepth()+","+copro.getNToCopro()+","+copro.getNFromCopro()+","+copro.getNConfig()+","+copro.getNStatus()+","+ copro.getUseLLSC()+");"+ CR2;
-//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+ public static String getDeclarations (AvatarSpecification _avspec)
+ {
+ avspec = _avspec;
-//DG 28.08.
- // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
- if(copro.getCoprocType()==0){
- declaration += "soclib::caba::VciInputEngine<vci_param>" + copro.getCoprocName()+"(\"" + copro.getCoprocName()+ "\", 1 , maptab,\"input.txt\",1024,1,8);"+ CR;
- }
- /*VciInputEngine(
- sc_core::sc_module_name insname,
- const soclib::common::IntTab &index, //???channel index
- const soclib::common::MappingTable &mt,
- const std::string &finput,
- uint32_t dext,
- uint32_t nchannels,
- uint32_t burstlength);*/
- //DG 27.04.2018 attention a la numerotation!faut il incrementer ici?
- else {
- if(copro.getCoprocType()==1)
- {
- declaration += "soclib::caba::VciOutputEngine<vci_param>"+ copro.getCoprocName()+"(\"" + copro.getCoprocName()+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"+ CR;
- /*VciOutputEngine(
- sc_core::sc_module_name insname,
- const soclib::common::IntTab &index,
- const soclib::common::MappingTable &mt,
- uint32_t advance,
- uint32_t delay,
- uint32_t size,
- const std::string &foutput,
- const std::string &fthrow);*/
- }
-
-
- else{
-declaration += "dsx::caba::MyHWA"+hwa_no+" hwa"+hwa_no+"(\"hwa"+hwa_no+"\");"+ CR2;
- hwa_no++;
- // init_no++; DG 27.04.2018
- // target_no++; DG 27.04.2018
- }
- }
- init_no++;
- target_no++;
- }
- }else{
- declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));" + CR;
- declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");" + CR;
- declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);" + CR;
-
-int hwa_no=0;
- //int target_no = TopCellGenerator.avatardd.getNb_target();
- int target_no = (last_tty +4);//DG 5.9.
- int init_no = TopCellGenerator.avatardd.getNb_init();
- for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- // declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
-
- declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "_wrapper(\"" + copro.getCoprocName()+ "_wrapper\", maptab, IntTab("+(init_no-1)+"), IntTab("+target_no+ "),"+copro.getPlaps()+","+copro.getFifoToCoprocDepth()+","+copro.getFifoFromCoprocDepth()+","+copro.getNToCopro()+","+copro.getNFromCopro()+","+copro.getNConfig()+","+copro.getNStatus()+","+ copro.getUseLLSC()+");"+ CR2;
+ String declaration =
+ "//----------------------------Instantiation-------------------------------"
+ + CR2;
-//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
-//DG 28.08.
- // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
- if(copro.getCoprocType()==0){
- declaration += "soclib::caba::VciInputEngine<vci_param>" + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", 1 , maptab,\"input.txt\",1024,1,8);"+ CR;
- }
- /*VciInputEngine(
- sc_core::sc_module_name insname,
- const soclib::common::IntTab &index, //???channel index
- const soclib::common::MappingTable &mt,
- const std::string &finput,
- uint32_t dext,
- uint32_t nchannels,
- uint32_t burstlength);*/
- //DG 27.04.2018 attention a la numerotation!faut il incrementer ici?
- else {
- if(copro.getCoprocType()==1)
- {
- declaration += "soclib::caba::VciOutputEngine<vci_param>" + copro.getCoprocName()+"(\"" + copro.getCoprocName()+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"+ CR;
- /*VciOutputEngine(
- sc_core::sc_module_name insname,
- const soclib::common::IntTab &index,
- const soclib::common::MappingTable &mt,
- uint32_t advance,
- uint32_t delay,
- uint32_t size,
- const std::string &foutput,
- const std::string &fthrow);*/
- }
-
-
- else{
-declaration += "dsx::caba::MyHWA"+hwa_no+" hwa"+hwa_no+"(\"hwa"+hwa_no+"\");"+ CR2;
-//target_no++; DG 27.04.
-//init_no++; DG 27.04.
- hwa_no++;
- }
- }
- target_no++;
- init_no++;
- }
-
- }
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
-if(nb_clusters==0){
+ boolean trace_caba = true;
- for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
-
-
-
- //declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
- // declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
+ if (nb_clusters == 0)
+ {
+ declaration += CR
+ +
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration += CR
+ +
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);"
+ + CR;
+ }
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);"
+ + CR;
+ }
- declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab,"+(3+TopCellGenerator.avatardd.getNb_init())+"," + (TopCellGenerator.avatardd.getNb_target()+3)+ ");" + CR2;//DG 17.05.2018
- int i=0;
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);"
+ + CR;
+ }
- //if BUS was not last in input file, update here
+ if (nb_clusters == 0)
+ {
+ declaration =
+ declaration +
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
+ else
+ {
+ declaration =
+ declaration +
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
- //DG 12.10. enleve
- //bus.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
- //bus.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
- }
+ if (nb_clusters == 0)
+ {
+ declaration =
+ declaration +
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);"
+ + CR2;
+ }
+ else
+ {
+ declaration =
+ declaration +
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);"
+ + CR2;
+ }
- for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
- //
- //
- /* The user might have forgotten to specify the following, thus set default values */
-
-
-
+ if (nb_clusters == 0)
+ {
+ declaration +=
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);"
+ + CR;
+ }
+ else
+ {
+ declaration +=
+ "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);"
+ + CR;
+ }
- if(vgmn.getMinLatency()<2)
- vgmn.setMinLatency(10); //default value; must be > 2
- if(vgmn.getFifoDepth()<2)
- vgmn.setFifoDepth(8); //default value; must be > 2
+ int last_tty = 0;
+ if (nb_clusters == 0)
+ {
+ int i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_target () + "), maptab, \"vci_multi_tty" +
+ i + "\", NULL);" + CR;
+ i++;
+ last_tty = tty.getNo_target () + 1;
+ }
+
+ //target address depends on number of TTYs and RAMs
+
+ if (nb_clusters == 0)
+ {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(last_tty+3)+"), maptab);" + CR;
+ }
+ else
+ {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
+ }
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ if (ram.getIndex () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" +
+ ram.getMemoryName () + "\"" +
+ ", IntTab(2), maptab);" + CR;
+ }
+ else
+ {
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" +
+ ram.getMemoryName () + "\"" + ", IntTab(" +
+ ram.getNo_target () + "), maptab);" + CR;
+ }
+ }
+ else
+ {
+ int i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+ declaration +=
+ "caba::VciMultiTty<vci_param> " + tty.getTTYName () +
+ "(\"" + tty.getTTYName () + "\", IntTab(" +
+ tty.getNo_cluster () + "," + tty.getNo_target () +
+ "), maptab, \"vci_multi_tty" + i + "\", NULL);" + CR;
+ i++;
+ }
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ declaration +=
+ "soclib::caba::VciRam<vci_param>" +
+ ram.getMemoryName () + "(\"" + ram.getMemoryName () +
+ "\"" + ", IntTab(" + ram.getNo_cluster () + "," +
+ ram.getNo_target () + "), maptab);" + CR2;
+ }
+ if (nb_clusters == 0)
+ {
+
+ declaration +=
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
+ + last_tty + "));" + CR;
+ declaration +=
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
+ + (last_tty + 1) + "), \"soclib0\");" + CR;
+ declaration +=
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
+ + (last_tty + 2) + "),\"block0.iso\", 2048);" + CR;
+
+ //non-clustered version
+ int hwa_no = 0;
+ //int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);
+ int init_no = TopCellGenerator.avatardd.getNb_init ();
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", maptab, IntTab(" + (init_no - 1) +
+ "), IntTab(" + target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+//one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
- // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
- // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, " +(3+TopCellGenerator.avatardd.getNb_init())+"," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;//DG 28.08.
+ if (copro.getCoprocType () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciInputEngine<vci_param>" +
+ copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,\"input.txt\",1024,1,8);" + CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ declaration +=
+ "soclib::caba::VciOutputEngine<vci_param>"
+ + copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"
+ + CR;
+ }
+
+
+ else
+ {
+ declaration +=
+ // "dsx::caba::MyHWA" + hwa_no + " hwa" +
+ // hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+ "dsx::caba::MyHWA(\""+copro.getCoprocName ()+ "\");" + CR2;
+
+ }
+ }
+ init_no++;
+ target_no++;
+ }
+ }
+ else
+ {
+ declaration +=
+ "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));"
+ + CR;
+ declaration +=
+ "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");"
+ + CR;
+ declaration +=
+ "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);"
+ + CR;
+
+ int hwa_no = 0;
+ //int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);
+ int init_no = TopCellGenerator.avatardd.getNb_init ();
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+
+ declaration +=
+ "caba::VciMwmrController<vci_param> " +
+ copro.getCoprocName () + "_wrapper(\"" +
+ copro.getCoprocName () +
+ "_wrapper\", maptab, IntTab(" + (init_no - 1) +
+ "), IntTab(" + target_no + ")," + copro.getPlaps () +
+ "," + copro.getFifoToCoprocDepth () + "," +
+ copro.getFifoFromCoprocDepth () + "," +
+ copro.getNToCopro () + "," + copro.getNFromCopro () +
+ "," + copro.getNConfig () + "," +
+ copro.getNStatus () + "," + copro.getUseLLSC () +
+ ");" + CR2;
+
+ //one virtual component for each hardware accellerator, info from diplodocus (not yet implemented)
+ // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
+
+ if (copro.getCoprocType () == 0)
+ {
+ declaration +=
+ "soclib::caba::VciInputEngine<vci_param>" +
+ copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,\"input.txt\",1024,1,8);" + CR;
+ }
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ declaration +=
+ "soclib::caba::VciOutputEngine<vci_param>"
+ + copro.getCoprocName () + "(\"" +
+ copro.getCoprocName () +
+ "\", 1 , maptab,1,1,1,\"output.txt\",\"throw.txt\");"
+ + CR;
+ }
+
+
+ else
+ {
+ declaration +=
+ "dsx::caba::MyHWA" + hwa_no + " hwa" +
+ hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+
+ hwa_no++;
+ }
+ }
+ target_no++;
+ init_no++;
+ }
- declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, " +(3+TopCellGenerator.avatardd.getNb_init())+"," + (TopCellGenerator.avatardd.getNb_target()+3)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;//DG 17.05.2018
+ }
- // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNbRAM()+TopCellGenerator.avatardd.getNbTTY()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+ if (nb_clusters == 0)
+ {
+
+ for (AvatarBus bus:TopCellGenerator.avatardd.
+ getAllBus ())
+ {
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+ declaration +=
+ "soclib::caba::VciVgsb<vci_param> vgsb(\"" +
+ bus.getBusName () + "\"" + " , maptab," + (3 +
+ TopCellGenerator.
+ avatardd.getNb_init
+ ()) + "," +
+ (TopCellGenerator.avatardd.getNb_target () + 3) +
+ ");" + CR2;
+ int i = 0;
+
+ }
+
+ for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
+ getAllVgmn ())
+ {
+ /* set default values */
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+
+ if (vgmn.getMinLatency () < 2)
+ vgmn.setMinLatency (10); //default value; must be > 2
+ if (vgmn.getFifoDepth () < 2)
+ vgmn.setFifoDepth (8); //default value; must be > 2
+
+ declaration +=
+ "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
+ vgmn.getVgmnName () + "\"" + " , maptab, " + (3 +
+ TopCellGenerator.
+ avatardd.
+ getNb_init
+ ()) +
+ "," + (TopCellGenerator.avatardd.getNb_target () +
+ 3) + "," + vgmn.getMinLatency () + "," +
+ vgmn.getFifoDepth () + ");" + CR2;
+ }
- //DG 12.10. enleve
- // if VGMN was not last in input file, update here
- // vgmn.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
- //vgmn.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target()+4);
+ }
+ else
+ {
- }
+ /***************************************/
+ /* clustered interconnect architecture */
+ /***************************************/
+ for (AvatarBus bus:TopCellGenerator.avatardd.
+ getAllBus ())
+ {
+
+ declaration +=
+ "soclib::caba::VciVgsb<vci_param> vgsb(\"" +
+ bus.getBusName () + "\"" + " , maptab, " +
+ +nb_clusters + "," + nb_clusters + ");" + CR2;
+
+ //if BUS was not last in input file, update here
+ int i = 0;
+ }
+
+ for (AvatarVgmn vgmn:TopCellGenerator.avatardd.
+ getAllVgmn ())
+ {
+ TraceManager.addDev ("initiators: " +
+ TopCellGenerator.avatardd.
+ getNb_init ());
+ TraceManager.addDev ("targets: " +
+ TopCellGenerator.avatardd.
+ getNb_target ());
+
+ declaration +=
+ "soclib::caba::VciVgmn<vci_param> vgmn (\"" +
+ vgmn.getVgmnName () + "\"" + " , maptab, " +
+ nb_clusters + "," + nb_clusters + "," +
+ vgmn.getMinLatency () + "," + vgmn.getFifoDepth () +
+ ");" + CR2;
+
+ }
+
+ int i = 0;
+ for (AvatarCrossbar crossbar:TopCellGenerator.avatardd.
+ getAllCrossbar
+ ())
+ {
+
+ crossbar.setClusterIndex (i);
+
+ if (crossbar.getClusterIndex () == 0)
+ {
+ crossbar.setNbOfAttachedInitiators (nb_clusters);
+ crossbar.setNbOfAttachedTargets (13);
+ }
+ else
+ {
- /* VciMwmrController(
- sc_module_name name,
- const MappingTable &mt,
- const IntTab &srcid,
- const IntTab &tgtid,
- const size_t plaps,
- const size_t fifo_to_coproc_depth,
- const size_t fifo_from_coproc_depth,
- const size_t n_to_coproc,
- const size_t n_from_coproc,
- const size_t n_config,
- const size_t n_status,
- const bool use_llsc );
- */
+ crossbar.setNbOfAttachedInitiators (1);
+ crossbar.setNbOfAttachedTargets (1);
+ }
+ TraceManager.addDev ("initiators: " +
+ crossbar.
+ getNbOfAttachedInitiators ());
+ TraceManager.addDev ("targets: " +
+ crossbar.getNbOfAttachedTargets ());
+
+ declaration +=
+ "soclib::caba::VciLocalCrossbar<vci_param> crossbar" +
+ crossbar.getClusterIndex () + "(\"" +
+ crossbar.getCrossbarName () + "\"" +
+ " , maptab, IntTab(" + crossbar.getClusterIndex () +
+ "),IntTab(" + crossbar.getClusterIndex () + "), " +
+ crossbar.getNbOfAttachedInitiators () + ", " +
+ crossbar.getNbOfAttachedTargets () + ");" + CR2;
+
+ //if CROSSBAR was not last in input file, update here
+ crossbar.
+ setNbOfAttachedInitiators (TopCellGenerator.avatardd.
+ getNb_init ());
+ crossbar.
+ setNbOfAttachedTargets (TopCellGenerator.avatardd.
+ getNb_target ());
+ i++;
+ }
+ }
+ int i = 0;
+ //monitoring CPU by logger(1)
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+
+ if (cpu.getMonitored () == 1)
+ {
+
+ declaration +=
+ "soclib::caba::VciLogger<vci_param> logger" + i +
+ "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ }
-}
-else {
+ int j = 0;
+ //monitoring RAM either by logger(1) or stats (2)
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+
+ }
+ if (ram.getMonitored () == 1)
+ {
+
+ declaration +=
+ "soclib::caba::VciLogger<vci_param> logger" + i +
+ "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ else
+ {
+ if (ram.getMonitored () == 2)
+ {
+
+ String strArray = "";
+
+ for (AvatarRelation ar:avspec.
+ getRelations
+ ())
+ {
+
+ for (i = 0; i < ar.nbOfSignals (); i++)
+ {
+
+ AvatarSignal as1 = ar.getSignal1 (i);
+ AvatarSignal as2 = ar.getSignal2 (i);
+
+ String chname = generateName (ar, i);
+ strArray =
+ strArray + "\"" + chname + "\",";
+ }
- /***************************************/
- /* clustered interconnect architecture */
- /***************************************/
+ }
-
- for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
-
- declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, "+ +nb_clusters+"," + nb_clusters + ");" + CR2;
-
- //if BUS was not last in input file, update here
- int i=0;
- }
-
- for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
-
-
-
- declaration += "soclib::caba::VciVgmn<vci_param> vgmn (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "+ nb_clusters +"," + nb_clusters +
- "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
-
- }
-
- int i=0;
- for (AvatarCrossbar crossbar : TopCellGenerator.avatardd.getAllCrossbar()) {
-
- //currently the number on initiators and targets is fixed
-
- crossbar.setClusterIndex(i);
-
- if (crossbar.getClusterIndex()==0){
- crossbar.setNbOfAttachedInitiators(nb_clusters);
- crossbar.setNbOfAttachedTargets(13);
- }
- else{
- //processor(s) and link to central interconnect are initiators
- //crossbar.setNbOfAttachedInitiators(2);
- //crossbar.setNbOfAttachedTargets(2);
- crossbar.setNbOfAttachedInitiators(1);
- crossbar.setNbOfAttachedTargets(1);
+ declaration +=
+ "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"
+ + j + "(\"mwmr_stats" + j +
+ "\",maptab, data_ldr, \"mwmr" + j +
+ ".log\",stringArray(" + strArray + "NULL));" +
+ CR2;
+ j++;
+ }
+ }
}
-
-
-
- declaration += "soclib::caba::VciLocalCrossbar<vci_param> crossbar"+crossbar.getClusterIndex()+"(\"" + crossbar.getCrossbarName() + "\"" + " , maptab, IntTab("+ crossbar.getClusterIndex()+"),IntTab("+crossbar.getClusterIndex()+"), "+crossbar.getNbOfAttachedInitiators()+", "+crossbar.getNbOfAttachedTargets()+");" + CR2;
-
- //if CROSSBAR was not last in input file, update here
- crossbar.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
- crossbar.setNbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
- i++;
- }
-}
-int i=0;
- //monitoring CPU by logger(1)
- for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
-
- if (cpu.getMonitored()==1){
-
- declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
- i++;
- }
- }
-
- int j=0;
- //monitoring RAM either by logger(1) ou stats (2)
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- if (ram.getMonitored()==0){
-
- }
- if (ram.getMonitored()==1){
-
- declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
- i++;
- }
- else{
- if (ram.getMonitored()==2){
-
- String strArray="";
-
- for(AvatarRelation ar: avspec.getRelations()) {
-
- for(i=0; i<ar.nbOfSignals() ; i++) {
-
- AvatarSignal as1=ar.getSignal1(i);
- AvatarSignal as2=ar.getSignal2(i);
-
- String chname = generateName(ar,i);
- strArray=strArray+"\""+chname+"\",";
- }
-
- }
-
-
- declaration += "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"+j+"(\"mwmr_stats" + j+"\",maptab, data_ldr, \"mwmr"+j+".log\",stringArray("+strArray+"NULL));" + CR2;
- j++;
- }
- }
- }
-
-return declaration;
- }
+ return declaration;
+ }
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
index cc528cef4eeb8e4eefd99d7ca7f89eb5da574294..5c2b98e11913c8f413b904ac5e2e307277eaa8a9 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/NetList.java
@@ -51,78 +51,129 @@ import ddtranslatorSoclib.AvatarCoproMWMR;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
-public class NetList {
+public class NetList
+{
public static final String NAME_CLK = "signal_clk";
public static final String CR = "\n";
public static final String CR2 = "\n\n";
private static final String NAME_RST = "signal_resetn";
private static boolean tracing;
- public static String getNetlist(String icn, boolean _tracing) {
- int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
- int coproc_count=0;
+ public static String getNetlist (String icn, boolean _tracing)
+ {
+ int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar ().size ();
+ int coproc_count = 0;
+
+ tracing = _tracing;
- tracing = _tracing;
-
String netlist;
- netlist = CR2 + "//------------------------------Netlist---------------------------------" + CR2;
-
- netlist = netlist + "// icu" + CR2;
- netlist = netlist + " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));" + CR2;
-
- netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
- netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
-
- netlist = netlist + " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");" + CR;
-
- netlist = netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");" + CR2;
- netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
- netlist = netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
- netlist = netlist + " {" + CR;
- netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
- netlist = netlist + " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
- netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
- netlist = netlist + " }" + CR2;
- netlist = netlist + " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR2;
-
- netlist = netlist + " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
- netlist = netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
-
- netlist = netlist + "///////////////// cpus" + CR2;
-
- netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
- netlist = netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
- netlist = netlist + " // configure het_rom" + CR;
- netlist = netlist + " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
-
- netlist = netlist + " // add cpu node to device tree" + CR;
- netlist = netlist + " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR2;
-
- netlist = netlist + "// connect cpu" + CR;
- netlist = netlist + " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);" + CR;
- if(icn=="vgmn")
- {
- netlist = netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
- }
- else{
- netlist = netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
- }
-
+ netlist =
+ CR2 +
+ "//------------------------------Netlist---------------------------------"
+ + CR2;
+
+ netlist = netlist + "// icu" + CR2;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));"
+ + CR2;
+
+ netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
+ netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");"
+ + CR;
+
+ netlist =
+ netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
+ CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");"
+ + CR2;
+ netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
+ netlist =
+ netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
+ netlist = netlist + " {" + CR;
+ netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
+ netlist =
+ netlist +
+ " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
+ netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
+ netlist = netlist + " }" + CR2;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" +
+ CR2;
+
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" +
+ CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());"
+ + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());"
+ + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist =
+ netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
+ netlist =
+ netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
+
+ netlist = netlist + "///////////////// cpus" + CR2;
+
+ netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
+ netlist =
+ netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
+ netlist = netlist + " // configure het_rom" + CR;
+ netlist =
+ netlist +
+ " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
+
+ netlist = netlist + " // add cpu node to device tree" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);"
+ + CR;
+ netlist =
+ netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+ netlist =
+ netlist +
+ " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);"
+ + CR;
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+
netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
netlist = netlist + " }" + CR;
netlist = netlist + " vcifdtrom.end_node();" + CR2;
@@ -133,442 +184,702 @@ public class NetList {
netlist = netlist + " vcisimhelper.p_clk(signal_clk);" + CR;
netlist = netlist + " vcirttimer.p_clk(signal_clk);" + CR;
- netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
netlist = netlist + " vcifdtrom.p_resetn(signal_resetn);" + CR;
netlist = netlist + " vcirom.p_resetn(signal_resetn);" + CR;
netlist = netlist + " vcisimhelper.p_resetn(signal_resetn);" + CR;
netlist = netlist + " vcirttimer.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
-
+ netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
+
netlist = netlist + " vcifdtrom.p_vci(signal_vci_vcifdtrom);" + CR;
netlist = netlist + " vcirom.p_vci(signal_vci_vcirom);" + CR;
- netlist = netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
+ netlist =
+ netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
- netlist = netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
-
- if(icn=="vgmn"){
- netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
- netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" + CR;
- netlist = netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
- netlist = netlist + " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
- netlist = netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
- netlist = netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" + CR2;
- netlist = netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
- netlist = netlist + " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
- netlist = netlist + " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
- netlist = netlist + " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
- }
- else{
- netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
- netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
- netlist = netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" + CR;
- netlist = netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
- netlist = netlist + " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
- netlist = netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
- netlist = netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" + CR2;
- netlist = netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
- netlist = netlist + " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
- netlist = netlist + " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
- netlist = netlist + " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
- }
-
- if(nb_clusters==0){
- netlist = netlist + "// RAM netlist" + CR2;
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
-
- netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
- if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ netlist =
+ netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
+
+ if (icn == "vgmn")
+ {
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
+ netlist =
+ netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist =
+ netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist =
+ netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
+ netlist =
+ netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+ else
+ {
+ netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" +
+ CR;
+ netlist =
+ netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist =
+ netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist =
+ netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" +
+ CR2;
+ netlist =
+ netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" +
+ CR2;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);"
+ + CR;
+ netlist =
+ netlist +
+ " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);"
+ + CR2;
+ }
+
+ if (nb_clusters == 0)
+ {
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ (ram.getNo_target ()) + "](signal_vci_vciram" +
+ ram.getIndex () + ");" + CR2;
+ }
}
- else{
- netlist = netlist + "vgsb.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
- }
- }
- }
+ }
/* clustered version */
- /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster*/
- else{
- int i;
- netlist = netlist + "// RAM netlist" + CR2;
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
-
- netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
- netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
- //target number for local cluster: this is set at avatardd creation
- netlist = netlist + "crossbar"+ram.getNo_cluster()+".p_to_target["+ram.getNo_target()+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
- }
-
- //one mwmr ram and one mwmrdram per cluster are added transparently
-
- /*convention for local target ids on cluster :
- channel: 0
- mwmr_ram: 1
- mwmrd_ram: 2
- locks: 3
- ram: 4
- tty: 5
- */
-
- /* for(i=0;i<nb_clusters;i++){
- netlist = netlist + "crossbar"+i+".p_to_target["+1+"](signal_vci_mwmr_ram"+i+");" + CR2;
- //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
- netlist = netlist + "crossbar"+i+".p_to_target["+2+"](signal_vci_mwmrd_ram"+i+");" + CR2;
- //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
- } */
- }
-
- if(nb_clusters==0){
- // we can have several TTYs and each is associated to the fdtrom
-
- /* if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
- //netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
- }else{ //vgsb
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
- // netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
- }*/
-
- int l=8; //number of last tty ToDo
- if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+(l)+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(l+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgmn.p_to_target["+(l+2)+"](signal_vci_bdt);" + CR;
- // netlist = netlist + "vgmn.p_to_target["+(l+3)+"](signal_vci_vcilocks);" + CR;
- int i;
- //DG 14.09.
- //int coproc_count=0;
- for(i=0;i<coproc_count;i++){
-
- netlist = netlist + "vgmn.p_to_target["+(l+4+i)+"](signal_mwmr_"+i+"_target);" + CR;
- }
- }else{ //vgsb
- netlist = netlist + "vgsb.p_to_target["+(l)+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(l+1)+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgsb.p_to_target["+(l+2)+"](signal_vci_bdt);" + CR;
- // netlist = netlist + "vgsb.p_to_target["+(l+3)+"](signal_vci_vcilocks);" + CR;
-
- //DG 14.09.
- // int coproc_count=0;
- int i;
- for(i=0;i<coproc_count;i++){
- netlist = netlist + "vgmn.p_to_target["+(l+4+i)+"](signal_mwmr_"+i+"_target);" + CR;
+ /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster */
+ else
+ {
+ int i;
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+
+ netlist =
+ netlist + ram.getMemoryName () + ".p_clk(" +
+ NAME_CLK + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () + ".p_resetn(" +
+ NAME_RST + ");" + CR;
+ netlist =
+ netlist + ram.getMemoryName () +
+ ".p_vci(signal_vci_vciram" + ram.getIndex () + ");" +
+ CR2;
+ //target number for local cluster: this is set at avatardd creation
+ netlist =
+ netlist + "crossbar" + ram.getNo_cluster () +
+ ".p_to_target[" + ram.getNo_target () +
+ "](signal_vci_vciram" + ram.getIndex () + ");" + CR2;
+ }
+
+ /*convention for local target ids on cluster :
+ channel: 0
+ mwmr_ram: 1
+ mwmrd_ram: 2
+ locks: 3
+ ram: 4
+ tty: 5
+ */
+
}
- }
-
- }else{
- /* cluster case */
- if(icn=="vgmn"){
- netlist = netlist + "vgmn.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgmn.p_to_target["+6+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgmn.p_to_target["+7+"](signal_vci_bdt);" + CR;
- }else{
- netlist = netlist + "vgsb.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vgsb.p_to_target["+6+"](signal_vci_ethernett);" + CR;
- netlist = netlist + "vgsb.p_to_target["+7+"](signal_vci_bdt);" + CR;
- }
- }
- //netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty\",\"soclib:vci_multi_tty\");" + CR2;
-
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
+
+ if (nb_clusters == 0)
+ {
+
+ int l = 8; //number of last tty
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ int i;
+
+ for (i = 0; i < coproc_count; i++)
+ {
+
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+ else
+ { //vgsb
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l) +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 1) +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + (l + 2) +
+ "](signal_vci_bdt);" + CR;
+
+ int i;
+ for (i = 0; i < coproc_count; i++)
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + (l + 4 + i) +
+ "](signal_mwmr_" + i + "_target);" + CR;
+ }
+ }
+
+ }
+ else
+ {
+ /* cluster */
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist + "vgmn.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgmn.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ else
+ {
+ netlist =
+ netlist + "vgsb.p_to_target[" + 5 +
+ "](signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 6 +
+ "](signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vgsb.p_to_target[" + 7 +
+ "](signal_vci_bdt);" + CR;
+ }
+ }
+
+ netlist =
+ netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
netlist = netlist + "vcifdtrom.end_node();;" + CR2;
netlist = netlist + "// TTY netlist" + CR2;
- int i=0;
-
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
- netlist = netlist + tty.getTTYName()+".p_clk(signal_clk);" + CR;
- netlist = netlist + tty.getTTYName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist + tty.getTTYName()+".p_vci(signal_vci_tty"+i+");" + CR2;
- int no_irq_tty=0;
- if(nb_clusters==0){
-
- if(icn=="vgmn"){
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+i+"\");" + CR2;
- netlist = netlist + "vgmn.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
- netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
- }else{
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+tty.getNo_tty()+"\");" + CR2;
- netlist = netlist + "vgsb.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
- netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
+ int i = 0;
+
+ for (AvatarTTY tty:TopCellGenerator.avatardd.getAllTTY ())
+ {
+ netlist =
+ netlist + tty.getTTYName () + ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist =
+ netlist + tty.getTTYName () + ".p_vci(signal_vci_tty" + i +
+ ");" + CR2;
+ int no_irq_tty = 0;
+ if (nb_clusters == 0)
+ {
+
+ if (icn == "vgmn")
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" + i + "\");" +
+ CR2;
+ netlist =
+ netlist + "vgmn.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
+ else
+ {
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_multi_tty" +
+ i + "\",\"soclib:vci_multi_tty" +
+ tty.getNo_tty () + "\");" + CR2;
+ netlist =
+ netlist + "vgsb.p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + i +
+ ");" + CR2;
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" + no_irq_tty +
+ "]);" + CR2;
+ }
}
- }
-
- //we have a clustered architecture: identify local crossbar
- else{
- int j;
- for(j=0;j<nb_clusters;j++){
- netlist = netlist + "crossbar"+j+".p_to_target["+tty.getNo_target()+"](signal_vci_tty"+j+");" + CR2;
- //recalculate irq addresses, 5 devices generating irq per cluster
- netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+(tty.getNo_cluster()*5)+"]);" + CR2;
- }
- }
- i++;
- //One ICU per cluster per default
- no_irq_tty+=6;//if there is more than one tty, irq >5
- }
+
+ //we have a clustered architecture: identify local crossbar
+ else
+ {
+ int j;
+ for (j = 0; j < nb_clusters; j++)
+ {
+ netlist =
+ netlist + "crossbar" + j + ".p_to_target[" +
+ tty.getNo_target () + "](signal_vci_tty" + j +
+ ");" + CR2;
+ //recalculate irq addresses, 5 devices generating irq per cluster
+ netlist =
+ netlist + tty.getTTYName () +
+ ".p_irq[0](signal_xicu_irq[" +
+ (tty.getNo_cluster () * 5) + "]);" + CR2;
+ }
+ }
+ i++;
+ //One ICU per cluster per default
+ no_irq_tty += 6; //if there is more than one tty, irq >5
+ }
//////////////// fdrom
-
- netlist = netlist + "{" + CR2;
- netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR; netlist = netlist + " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");" + CR;
- netlist = netlist + " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");" + CR;
- netlist = netlist + " vcifdtrom.end_node();" + CR;
- netlist = netlist + "}" + CR2;
+
+ netlist = netlist + "{" + CR2;
+ netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");"
+ + CR;
+ netlist =
+ netlist +
+ " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");"
+ + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR;
+ netlist = netlist + "}" + CR2;
//////////////// ethernet
- netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
- netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
- netlist = netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
+ netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
+ netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
+ netlist =
+ netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");" + CR;
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
- netlist = netlist + "vcifdtrom.end_node();" + CR;
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
//////////////// block device
- netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
- netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
- netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
+ netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
+ netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
+ netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");" + CR;
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
- netlist = netlist + "vcifdtrom.end_node();" + CR;
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
//////////////// fd access
- netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
-
- netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
- netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
- netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
- netlist = netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
- netlist = netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
-
- netlist = netlist + "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");" + CR;
- netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
- netlist = netlist + "vcifdtrom.end_node();" + CR2;
-
- //////////////// locks
-
- // netlist = netlist + "vcilocks.p_clk(signal_clk);" + CR;
- // netlist = netlist + "vcilocks.p_resetn(signal_resetn);" + CR;
- //netlist = netlist + "vcilocks.p_vci(signal_vci_vcilocks);" + CR;
-
- ////////////////MWMR controller; hypothesis 1 per coprocessor
- // if(nb_cluster == 0){
-
- i=0;int j=0;
-
-
- for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- //a coprocessor with its FIFO interface built from HWA
- /* netlist = netlist +"hwa"+i+".p_clk(signal_clk);" + CR;
- netlist = netlist +"hwa"+i+".p_resetn(signal_resetn);" + CR;
- netlist = netlist +"hwa"+i+".p_from_ctrl["+i+"](signal_fifo_"+i+"_from_ctrl);" + CR;
- netlist = netlist +"hwa"+i+".p_to_ctrl["+i+"](signal_fifo_"+i+"_to_ctrl);" + CR2;*/
-
-
- //IE and OE are special cases as they have VCI an fifo initiator interface!!!
-
- if(copro.getCoprocType()==0){
- i=0;
- netlist = netlist +copro.getCoprocName()+".p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_vci(signal_vci_IE);"+ CR;
-
- netlist = netlist +copro.getCoprocName()+".p_pktdesc[0](signal_fifo_"+j+"_"+i+"_to_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_slin(signal_fifo_"+j+"_"+i+"_from_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_slext(signal_fifo_"+j+"_"+(i+1)+"_from_ctrl);" + CR;
-
- netlist = netlist +copro.getCoprocName()+".p_running(signal_IE_from_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_status(signal_IE_to_ctrl);" + CR2;
- i=0;
+ netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
+
+ netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
+ netlist =
+ netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
+ netlist =
+ netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
+
+ netlist =
+ netlist +
+ "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");"
+ + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR2;
+
+ i = 0;
+ int j = 0;
+
+ for (AvatarCoproMWMR copro:TopCellGenerator.
+ avatardd.getAllCoproMWMR ())
+ {
+
+ //IE and OE are special cases as they have VCI an fifo initiator interface
+
+ if (copro.getCoprocType () == 0)
+ {
+ i = 0;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_IE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_pktdesc[0](signal_fifo_" + j + "_" + i +
+ "_to_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_from_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_IE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_IE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_vci(signal_vci_OE);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_desc(signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slin(signal_fifo_" + j + "_" + i + "_to_ctrl);" +
+ CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_slext(signal_fifo_" + j + "_" + (i + 1) +
+ "_to_ctrl);" + CR;
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_running(signal_OE_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_status(signal_OE_to_ctrl);" + CR2;
+ i = 0;
+ }
+ else
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ ".p_resetn(signal_resetn);" + CR;
+ netlist =
+ // netlist + "hwa" + i + ".p_from_ctrl[" + i +
+ // "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
+ netlist + copro.getCoprocName ()+ ".p_from_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR;
+ netlist =
+ // netlist + "hwa" + i + ".p_to_ctrl[" + i +
+ // "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
+ netlist + copro.getCoprocName () + ".p_to_ctrl[" + i +
+ "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR2;
+ }
+
+
+ //additional interfaces for IE and OE
+
+ if (copro.getCoprocType () == 0)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //pktdesc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_from_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_IE_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_IE_from_ctrl);" + CR; //slext
}
- else if(copro.getCoprocType()==1){
- netlist = netlist +copro.getCoprocName()+".p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_vci(signal_vci_OE);"+ CR;
-
- netlist = netlist +copro.getCoprocName()+".p_desc(signal_fifo_"+j+"_"+i+"_from_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_slin(signal_fifo_"+j+"_"+i+"_to_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_slext(signal_fifo_"+j+"_"+(i+1)+"_to_ctrl);" + CR;
-
- netlist = netlist +copro.getCoprocName()+".p_running(signal_OE_from_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_status(signal_OE_to_ctrl);" + CR2;
- i=0;
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_from_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_from_ctrl);" + CR; //desc
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_status[0](signal_OE_to_ctrl);" + CR; //running
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + i + "](signal_fifo_" + j + "_" + i + "_to_ctrl);" + CR; //status
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_to_coproc[" + (i + 1) + "](signal_fifo_" + j + "_" + (i + 1) + "_to_ctrl);" + CR; //slin
+ netlist = netlist + copro.getCoprocName () + "_wrapper.p_config[0](signal_OE_from_ctrl);" + CR; //slext
+ }
+ else
+ {
+
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_clk(signal_clk);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_resetn(signal_resetn);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_initiator(signal_mwmr_" + i +
+ "_initiator);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_vci_target(signal_mwmr_" + i +
+ "_target);" + CR2;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_from_coproc[" + i +
+ "](signal_fifo_" + j + "_" + i +
+ "_from_ctrl);" + CR;
+ netlist =
+ netlist + copro.getCoprocName () +
+ "_wrapper.p_to_coproc[" + i + "](signal_fifo_" +
+ j + "_" + i + "_to_ctrl);" + CR;
+ }
+ i++;
}
- else{ // a completer pour plusieurs fifos et signaux non-fifo
- netlist = netlist +copro.getCoprocName()+".p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName()+".p_resetn(signal_resetn);" + CR;
- netlist = netlist +"hwa"+i+".p_from_ctrl["+i+"](signal_fifo_"+j+"_"+i+"_from_ctrl);" + CR;
- netlist = netlist +"hwa"+i+".p_to_ctrl["+i+"](signal_fifo_"+j+"_"+i+"_to_ctrl);" + CR2;
+ j++;
+ coproc_count++;
+ }
+
+
+ //If there is a spy, add logger or stats to vci interface
+
+ i = 0;
+ for (AvatarCPU cpu:TopCellGenerator.avatardd.getAllCPU ())
+ {
+ int number = cpu.getNo_proc ();
+ if (cpu.getMonitored () == 1)
+ {
+ netlist = netlist + CR +
+ "logger" + i + ".p_clk(signal_clk);" + CR +
+ "logger" + i + ".p_resetn(signal_resetn);" + CR +
+ "logger" + i + ".p_vci(signal_vci_m[" + number +
+ "]);" + CR2;
+ i++;
}
- //DG 7.5. probleme avec les index i: faut faire plus general!!
-
- //MWMR controller of the HWA
-
- //additional interfaces for IE and OE
-
- if(copro.getCoprocType()==0){
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_resetn(signal_resetn);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_vci_initiator(signal_mwmr_"+i+"_initiator);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_from_coproc["+i+"](signal_fifo_"+ j+"_"+i+"_from_ctrl);" + CR;//pktdesc
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_from_coproc["+(i+1)+"](signal_fifo_"+ j+"_"+(i+1)+"_from_ctrl);" + CR;//running
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_status[0](signal_IE_to_ctrl);" + CR;//status
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_to_coproc["+i+"](signal_fifo_"+j +"_"+i+"_to_ctrl);" + CR;//slin
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_config[0](signal_IE_from_ctrl);" + CR;//slext
- }
- else{
- if(copro.getCoprocType()==1){
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_resetn(signal_resetn);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_vci_initiator(signal_mwmr_"+i+"_initiator);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_from_coproc["+i+"](signal_fifo_"+ j+"_"+i+"_from_ctrl);" + CR;//desc
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_status[0](signal_OE_to_ctrl);" + CR;//running
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_to_coproc["+i+"](signal_fifo_"+j +"_"+i+"_to_ctrl);" + CR;//status
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_to_coproc["+(i+1)+"](signal_fifo_"+j +"_"+(i+1)+"_to_ctrl);" + CR;//slin
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_config[0](signal_OE_from_ctrl);" + CR;//slext
+
+ }
+ j = 0;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.getAllRAM ())
+ {
+ if (ram.getMonitored () == 1)
+ {
+ int number = number = ram.getIndex ();
+ netlist += "logger" + i + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "logger" + i + ".p_resetn(signal_resetn);" + CR;
+ netlist +=
+ "logger" + i + ".p_vci(signal_vci_vciram" + number +
+ ");" + CR2;
+ i++;
}
- else{
- //DG currently only one fifo per direction
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_clk(signal_clk);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_resetn(signal_resetn);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_vci_initiator(signal_mwmr_"+i+"_initiator);" + CR;
- netlist = netlist + copro.getCoprocName()+"_wrapper.p_vci_target(signal_mwmr_"+i+"_target);" + CR2;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_from_coproc["+i+"](signal_fifo_"+ j+"_"+i+"_from_ctrl);" + CR;
- netlist = netlist +copro.getCoprocName() +"_wrapper.p_to_coproc["+i+"](signal_fifo_"+j +"_"+i+"_to_ctrl);" + CR;
+ else
+ {
+
+ if (ram.getMonitored () == 2)
+ {
+ int number = number = ram.getIndex ();
+ netlist +=
+ "mwmr_stats" + j + ".p_clk(signal_clk);" + CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_resetn(signal_resetn);" +
+ CR;
+ netlist +=
+ "mwmr_stats" + j + ".p_vci(signal_vci_vciram" +
+ number + ");" + CR2;
+ j++;
+ }
}
- i++;
- }
- j++;
- coproc_count++;
- }
-
-
- //If there is a spy, add logger or stats to vci interface
-
- i=0;
- for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
- int number = cpu.getNo_proc();
- if(cpu.getMonitored()==1){
- netlist=netlist+CR+
- "logger"+i+".p_clk(signal_clk);" +CR+
- "logger"+i+".p_resetn(signal_resetn);" +CR+
- "logger"+i+".p_vci(signal_vci_m["+number+"]);" +CR2;
- i++;
- }
-
- }
- j=0;
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- if (ram.getMonitored()==1){
- int number = number = ram.getIndex();
- netlist += "logger"+i+".p_clk(signal_clk);" + CR;
- netlist += "logger"+i+".p_resetn(signal_resetn);" + CR;
- netlist += "logger"+i+".p_vci(signal_vci_vciram"+number+");" + CR2;
- i++;
- }
- else{
-
- if (ram.getMonitored()==2){
- int number = number = ram.getIndex();
- netlist += "mwmr_stats"+j+".p_clk(signal_clk);" + CR;
- netlist += "mwmr_stats"+j+".p_resetn(signal_resetn);" + CR;
- netlist += "mwmr_stats"+j+".p_vci(signal_vci_vciram"+number+");" + CR2;
- j++;
- }
- }
- }
-
- //if (with_hw_accellerator>0){
-
- int p=0;
- //for testing: vci_synthetic_initiator.h and vci_synthetic_target.h
- //for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
- /* netlist += "mwmr"+HWAccelerator.getNo()+".p_clk(signal_clk);" + CR;
- netlist += "mwmr"+HWAccelerator.getNo()+".p_resetn(signal_resetn);" + CR;
- netlist += "mwmr"+HWAccelerator.getNo()+".p_vci_initiator(signal_mwmr"+HWAccelerator.getNo()+"_initiator);" + CR;
- netlist += " mwmr"+HWAccelerator.getNo()+".p_vci_target(signal_mwmr"+HWAccelerator.getNo()+"_target);" + CR;
- netlist += " mwmr"+HWAccelerator.getNo()+".p_from_coproc["+HWAccelerator.getNo()+"](signal_fifo_to_ctrl);" + CR;
- netlist += " mwmr"+HWAccelerator.getNo()+".p_to_coproc["+HWAccelerator.getNo()+"](signal_fifo_from_ctrl);" + CR;*/
-
- /* netlist += "mwmr"+p+".p_clk(signal_clk);" + CR;
- netlist += "mwmr"+p+".p_resetn(signal_resetn);" + CR;
- netlist += "mwmr"+p+".p_vci_initiator(signal_mwmr"+p+"_initiator);" + CR;
- netlist += " mwmr"+p+".p_vci_target(signal_mwmr"+p+"_target);" + CR;
- netlist += " mwmr"+p+".p_from_coproc["+p+"](signal_fifo_"+p+"_to_ctrl);" + CR;
- netlist += " mwmr"+p+".p_to_coproc["+p+"](signal_fifo_"+p+"_from_ctrl);" + CR;
- } */
-// }
-
+ }
+
+
+ int p = 0;
+
//generate trace file if marked trace option
-
- if(tracing){
- netlist += "sc_trace_file *tf;" + CR;
- netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
- netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
- netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
-
- netlist += "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");" + CR;
- netlist += "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");" + CR;
- netlist += "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");" + CR;
- netlist += "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
- netlist += "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
- netlist += "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");" + CR;
- netlist += "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");" + CR;
-
- for(i=0;i<TopCellGenerator.avatardd.getNb_init();i++){
- netlist += "sc_trace(tf,signal_vci_m["+ i +"] ,\"signal_vci_m["+ i +"]\");" + CR;
- }
-
- i=0;
- for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
-
- netlist += "sc_trace(tf,signal_vci_tty"+tty.getNo_tty()+",\"TTY"+tty.getNo_tty()+"\");" + CR;
- netlist += "sc_trace(tf,signal_xicu_irq["+ i +"] ,\"signal_xicu_irq["+ i +"]\");" + CR;
- i++;
- }
-
- netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
- netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
- netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
-
- for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
- if (ram.getMonitored()==0){
- netlist += "sc_trace(tf,signal_vci_vciram"+ram.getIndex()+",\"Memory"+ram.getIndex()+"\");" + CR;
- }
- }
- }
- netlist = netlist + " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
- netlist = netlist + " signal_resetn = false;" + CR;
- netlist = netlist + " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
- netlist = netlist + " signal_resetn = true;" + CR;
- netlist = netlist + " sc_core::sc_start();" + CR;
- if(tracing){
- netlist += "sc_close_vcd_trace_file(tf);" + CR;
- }
- netlist = netlist + CR + " return EXIT_SUCCESS;"+ CR;
- netlist = netlist +"}" + CR;
- return netlist;
+
+ if (tracing)
+ {
+ netlist += "sc_trace_file *tf;" + CR;
+ netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
+ netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
+ netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
+
+ netlist +=
+ "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" +
+ CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
+ netlist +=
+ "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");"
+ + CR;
+ netlist +=
+ "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");"
+ + CR;
+
+ for (i = 0; i < TopCellGenerator.avatardd.getNb_init (); i++)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_m[" + i +
+ "] ,\"signal_vci_m[" + i + "]\");" + CR;
+ }
+
+ i = 0;
+ for (AvatarTTY tty:TopCellGenerator.avatardd.
+ getAllTTY ())
+ {
+
+ netlist +=
+ "sc_trace(tf,signal_vci_tty" + tty.getNo_tty () +
+ ",\"TTY" + tty.getNo_tty () + "\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ i++;
+ }
+
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+ netlist +=
+ "sc_trace(tf,signal_xicu_irq[" + i +
+ "] ,\"signal_xicu_irq[" + i + "]\");" + CR;
+
+ for (AvatarRAM ram:TopCellGenerator.avatardd.
+ getAllRAM ())
+ {
+ if (ram.getMonitored () == 0)
+ {
+ netlist +=
+ "sc_trace(tf,signal_vci_vciram" +
+ ram.getIndex () + ",\"Memory" +
+ ram.getIndex () + "\");" + CR;
+ }
+ }
+ }
+ netlist =
+ netlist +
+ " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = false;" + CR;
+ netlist =
+ netlist +
+ " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = true;" + CR;
+ netlist = netlist + " sc_core::sc_start();" + CR;
+ if (tracing)
+ {
+ netlist += "sc_close_vcd_trace_file(tf);" + CR;
+ }
+ netlist = netlist + CR + " return EXIT_SUCCESS;" + CR;
+ netlist = netlist + "}" + CR;
+ return netlist;
}
}
diff --git a/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java b/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
index 2274f78126107b403fd315f98d62f2a4068db14d..c384202c6ca94816f16a63057fc4484dc43d265b 100755
--- a/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
+++ b/src/main/java/ddtranslatorSoclib/toTopCell/Platforminfo.java
@@ -49,93 +49,116 @@
package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.*;
-public class Platforminfo {
+public class Platforminfo
+{
private final static String CR = "\n";
private final static String CR2 = "\n\n";
-
- public static String getPlatformInfo() {
+
+ public static String getPlatformInfo ()
+ {
//determine if the platform is vgsb or vgmn based (mutually exclusive)
- int with_vgsb=TopCellGenerator.avatardd.getAllBus().size();
- int nb_hwa=TopCellGenerator.avatardd.getAllCoproMWMR().size();
-
- //bus can be other than VGSB (CAN...), for the moment restricted to VGSB
- String platforminfo = CR;
- platforminfo +="use = ["+CR
- // +"Uses('caba:vci_locks'),"+CR
- +"Uses('caba:vci_ram'),"+CR
- +"Uses('caba:vci_fdt_rom'),"+CR
- +"Uses('caba:vci_heterogeneous_rom'),"+CR
- +"Uses('caba:vci_multi_tty'),"+CR
- +"Uses('caba:vci_xicu'),"+CR
- +"Uses('caba:vci_block_device'),"+CR
- +"Uses('caba:vci_ethernet'),"+CR
- +"Uses('caba:vci_rttimer'),"+CR
- +"Uses('caba:vci_fd_access'),"+CR
- +"Uses('caba:vci_simhelper'),"+CR;
-
- if(with_vgsb>0){
- platforminfo+="Uses('caba:vci_vgsb'),"+CR;
- }
- else {
- platforminfo+="Uses('caba:vci_vgmn'),"+CR;
- }
+ int with_vgsb = TopCellGenerator.avatardd.getAllBus ().size ();
+ int nb_hwa = TopCellGenerator.avatardd.getAllCoproMWMR ().size ();
+
+ //bus can be other than VGSB (CAN...), for the moment restricted to VGSB
+ String platforminfo = CR;
+ platforminfo += "use = [" + CR
+ // +"Uses('caba:vci_locks'),"+CR
+ + "Uses('caba:vci_ram')," + CR
+ + "Uses('caba:vci_fdt_rom')," + CR
+ + "Uses('caba:vci_heterogeneous_rom')," + CR
+ + "Uses('caba:vci_multi_tty')," + CR
+ + "Uses('caba:vci_xicu')," + CR
+ + "Uses('caba:vci_block_device')," + CR
+ + "Uses('caba:vci_ethernet')," + CR
+ + "Uses('caba:vci_rttimer')," + CR
+ + "Uses('caba:vci_fd_access')," + CR
+ + "Uses('caba:vci_simhelper')," + CR;
+
+ if (with_vgsb > 0)
+ {
+ platforminfo += "Uses('caba:vci_vgsb')," + CR;
+ }
+ else
+ {
+ platforminfo += "Uses('caba:vci_vgmn')," + CR;
+ }
//DG 23.08. added virtual coprocessor
- platforminfo+="Uses('caba:vci_mwmr_stats'),"+CR
- +"Uses('caba:vci_logger'),"+CR
- +"Uses('caba:vci_local_crossbar'),"+CR
- +"Uses('caba:fifo_virtual_copro_wrapper'),"+CR;
-
-for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
- if(copro.getCoprocType()==0){
- platforminfo+="Uses('caba:vci_input_engine'),"+CR
- +"Uses('common:papr_slot'),"+CR
- +"Uses('caba:generic_fifo'),"+CR
- +"Uses('common:network_io'),"+CR;
- nb_hwa--;
+ platforminfo += "Uses('caba:vci_mwmr_stats')," + CR
+ + "Uses('caba:vci_logger')," + CR
+ + "Uses('caba:vci_local_crossbar')," + CR
+ + "Uses('caba:fifo_virtual_copro_wrapper')," + CR;
+
+ int hwa=1; // at least one HWA present
+
+ for (AvatarCoproMWMR copro:TopCellGenerator.avatardd.
+ getAllCoproMWMR ())
+ {
+ if (copro.getCoprocType () == 0)
+ {
+ platforminfo += "Uses('caba:vci_input_engine')," + CR
+ + "Uses('common:papr_slot')," + CR
+ + "Uses('caba:generic_fifo')," + CR
+ + "Uses('common:network_io')," + CR;
+
+ }
+
+ else
+ {
+ if (copro.getCoprocType () == 1)
+ {
+ platforminfo +=
+ "Uses('caba:vci_output_engine')," + CR;
+
+ }
+
+
+ else
+ {
+ int i;
+ for (i = 0; i < nb_hwa; i++)
+ {if (hwa>0){
+ platforminfo +=
+ "Uses('caba:my_hwa')," + CR;
+ hwa=0; }
+ }
+ }
+ }
}
-
- else {
- if(copro.getCoprocType()==1)
- {
- platforminfo+="Uses('caba:vci_output_engine'),"+CR ; nb_hwa--;
- }
-
-
- else{int i;
- for(i=0;i<nb_hwa;i++){
- platforminfo+="Uses('caba:my_hwa"+i+"'),"+CR;
- }
- }
- }
-}
-
- platforminfo+="Uses('common:elf_file_loader'),"+CR
- +"Uses('common:plain_file_loader'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:arm'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32eb'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32el'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:niosII'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:lm32'),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=8),"+CR
- +"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=2),"+CR
- +" ]"+CR2
-+"todo = Platform('caba', 'top.cc',"+CR
-+" uses=use,"+CR
-+" cell_size = 4,"+CR
-+" plen_size = 9,"+CR
-+" addr_size = 32,"+CR
-+" rerror_size = 1,"+CR
-+" clen_size = 1,"+CR
-+" rflag_size = 1,"+CR
-+" srcid_size = 8,"+CR
-+" pktid_size = 1,"+CR
-+" trdid_size = 1,"+CR
-+" wrplen_size = 1"+CR
-+")"+CR2;
-
-return platforminfo;
+
+ platforminfo += "Uses('common:elf_file_loader')," + CR
+ + "Uses('common:plain_file_loader')," + CR
+ +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:arm'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32eb'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32el'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:niosII'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:lm32'),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=8),"
+ + CR +
+ "Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:sparcv8', NWIN=2),"
+ + CR + " ]" + CR2 + "todo = Platform('caba', 'top.cc'," + CR +
+ " uses=use," + CR + " cell_size = 4," + CR +
+ " plen_size = 9," + CR + " addr_size = 32," +
+ CR + " rerror_size = 1," + CR +
+ " clen_size = 1," + CR +
+ " rflag_size = 1," + CR +
+ " srcid_size = 8," +
+ CR +
+ " pktid_size = 1,"
+ + CR +
+ " trdid_size = 1,"
+ + CR + " wrplen_size = 1" + CR + ")" + CR2;
+
+ return platforminfo;
}
}