From e3d356368d1d3a9ca1a0c5ed3a96963a284b4aa6 Mon Sep 17 00:00:00 2001
From: Etudiant Master SESI <irina.lee@etu.upmc.fr>
Date: Sat, 19 May 2018 11:46:29 +0200
Subject: [PATCH] delete het trans add syscams trans
---
.../systemCAMStranslator/CAMSBlocks.java | 152 ------
.../SysCAMSSpecification.java | 150 ++++++
.../syscamstranslator/SysCAMSTBlockDE.java | 84 +++
.../syscamstranslator/SysCAMSTBlockTDF.java | 105 ++++
.../syscamstranslator/SysCAMSTCluster.java | 75 +++
.../syscamstranslator/SysCAMSTComponent.java | 58 ++
.../SysCAMSTConnectingPoint.java} | 54 +-
.../SysCAMSTConnector.java} | 80 +--
.../SysCAMSTPortConverter.java | 102 ++++
.../syscamstranslator/SysCAMSTPortDE.java | 112 ++++
.../syscamstranslator/SysCAMSTPortTDF.java | 112 ++++
.../syscamstranslator/toSysCAMS/Code.java | 169 ++++++
.../syscamstranslator/toSysCAMS/Corps.java | 159 ++++++
.../toSysCAMS/Declaration.java | 395 ++++++++++++++
.../syscamstranslator/toSysCAMS/Header.java | 97 ++++
.../syscamstranslator/toSysCAMS/Loader.java | 148 +++++
.../syscamstranslator/toSysCAMS/NetList.java | 508 ++++++++++++++++++
.../toSysCAMS/PrimitiveCode.java | 96 ++++
.../syscamstranslator/toSysCAMS/Signal.java | 163 ++++++
.../toSysCAMS/Simulation.java | 74 +++
.../toSysCAMS/TopCellGenerator.java | 154 ++++++
21 files changed, 2802 insertions(+), 245 deletions(-)
delete mode 100755 src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSBlocks.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSSpecification.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSTBlockDE.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSTBlockTDF.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSTCluster.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSTComponent.java
rename src/main/java/{heterogeneoustranslator/systemCAMStranslator/CAMSConnection.java => syscamstranslator/SysCAMSTConnectingPoint.java} (73%)
mode change 100755 => 100644
rename src/main/java/{heterogeneoustranslator/systemCAMStranslator/CAMSSignal.java => syscamstranslator/SysCAMSTConnector.java} (56%)
mode change 100755 => 100644
create mode 100644 src/main/java/syscamstranslator/SysCAMSTPortConverter.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSTPortDE.java
create mode 100644 src/main/java/syscamstranslator/SysCAMSTPortTDF.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Code.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Corps.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Declaration.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Header.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Loader.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/NetList.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/PrimitiveCode.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Signal.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/Simulation.java
create mode 100644 src/main/java/syscamstranslator/toSysCAMS/TopCellGenerator.java
diff --git a/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSBlocks.java b/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSBlocks.java
deleted file mode 100755
index ad65f43794..0000000000
--- a/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSBlocks.java
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
- *
- * ludovic.apvrille AT enst.fr
- *
- * This software is a computer program whose purpose is to allow the
- * edition of TURTLE analysis, design and deployment diagrams, to
- * allow the generation of RT-LOTOS or Java code from this diagram,
- * and at last to allow the analysis of formal validation traces
- * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
- * from INRIA Rhone-Alpes.
- *
- * This software is governed by the CeCILL license under French law and
- * abiding by the rules of distribution of free software. You can use,
- * modify and/ or redistribute the software under the terms of the CeCILL
- * license as circulated by CEA, CNRS and INRIA at the following URL
- * "http://www.cecill.info".
- *
- * As a counterpart to the access to the source code and rights to copy,
- * modify and redistribute granted by the license, users are provided only
- * with a limited warranty and the software's author, the holder of the
- * economic rights, and the successive licensors have only limited
- * liability.
- *
- * In this respect, the user's attention is drawn to the risks associated
- * with loading, using, modifying and/or developing or reproducing the
- * software by the user in light of its specific status of free software,
- * that may mean that it is complicated to manipulate, and that also
- * therefore means that it is reserved for developers and experienced
- * professionals having in-depth computer knowledge. Users are therefore
- * encouraged to load and test the software's suitability as regards their
- * requirements in conditions enabling the security of their systems and/or
- * data to be ensured and, more generally, to use and operate it in the
- * same conditions as regards security.
- *
- * The fact that you are presently reading this means that you have had
- * knowledge of the CeCILL license and that you accept its terms.
- */
-
-
-
-
-package heterogeneoustranslator.systemCAMStranslator;
-
-import javax.swing.*;
-import java.awt.*;
-import java.util.LinkedList;
-import java.util.Vector;
-import ui.*;
-
-/**
-* Class CAMSBlocks
-* Simulation Block for SystemC-AMS Diagrams
-* Creation: 28/08/2017
-* @version 1.0 28/08/2017
-* @author Côme DEMARIGNY
- */
-
-public class CAMSBlocks{
-
- private String name;
- private int nbOfIn;
- private int nbOfOut;
- private int nbOfHybridIn;
- private int nbOfHybridOut;
- private LinkedList<TAttribute> myAttributes;
- private LinkedList<CAMSSignal> mySignals;
- private String [] processCode;
-
-
- public CAMSBlocks(String _name, int _nbOfIn, int _nbOfOut, int _nbOfHybridIn, int _nbOfHybridOut, LinkedList<TAttribute> _myAttributes, LinkedList<CAMSSignal> _mySignals, String [] _processCode){
- name=_name;
- nbOfIn=_nbOfIn;
- nbOfOut=_nbOfOut;
- nbOfHybridIn=_nbOfHybridIn;
- nbOfHybridOut=_nbOfHybridOut;
- myAttributes=_myAttributes;
- mySignals=_mySignals;
- processCode=_processCode;
-
- }
-
- public void setBlockName(String newName){
- name = newName;
- }
-
- public void setNbOfIn(int newIn){
- nbOfIn = newIn;
- }
-
- public void setNbOfOut(int newOut){
- nbOfOut = newOut;
- }
-
- public void setNbOfHybridIn(int newIn){
- nbOfHybridIn = newIn;
- }
-
- public void setNbOfHybridOut(int newOut){
- nbOfHybridOut = newOut;
- }
-
- public void setMyAttributes(LinkedList<TAttribute> newMyAttributes){
- myAttributes = newMyAttributes;
- }
-
- public void setMySignals(LinkedList<CAMSSignal> newMySignals){
- mySignals = newMySignals;
- }
-
- public void setProcessCode(String[] newProcessCode){
- processCode = newProcessCode;
- }
-
- public String getBlockName(){
- return name;
- }
-
- public int getNbOfIn() {
- return nbOfIn;
- }
-
- public int getNbOfOut() {
- return nbOfOut;
- }
- public int getNbOfHybridIn() {
- return nbOfHybridIn;
- }
-
- public int getNbOfHybridOut() {
- return nbOfHybridOut;
- }
- public int getTotalIn() {
- return nbOfIn + nbOfHybridIn;
- }
-
- public int getTotalOut() {
- return nbOfOut + nbOfHybridOut;
- }
-
- public LinkedList<TAttribute> getMyAttributes(){
- return myAttributes;
- }
-
- public LinkedList<CAMSSignal> getMySignals(){
- return mySignals;
- }
-
- public String[] getProcessCode(){
- return processCode;
- }
-
-}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSSpecification.java b/src/main/java/syscamstranslator/SysCAMSSpecification.java
new file mode 100644
index 0000000000..2446a30ac7
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSSpecification.java
@@ -0,0 +1,150 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+import java.util.LinkedList;
+import java.util.List;
+
+/**
+* Creation: 14/05/2018
+* @version 1.0 14/05/2018
+* @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSSpecification{
+ private List<SysCAMSTComponent> components;
+ private List<SysCAMSTConnector> connectors;
+
+ public SysCAMSSpecification(List<SysCAMSTComponent> _components, List<SysCAMSTConnector> _connectors){
+ components = _components ;
+ connectors = _connectors ;
+ }
+
+ public List<SysCAMSTComponent> getComponents(){
+ return components;
+ }
+
+ public List<SysCAMSTConnector> getConnectors(){
+ return connectors;
+ }
+
+ public LinkedList<SysCAMSTBlockTDF> getAllBlockTDF(){
+ LinkedList<SysCAMSTBlockTDF> blocksTDF = new LinkedList<SysCAMSTBlockTDF>();
+ for (SysCAMSTComponent blockTDF : components) {
+ if (blockTDF instanceof SysCAMSTBlockTDF) {
+ blocksTDF.add((SysCAMSTBlockTDF) blockTDF);
+ }
+ }
+ return blocksTDF;
+ }
+
+ public LinkedList<SysCAMSTBlockDE> getAllBlockDE(){
+ LinkedList<SysCAMSTBlockDE> blocksDE = new LinkedList<SysCAMSTBlockDE>();
+ for (SysCAMSTComponent blockDE : components) {
+ if (blockDE instanceof SysCAMSTBlockDE) {
+ blocksDE.add((SysCAMSTBlockDE) blockDE);
+ }
+ }
+ return blocksDE;
+ }
+
+ public LinkedList<SysCAMSTCluster> getAllCluster(){
+ LinkedList<SysCAMSTCluster> clusters = new LinkedList<SysCAMSTCluster>();
+ for (SysCAMSTComponent cluster : components) {
+ if (cluster instanceof SysCAMSTCluster) {
+ clusters.add((SysCAMSTCluster) cluster);
+ }
+ }
+ return clusters;
+ }
+
+ public LinkedList<SysCAMSTPortConverter> getAllPortConverter(){
+ LinkedList<SysCAMSTPortConverter> portsConv = new LinkedList<SysCAMSTPortConverter>();
+ for (SysCAMSTComponent portConv : components) {
+ if (portConv instanceof SysCAMSTPortConverter) {
+ portsConv.add((SysCAMSTPortConverter) portConv);
+ }
+ }
+ return portsConv;
+ }
+
+ public LinkedList<SysCAMSTPortTDF> getAllPortTDF(){
+ LinkedList<SysCAMSTPortTDF> portsTDF = new LinkedList<SysCAMSTPortTDF>();
+ for (SysCAMSTComponent portTDF : components) {
+ if (portTDF instanceof SysCAMSTPortTDF) {
+ portsTDF.add((SysCAMSTPortTDF) portTDF);
+ }
+ }
+ return portsTDF;
+ }
+
+ public LinkedList<SysCAMSTPortDE> getAllPortDE(){
+ LinkedList<SysCAMSTPortDE> portsDE = new LinkedList<SysCAMSTPortDE>();
+ for (SysCAMSTComponent portDE : components) {
+ if (portDE instanceof SysCAMSTPortDE) {
+ portsDE.add((SysCAMSTPortDE) portDE);
+ }
+ }
+ return portsDE;
+ }
+
+ public int getNbBlockTDF(){
+ return (getAllBlockTDF()).size();
+ }
+
+ public int getNbBlockDE(){
+ return (getAllBlockDE()).size();
+ }
+
+ public int getNbCluster(){
+ return (getAllCluster()).size();
+ }
+
+ public int getNbPortConverter(){
+ return (getAllPortConverter()).size();
+ }
+
+ public int getNbPortTDF(){
+ return (getAllPortTDF()).size();
+ }
+
+ public int getNbPortDE(){
+ return (getAllPortDE()).size();
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTBlockDE.java b/src/main/java/syscamstranslator/SysCAMSTBlockDE.java
new file mode 100644
index 0000000000..151a804ba2
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTBlockDE.java
@@ -0,0 +1,84 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+import ui.syscams.SysCAMSPortDE;
+
+/**
+ * Creation: 14/05/2018
+ * @version 1.0 14/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTBlockDE extends SysCAMSTComponent {
+
+ private String blockDEName;
+ private int period;
+ private java.util.List<SysCAMSPortDE> ports;
+
+ public SysCAMSTBlockDE(String _blockDEName, int _period, java.util.List<SysCAMSPortDE> _ports) {
+ blockDEName = _blockDEName;
+ period = _period;
+ ports = _ports;
+ }
+
+ public int getPeriod() {
+ return period;
+ }
+
+ public void setPeriod(int _period) {
+ period = _period;
+ }
+
+ public String getBlockDEName() {
+ return blockDEName;
+ }
+
+ public void setBlockDEName(String _blockDEName) {
+ blockDEName = _blockDEName;
+ }
+
+ public java.util.List<SysCAMSPortDE> getPorts() {
+ return ports;
+ }
+
+ public void setPorts(java.util.List<SysCAMSPortDE> ports) {
+ this.ports = ports;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTBlockTDF.java b/src/main/java/syscamstranslator/SysCAMSTBlockTDF.java
new file mode 100644
index 0000000000..3da72debce
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTBlockTDF.java
@@ -0,0 +1,105 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+import ui.syscams.SysCAMSPortConverter;
+import ui.syscams.SysCAMSPortTDF;
+
+/**
+ * Creation: 14/05/2018
+ * @version 1.0 14/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTBlockTDF extends SysCAMSTComponent {
+
+ private String blockTDFName;
+ private int period;
+ private String processCode;
+ private java.util.List<SysCAMSPortTDF> tdfports;
+ private java.util.List<SysCAMSPortConverter> convports;
+
+ public SysCAMSTBlockTDF(String _blockTDFName, int _period, String _processCode, java.util.List<SysCAMSPortTDF> _tdfports, java.util.List<SysCAMSPortConverter> _convports) {
+ blockTDFName = _blockTDFName;
+ period = _period;
+ processCode = _processCode;
+ tdfports = _tdfports;
+ convports = _convports;
+ }
+
+ public int getPeriod() {
+ return period;
+ }
+
+ public void setPeriod(int _period) {
+ period = _period;
+ }
+
+ public String getProcessCode() {
+ return processCode;
+ }
+
+ public void setProcessCode(String _processCode) {
+ processCode = _processCode;
+ }
+
+ public String getBlockTDFName() {
+ return blockTDFName;
+ }
+
+ public void setBlockTDFName(String _blockTDFName) {
+ blockTDFName = _blockTDFName;
+ }
+
+ public java.util.List<SysCAMSPortTDF> getTdfports() {
+ return tdfports;
+ }
+
+ public void setTdfports(java.util.List<SysCAMSPortTDF> tdfports) {
+ this.tdfports = tdfports;
+ }
+
+ public java.util.List<SysCAMSPortConverter> getConvports() {
+ return convports;
+ }
+
+ public void setConvports(java.util.List<SysCAMSPortConverter> convports) {
+ this.convports = convports;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTCluster.java b/src/main/java/syscamstranslator/SysCAMSTCluster.java
new file mode 100644
index 0000000000..9cd6cea2cd
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTCluster.java
@@ -0,0 +1,75 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+import ui.syscams.SysCAMSBlockTDF;
+
+/**
+ * Creation: 14/05/2018
+ * @version 1.0 14/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTCluster extends SysCAMSTComponent {
+
+ private String clusterName;
+ private java.util.List<SysCAMSBlockTDF> blocks;
+
+ public SysCAMSTCluster(String _clusterName, java.util.List<SysCAMSBlockTDF> _blocks) {
+ super();
+ clusterName = _clusterName;
+ blocks = _blocks;
+ }
+
+ public String getClusterName() {
+ return clusterName;
+ }
+
+ public void setClusterName(String _clusterName) {
+ clusterName = _clusterName;
+ }
+
+ public java.util.List<SysCAMSBlockTDF> getBlocks() {
+ return blocks;
+ }
+
+ public void setBlocks(java.util.List<SysCAMSBlockTDF> blocks) {
+ this.blocks = blocks;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTComponent.java b/src/main/java/syscamstranslator/SysCAMSTComponent.java
new file mode 100644
index 0000000000..5a4b606380
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTComponent.java
@@ -0,0 +1,58 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+/**
+ * Creation: 07/05/2018
+ * @version 1.0 07/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTComponent {
+
+ public String name;
+
+ public String getName() {
+ return name;
+ }
+
+ public void setName(String _name) {
+ name = _name;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSConnection.java b/src/main/java/syscamstranslator/SysCAMSTConnectingPoint.java
old mode 100755
new mode 100644
similarity index 73%
rename from src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSConnection.java
rename to src/main/java/syscamstranslator/SysCAMSTConnectingPoint.java
index 1d3961178b..194e01efd7
--- a/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSConnection.java
+++ b/src/main/java/syscamstranslator/SysCAMSTConnectingPoint.java
@@ -36,43 +36,37 @@
* knowledge of the CeCILL license and that you accept its terms.
*/
-
-
-
-package heterogeneoustranslator.systemCAMStranslator;
-
-import javax.swing.*;
-import java.awt.*;
-import java.util.LinkedList;
-import java.util.Vector;
-import ui.*;
+package syscamstranslator;
/**
-* Class CAMSConnection
-* Connection beetwen blocks for SystemC-AMS Diagrams
-* Creation: 30/08/2017
-* @version 1.0 30/08/2017
-* @author Côme DEMARIGNY
- */
+ * Creation: 07/05/2018
+ * @version 1.0 07/05/2018
+ * @author Irina Kit Yan LEE
+*/
-public class CAMSConnection{
-
- public String name;
- public CAMSBlocks inputBlock, outputBlock;
- public int rate;
- public int type;
-
- public CAMSConnection(CAMSBlocks _inputBlock, CAMSBlocks _outputBlock){
- inputBlock = _inputBlock;
- outputBlock = _outputBlock;
+public class SysCAMSTConnectingPoint{
+
+ SysCAMSTConnector ownerConnector ;
+ SysCAMSTComponent ownerComponent;
+
+ public SysCAMSTConnectingPoint( SysCAMSTComponent _ownerComponent)
+ {
+ ownerComponent = _ownerComponent;
}
- public CAMSBlocks getInputBlock(){
- return inputBlock;
+ SysCAMSTConnector getConnector(){
+ return ownerConnector;
}
- public CAMSBlocks getOutputBlock(){
- return outputBlock;
+ public SysCAMSTComponent getComponent(){
+ return ownerComponent;
}
+ void setConnector(SysCAMSTConnector _connector){
+ ownerConnector = _connector;
+ }
+
+ boolean ConnectingPointIsFree(){
+ return ownerConnector == null;
+ }
}
\ No newline at end of file
diff --git a/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSSignal.java b/src/main/java/syscamstranslator/SysCAMSTConnector.java
old mode 100755
new mode 100644
similarity index 56%
rename from src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSSignal.java
rename to src/main/java/syscamstranslator/SysCAMSTConnector.java
index 3c0cc72cb5..96ea213429
--- a/src/main/java/heterogeneoustranslator/systemCAMStranslator/CAMSSignal.java
+++ b/src/main/java/syscamstranslator/SysCAMSTConnector.java
@@ -1,4 +1,4 @@
- /* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
*
* ludovic.apvrille AT enst.fr
*
@@ -36,76 +36,30 @@
* knowledge of the CeCILL license and that you accept its terms.
*/
-
-
-
-package heterogeneoustranslator.systemCAMStranslator;
-
-import myutil.GraphicLib;
-import org.w3c.dom.Element;
-import org.w3c.dom.Node;
-import org.w3c.dom.NodeList;
-import ui.*;
-import ui.het.*;
-import ui.util.IconManager;
-import ui.window.JDialogCAMSBlocks;
-
-import javax.swing.*;
-import java.awt.*;
-import java.util.LinkedList;
-import java.util.Vector;
-
+package syscamstranslator;
/**
-* Class CAMSSignal
-* Signals for SystemC-AMS Diagrams
-* Creation: 27/06/2017
-* @version 1.0 27/06/2017
-* @author Côme DEMARIGNY
- */
-public class CAMSSignal {
-
- public final static int IN = 0;
- public final static int OUT= 1;
- public final static int HYBRID_IN = 2;
- public final static int HYBRID_OUT= 3;
- public final static int INCORRECT=-1;
-
- private static int i=0;
+ * Creation: 07/05/2018
+ * @version 1.0 07/05/2018
+ * @author Irina Kit Yan LEE
+*/
- private String name;
-
- public int inout;
-
- public CAMSSignal (String _name, int _inout) {
- inout = _inout;
- }
+public class SysCAMSTConnector{
+ private SysCAMSTConnectingPoint connectingPoint1;
+ private SysCAMSTConnectingPoint connectingPoint2;
- public CAMSSignal makeclone(){
- return this;
+ public SysCAMSTConnector(SysCAMSTConnectingPoint _connectingPoint1, SysCAMSTConnectingPoint _connectingPoint2){
+
+ connectingPoint1 = _connectingPoint1;
+ connectingPoint2 = _connectingPoint2;
}
- public static CAMSSignal isAValidSignal(String _name, int _inout) {
- if (_inout==INCORRECT) {
- return null;
- }
- String s = signalName(_name);
- CAMSSignal cs = new CAMSSignal(s, _inout);
-
- return cs;
- }
-
- public int getInout(){
- return inout;
+ public SysCAMSTConnectingPoint get_p1(){
+ return connectingPoint1;
}
- public static String signalName(String _n){
- String s="";
- s+= _n + ": " + signalID();
- return s;
+ public SysCAMSTConnectingPoint get_p2(){
+ return connectingPoint2;
}
-
- public static int signalID(){i++;return i;}
-
}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTPortConverter.java b/src/main/java/syscamstranslator/SysCAMSTPortConverter.java
new file mode 100644
index 0000000000..8427946333
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTPortConverter.java
@@ -0,0 +1,102 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+/**
+ * Creation: 07/05/2018
+ * @version 1.0 07/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTPortConverter extends SysCAMSTComponent {
+
+ private String name;
+ private int period;
+ private int rate;
+ private int delay;
+ private String ConvType;
+
+ public SysCAMSTPortConverter(String _name, int _period, int _rate, int _delay, String _ConvType) {
+ name = _name;
+ period = _period;
+ rate = _rate;
+ delay = _delay;
+ ConvType = _ConvType;
+ }
+
+ public String getName() {
+ return name;
+ }
+
+ public void setName(String _name) {
+ name = _name;
+ }
+
+ public int getPeriod() {
+ return period;
+ }
+
+ public void setPeriod(int _period) {
+ period = _period;
+ }
+
+ public int getRate() {
+ return rate;
+ }
+
+ public void setRate(int _rate) {
+ rate = _rate;
+ }
+
+ public int getDelay() {
+ return delay;
+ }
+
+ public void setDelay(int _delay) {
+ delay = _delay;
+ }
+
+ public String getConvType() {
+ return ConvType;
+ }
+
+ public void setConvType(String _ConvType) {
+ ConvType = _ConvType;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTPortDE.java b/src/main/java/syscamstranslator/SysCAMSTPortDE.java
new file mode 100644
index 0000000000..9f1c549976
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTPortDE.java
@@ -0,0 +1,112 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+/**
+ * Creation: 07/05/2018
+ * @version 1.0 07/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTPortDE extends SysCAMSTComponent {
+
+ private String name;
+ private int period;
+ private int rate;
+ private int delay;
+ private int origin;
+ private String DEType;
+
+ public SysCAMSTPortDE(String _name, int _period, int _rate, int _delay, int _origin, String _DEType) {
+ name = _name;
+ period = _period;
+ rate = _rate;
+ delay = _delay;
+ origin = _origin;
+ DEType = _DEType;
+ }
+
+ public String getName() {
+ return name;
+ }
+
+ public void setName(String _name) {
+ name = _name;
+ }
+
+ public int getPeriod() {
+ return period;
+ }
+
+ public void setPeriod(int _period) {
+ period = _period;
+ }
+
+ public int getRate() {
+ return rate;
+ }
+
+ public void setRate(int _rate) {
+ rate = _rate;
+ }
+
+ public int getDelay() {
+ return delay;
+ }
+
+ public void setDelay(int _delay) {
+ delay = _delay;
+ }
+
+ public int getOrigin() {
+ return origin;
+ }
+
+ public void setOrigin(int _origin) {
+ origin = _origin;
+ }
+
+ public String getDEType() {
+ return DEType;
+ }
+
+ public void setDEType(String _DEType) {
+ DEType = _DEType;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/SysCAMSTPortTDF.java b/src/main/java/syscamstranslator/SysCAMSTPortTDF.java
new file mode 100644
index 0000000000..628c828f9e
--- /dev/null
+++ b/src/main/java/syscamstranslator/SysCAMSTPortTDF.java
@@ -0,0 +1,112 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ *
+ * ludovic.apvrille AT enst.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+package syscamstranslator;
+
+/**
+ * Creation: 07/05/2018
+ * @version 1.0 07/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class SysCAMSTPortTDF extends SysCAMSTComponent {
+
+ private String name;
+ private int period;
+ private int rate;
+ private int delay;
+ private int origin;
+ private String TDFType;
+
+ public SysCAMSTPortTDF(String _name, int _period, int _rate, int _delay, int _origin, String _TDFType) {
+ name = _name;
+ period = _period;
+ rate = _rate;
+ delay = _delay;
+ origin = _origin;
+ TDFType = _TDFType;
+ }
+
+ public String getName() {
+ return name;
+ }
+
+ public void setName(String _name) {
+ name = _name;
+ }
+
+ public int getPeriod() {
+ return period;
+ }
+
+ public void setPeriod(int _period) {
+ period = _period;
+ }
+
+ public int getRate() {
+ return rate;
+ }
+
+ public void setRate(int _rate) {
+ rate = _rate;
+ }
+
+ public int getDelay() {
+ return delay;
+ }
+
+ public void setDelay(int _delay) {
+ delay = _delay;
+ }
+
+ public int getOrigin() {
+ return origin;
+ }
+
+ public void setOrigin(int _origin) {
+ origin = _origin;
+ }
+
+ public String getTDFType() {
+ return TDFType;
+ }
+
+ public void setTDFType(String _TDFType) {
+ TDFType = _TDFType;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Code.java b/src/main/java/syscamstranslator/toSysCAMS/Code.java
new file mode 100644
index 0000000000..24eb31dab7
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Code.java
@@ -0,0 +1,169 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package syscamstranslator.toSysCAMS;
+
+import ddtranslatorSoclib.AvatarCPU;
+import common.ConfigurationTTool;
+
+import java.io.BufferedReader;
+import java.io.File;
+import java.io.FileReader;
+import java.io.IOException;
+
+public class Code {
+
+ static private String creation;
+ static private String creation2;
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private final static String GENERATED_PATH = "generated_topcell" + File.separator;
+
+ public static String getCode() {
+
+ creation = CR + "//**********************************************************************" + CR
+ + "// Processor entry and connection code" + CR
+ + "//**********************************************************************" + CR2 +
+
+ "#define CPU_CONNECT(n) void (n)(CpuEntry *e, sc_core::sc_clock &clk, \\" + CR
+ + "sc_core::sc_signal<bool> &rstn, caba::VciSignals<vci_param> &m)" + CR2
+ + "#define INIT_TOOLS(n) void (n)(const common::Loader &ldr)" + CR2
+ + "#define NEW_CPU(n) caba::BaseModule * (n)(CpuEntry *e)" + CR2 + "struct CpuEntry { " + CR
+ + " caba::BaseModule *cpu; " + CR + " common::Loader *text_ldr;" + CR
+ + " sc_core::sc_signal<bool> *irq_sig;" + CR + " size_t irq_sig_count;" + CR + " std::string type;"
+ + CR + " std::string name;" + CR + " int id;" + CR + " CPU_CONNECT(*connect);" + CR
+ + " INIT_TOOLS(*init_tools);" + CR + " NEW_CPU(*new_cpu);" + CR + "};" + CR2
+ + " template <class Iss_>" + CR + " CPU_CONNECT(cpu_connect){" + CR + " typedef ISS_NEST(Iss_) Iss;"
+ + CR
+ + " caba::VciXcacheWrapper<vci_param, Iss> *cpu = static_cast<caba::VciXcacheWrapper<vci_param, Iss> *>(e->cpu);"
+ + CR + " cpu->p_clk(clk);" + CR + " cpu->p_resetn(rstn);" + CR
+ + " e->irq_sig_count = Iss::n_irq; " + CR
+ + " e->irq_sig = new sc_core::sc_signal<bool>[Iss::n_irq];" + CR +
+
+ " for ( size_t irq = 0; irq < (size_t)Iss::n_irq; ++irq )" + CR
+ + " cpu->p_irq[irq](e->irq_sig[irq]); " + CR + " cpu->p_vci(m);" + CR + " }" + CR2;
+
+ creation = creation + "template <class Iss>" + CR + "INIT_TOOLS(initialize_tools){" + CR;
+
+ // Mips based platform requires a special bootstrap where only cpu 0 starts
+ // first
+
+ int isMipsArchitecture = 0;
+
+ try {
+ String path = ConfigurationTTool.AVATARMPSoCCodeDirectory;
+ BufferedReader in = new BufferedReader(new FileReader(path + "/Makefile.forsoclib"));
+ String line = null;
+ while ((line = in.readLine()) != null) {
+
+ if (line.equals("SOCLIB_CPU=mips32el")) {
+ isMipsArchitecture = 1;
+ }
+ }
+ in.close();
+ } catch (IOException e) {
+ e.printStackTrace();
+ }
+
+ if (isMipsArchitecture == 1) {
+ creation = creation + "Iss::setBoostrapCpuId(0);" + CR + "/* Only processor 0 starts execution on reset */"
+ + CR;
+ }
+ creation = creation + "#if defined(CONFIG_GDB_SERVER)" + CR + "ISS_NEST(Iss)::set_loader(ldr);" + CR + "#endif"
+ + CR + "#if defined(CONFIG_SOCLIB_MEMCHECK)" + CR
+ + " common::IssMemchecker<Iss>::init(maptab, ldr, \"vci_multi_tty0,vci_xicu,vci_block_device,vci_fd_acccess,vci_ethernet,vci_fdt_rom,vci_rttimer\");"
+ + CR + "#endif" + CR + "}" + CR2;
+
+ // currently, all caches must have the same parameters : take one
+ AvatarCPU cpu = TopCellGenerator.syscams.getAllCPU().getFirst();
+
+ int nb_clusters = TopCellGenerator.syscams.getAllCrossbar().size();
+
+ if (nb_clusters == 0) {
+ creation = creation + "template <class Iss>" + CR + "NEW_CPU(new_cpu){" + CR
+ + "return new caba::VciXcacheWrapper<vci_param, ISS_NEST(Iss)>(e->name.c_str(), e->id, maptab, IntTab(e->id),"
+ + cpu.getICacheWays() + "," + cpu.getICacheSets() + "," + cpu.getICacheWords() + ","
+ + cpu.getDCacheWays() + "," + cpu.getDCacheSets() + "," + cpu.getDCacheWords() + ")" + ";" + CR
+ + "}" + CR2;
+ } else {
+ creation = creation + "template <class Iss>" + CR + "NEW_CPU(new_cpu){" + CR
+ + "return new caba::VciXcacheWrapper<vci_param, ISS_NEST(Iss)>(e->name.c_str(), e->id, maptab, IntTab(e->id,e->id),"
+ + cpu.getICacheWays() + "," + cpu.getICacheSets() + "," + cpu.getICacheWords() + ","
+ + cpu.getDCacheWays() + "," + cpu.getDCacheSets() + "," + cpu.getDCacheWords() + ")" + ";" + CR
+ + "}" + CR2;
+ }
+
+ creation = creation + "/***************************************************************************" + CR
+ + "--------------------Processor creation code-------------------------" + CR
+ + "***************************************************************************/" + CR2 +
+
+ "template <class Iss> " + CR + " CpuEntry * newCpuEntry_(CpuEntry *e){" + CR
+ + " e->new_cpu = new_cpu<Iss>;" + CR + " e->connect = cpu_connect<Iss>;" + CR
+ + " e->init_tools = initialize_tools<Iss>;" + CR + " return e;" + CR + "}" + CR2 +
+
+ " struct CpuEntry * newCpuEntry(const std::string &type, int id, common::Loader *ldr) {" + CR
+ + " CpuEntry *e = new CpuEntry;" + CR + " std::ostringstream o;" + CR + " o << type << \"_\" << id; "
+ + CR2 + " e->cpu = 0;" + CR + " e->text_ldr = ldr;" + CR + " e->type = type;" + CR
+ + " e->name = o.str();" + CR + " e->id = id; " + CR2 + " switch (type[0]) {" + CR + " case 'm':"
+ + CR + " if (type == \"mips32el\")" + CR + " return newCpuEntry_<common::Mips32ElIss>(e);"
+ + CR + " else if (type == \"mips32eb\")" + CR
+ + " return newCpuEntry_<common::Mips32EbIss>(e);" + CR2 + " case 'a':" + CR
+ + " if (type == \"arm\")" + CR + " return newCpuEntry_<common::ArmIss>(e);" + CR
+ + " case 'n':" + CR + " if (type == \"nios2\")" + CR
+ + " return newCpuEntry_<common::Nios2fIss>(e);" + CR2 + " case \'p\':" + CR
+ + " if (type == \"ppc\")return newCpuEntry_<common::Ppc405Iss>(e);" + CR2 + " case 's':" + CR
+ + " if (type == \"sparc\")" + CR + " return newCpuEntry_<common::Sparcv8Iss<8> >(e);" + CR
+ + " else if (type == \"sparc_2wins\")" + CR
+ + " return newCpuEntry_<common::Sparcv8Iss<2> >(e);" + CR2 + " case 'l':" + CR
+ + " if (type == \"lm32\")" + CR + " return newCpuEntry_<common::LM32Iss<true> >(e);" + CR
+ + " } " + CR2 + " throw std::runtime_error(type + \": wrong processor type\"); " + CR + "}" + CR2
+ + "//**********************************************************************" + CR
+ + "// Args parsing and netlist" + CR2
+ + "//**********************************************************************" + CR2
+ + "int _main(int argc, char **argv)" + CR + "{" + CR2 + " // Avoid repeating these everywhere" + CR
+ + " std::vector<CpuEntry*> cpus;" + CR + " common::Loader data_ldr;" + CR
+ + " data_ldr.memory_default(0x5a);" + CR;
+ return creation;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Corps.java b/src/main/java/syscamstranslator/toSysCAMS/Corps.java
new file mode 100644
index 0000000000..24db0e41ad
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Corps.java
@@ -0,0 +1,159 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package syscamstranslator.toSysCAMS;
+
+import java.util.List;
+
+import syscamstranslator.*;
+import ui.syscams.SysCAMSBlockTDF;
+import ui.syscams.SysCAMSPortConverter;
+import ui.syscams.SysCAMSPortTDF;
+
+/**
+ * Class Header
+ * En-t�te des fichiers .h et .cpp
+ * Creation: 14/05/2018
+ * @version 1.0 14/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class Corps {
+ static private String corpsPrimitive;
+ static private String corpsCluster;
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ Corps() {}
+
+ public static String getPrimitiveCorps(SysCAMSTBlockTDF tdf) {
+ if (tdf != null) {
+ List<SysCAMSPortTDF> tdfports = tdf.getTdfports();
+ List<SysCAMSPortConverter> convports = tdf.getConvports();
+
+ corpsPrimitive = "//-------------------------------Corps------------------------------------" + CR2
+ + "SCA_TDF_MODULE(" + tdf.getBlockTDFName() + ") {" + CR2;
+
+ if (!tdfports.isEmpty()) {
+ corpsPrimitive = corpsPrimitive + "\t// TDF port declarations" + CR;
+ for (SysCAMSPortTDF t : tdfports) {
+ if (t.getOrigin() == 0) {
+ corpsPrimitive = corpsPrimitive + "\tsca_tdf::sca_in<" + t.getTDFType() + "> " + t.getPortName() + CR;
+ } else if (t.getOrigin() == 1) {
+ corpsPrimitive = corpsPrimitive + "\tsca_tdf::sca_out<" + t.getTDFType() + "> " + t.getPortName() + CR;
+ }
+ }
+ }
+ if (!convports.isEmpty()) {
+ corpsPrimitive = corpsPrimitive + "\t// Converter port declarations" + CR;
+ for (SysCAMSPortConverter conv : convports) {
+ if (conv.getOrigin() == 0) {
+ corpsPrimitive = corpsPrimitive + "\tsca_tdf::sca_de::sca_in<" + conv.getConvType() + "> " + conv.getPortName() + CR;
+ } else if (conv.getOrigin() == 1) {
+ corpsPrimitive = corpsPrimitive + "\tsca_tdf::sca_de::out<" + conv.getConvType() + "> " + conv.getPortName() + CR;
+ }
+ }
+ }
+
+ corpsPrimitive = corpsPrimitive + CR + "\t// Constructor" + CR + "\tSCA_CTOR(" + tdf.getBlockTDFName() + ")" + CR;
+
+ if (!tdfports.isEmpty() || !convports.isEmpty()) {
+ corpsPrimitive = corpsPrimitive + ": ";
+ if (!tdfports.isEmpty()) {
+ for (SysCAMSPortTDF t : tdfports) {
+ corpsPrimitive = corpsPrimitive + "\t" + t.getPortName() + "(\"" + t.getPortName() + "\")"+ CR;
+ }
+ }
+ if (!convports.isEmpty()) {
+ for (SysCAMSPortConverter conv : convports) {
+ corpsPrimitive = corpsPrimitive + "\t" + conv.getPortName() + "(\"" + conv.getPortName() + "\")"+ CR;
+ }
+ }
+ corpsPrimitive = corpsPrimitive + "\t{}" + CR2;
+ }
+
+ corpsPrimitive = corpsPrimitive + "\tvoid set_attributes() {" + CR;
+
+ // Block period
+ if (tdf.getPeriod() != 0) {
+ corpsPrimitive = corpsPrimitive + "\t\t" + "set_timestep(" + tdf.getPeriod() + ", sc_core::SC_MS);" + CR;
+ }
+ for (SysCAMSPortTDF t : tdfports) {
+ if (t.getPeriod() != 0) {
+ corpsPrimitive = corpsPrimitive + "\t\t" + t.getPortName() + ".set_timestep(" + t.getPeriod() + ", sc_core::SC_US);" + CR;
+ }
+ if (t.getRate() != 0) {
+ corpsPrimitive = corpsPrimitive + "\t\t" + t.getPortName() + ".set_rate(" + t.getRate() + ");" + CR;
+ }
+ if (t.getDelay() != 0) {
+ corpsPrimitive = corpsPrimitive + "\t\t" + t.getPortName() + ".set_delay(" + t.getDelay() + ");" + CR;
+ }
+ }
+ // Block processCode
+ corpsPrimitive = corpsPrimitive + "\t}" + CR2 + "\t" + tdf.getProcessCode() + CR2 + "};" + CR2 + "# endif"
+ + " // " + tdf.getBlockTDFName().toUpperCase() + "_H";
+ } else {
+ corpsPrimitive = "";
+ }
+ return corpsPrimitive;
+ }
+
+ public static String getClusterCorps(SysCAMSTCluster cluster) {
+ if (cluster != null) {
+ List<SysCAMSBlockTDF> blocks = cluster.getBlocks();
+
+ corpsCluster = "//-------------------------------Header------------------------------------" + CR2
+ + "#include <systemc-ams>" + CR2;
+
+ for (SysCAMSBlockTDF b : blocks) {
+ corpsCluster = corpsCluster + "#include \"" + b.getValue() + ".h\"" + CR;
+ }
+ corpsCluster = corpsCluster + CR;
+ } else {
+ corpsCluster = "";
+ }
+ return corpsCluster;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Declaration.java b/src/main/java/syscamstranslator/toSysCAMS/Declaration.java
new file mode 100644
index 0000000000..b4581dbbef
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Declaration.java
@@ -0,0 +1,395 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015
+ v2.1 Daniela GENIUS, 2016, 2017 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.*;
+import avatartranslator.AvatarRelation;
+import avatartranslator.AvatarBlock;
+import avatartranslator.AvatarSignal;
+import avatartranslator.AvatarSpecification;
+
+public class Declaration {
+ public static AvatarSpecification avspec;
+ private static String CR = "\n";
+ private static String CR2 = "\n\n";
+
+ public static String generateName(AvatarRelation _ar, int _index) {
+ return _ar.block1.getName() + "_" + _ar.getSignal1(_index).getName() + "__" + _ar.block2.getName() + "_"
+ + _ar.getSignal2(_index).getName();
+ }
+
+ public static String getDeclarations(AvatarSpecification _avspec) {
+ avspec = _avspec;
+
+ String declaration = "//----------------------------Instantiation-------------------------------" + CR2;
+
+ int nb_clusters = TopCellGenerator.syscams.getAllCrossbar().size();
+
+ boolean trace_caba = true;
+
+ if (nb_clusters == 0) {
+ declaration += CR + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);"
+ + CR;
+ } else {
+ declaration += CR + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);"
+ + CR;
+ }
+ if (nb_clusters == 0) {
+ declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);" + CR;
+ } else {
+ declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);" + CR;
+ }
+
+ if (nb_clusters == 0) {
+ declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);" + CR;
+ } else {
+ declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);"
+ + CR;
+ }
+
+ if (nb_clusters == 0) {
+ declaration = declaration
+ + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ } else {
+ declaration = declaration
+ + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ + CR;
+ }
+
+ if (nb_clusters == 0) {
+ declaration = declaration
+ + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);" + CR2;
+ } else {
+ declaration = declaration
+ + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);" + CR2;
+ }
+
+ if (nb_clusters == 0) {
+ declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);" + CR;
+ } else {
+ declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);" + CR;
+ }
+
+ int last_tty = 0;
+ if (nb_clusters == 0) {
+ int i = 0;
+ for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
+ declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName() + "(\"" + tty.getTTYName()
+ + "\", IntTab(" + tty.getNo_target() + "), maptab, \"vci_multi_tty" + i + "\", NULL);" + CR;
+ i++;
+ last_tty = tty.getNo_target() + 1;
+ }
+
+ // target address depends on number of TTYs and RAMs
+
+ if (nb_clusters == 0) {
+ // declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\",
+ // IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(" + (last_tty + 3)
+ + "), maptab);" + CR;
+ } else {
+ declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
+ }
+
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
+ if (ram.getIndex() == 0) {
+ declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName() + "(\"" + ram.getMemoryName()
+ + "\"" + ", IntTab(2), maptab);" + CR;
+ } else {
+ declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName() + "(\"" + ram.getMemoryName()
+ + "\"" + ", IntTab(" + ram.getNo_target() + "), maptab);" + CR;
+ }
+ } else {
+ int i = 0;
+ for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
+ declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName() + "(\"" + tty.getTTYName()
+ + "\", IntTab(" + tty.getNo_cluster() + "," + tty.getNo_target() + "), maptab, \"vci_multi_tty"
+ + i + "\", NULL);" + CR;
+ i++;
+ }
+
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
+ declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName() + "(\"" + ram.getMemoryName()
+ + "\"" + ", IntTab(" + ram.getNo_cluster() + "," + ram.getNo_target() + "), maptab);" + CR2;
+ }
+ if (nb_clusters == 0) {
+ /*
+ * declaration +=
+ * "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
+ * +(TopCellGenerator.avatardd.getNb_target())+"));" + CR; declaration +=
+ * "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
+ * +(TopCellGenerator.avatardd.getNb_target()+1)+"), \"soclib0\");" + CR;
+ * declaration +=
+ * "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
+ * +(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" +
+ * CR;
+ */
+
+ declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
+ + last_tty + "));" + CR;
+ declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
+ + (last_tty + 1) + "), \"soclib0\");" + CR;
+ declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
+ + (last_tty + 2) + "),\"block0.iso\", 2048);" + CR;
+
+ // only non-clustered version
+ int hwa_no = 0;
+ // int target_no = TopCellGenerator.avatardd.getNb_target();
+ int target_no = (last_tty + 4);// DG 5.9.
+ int init_no = TopCellGenerator.syscams.getNb_init();
+ for (AvatarCoproMWMR copro : TopCellGenerator.syscams.getAllCoproMWMR()) {
+ // declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+
+ // "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "),
+ // IntTab("+copro.getTgtid() +
+ // "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(),
+ // copro.getUseLLSC());"+ CR;
+
+ declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName() + "(\""
+ + copro.getCoprocName() + "\", maptab, IntTab(" + (init_no - 1) + "), IntTab(" + target_no
+ + ")," + copro.getPlaps() + "," + copro.getFifoToCoprocDepth() + ","
+ + copro.getFifoFromCoprocDepth() + "," + copro.getNToCopro() + "," + copro.getNFromCopro() + ","
+ + copro.getNConfig() + "," + copro.getNStatus() + "," + copro.getUseLLSC() + ");" + CR2;
+
+ // one virtual component for each hardware accellerator, info from diplodocus
+ // (not yet implemented)
+
+ // DG 28.08.
+ // declaration += "soclib::caba::FifoVirtualCoprocessorWrapper
+ // hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
+
+ declaration += "dsx::caba::MyHWA" + hwa_no + " hwa" + hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
+ target_no++;
+ init_no++;
+ hwa_no++;
+ }
+
+ } else {
+ declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));"
+ + CR;
+ declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");"
+ + CR;
+ declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);"
+ + CR;
+ }
+
+ if (nb_clusters == 0) {
+
+ for (AvatarBus bus : TopCellGenerator.syscams.getAllBus()) {
+ System.out.println("initiators: " + TopCellGenerator.syscams.getNb_init());
+ System.out.println("targets: " + TopCellGenerator.syscams.getNb_target());
+
+ // declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName()
+ // + "\"" + " , maptab, cpus.size()+3," +
+ // (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
+ // declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName()
+ // + "\"" + " , maptab, cpus.size()+3," +
+ // (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
+
+ declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab,"
+ + (3 + TopCellGenerator.syscams.getNb_init()) + ","
+ + (TopCellGenerator.syscams.getNb_target() + 4) + ");" + CR2;// DG 28.08.
+ int i = 0;
+
+ // if BUS was not last in input file, update here
+
+ bus.setNbOfAttachedInitiators(TopCellGenerator.syscams.getNb_init());
+ bus.setnbOfAttachedTargets(TopCellGenerator.syscams.getNb_target());
+ }
+
+ for (AvatarVgmn vgmn : TopCellGenerator.syscams.getAllVgmn()) {
+ // System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
+ // System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
+ /*
+ * The user might have forgotten to specify the following, thus set default
+ * values
+ */
+
+ if (vgmn.getMinLatency() < 2)
+ vgmn.setMinLatency(10); // default value; must be > 2
+ if (vgmn.getFifoDepth() < 2)
+ vgmn.setFifoDepth(8); // default value; must be > 2
+
+ // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
+ // vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," +
+ // (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() +
+ // "," + vgmn.getFifoDepth() + ");" + CR2;
+ // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
+ // vgmn.getVgmnName() + "\"" + " , maptab, "
+ // +(3+TopCellGenerator.avatardd.getNb_init())+"," +
+ // (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() +
+ // "," + vgmn.getFifoDepth() + ");" + CR2;//DG 28.08.
+
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, "
+ + (3 + TopCellGenerator.syscams.getNb_init()) + ","
+ + (TopCellGenerator.syscams.getNb_target() + 3) + "," + vgmn.getMinLatency() + ","
+ + vgmn.getFifoDepth() + ");" + CR2;// DG 5.9.
+
+ // declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
+ // vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," +
+ // (TopCellGenerator.avatardd.getNbRAM()+TopCellGenerator.avatardd.getNbTTY()+4)+
+ // "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
+
+ // if VGMN was not last in input file, update here
+ vgmn.setNbOfAttachedInitiators(TopCellGenerator.syscams.getNb_init());
+ vgmn.setnbOfAttachedTargets(TopCellGenerator.syscams.getNb_target() + 4);
+
+ }
+
+ /*
+ * VciMwmrController( sc_module_name name, const MappingTable &mt, const IntTab
+ * &srcid, const IntTab &tgtid, const size_t plaps, const size_t
+ * fifo_to_coproc_depth, const size_t fifo_from_coproc_depth, const size_t
+ * n_to_coproc, const size_t n_from_coproc, const size_t n_config, const size_t
+ * n_status, const bool use_llsc );
+ */
+
+ } else {
+
+ /***************************************/
+ /* clustered interconnect architecture */
+ /***************************************/
+
+ for (AvatarBus bus : TopCellGenerator.syscams.getAllBus()) {
+
+ declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, "
+ + +nb_clusters + "," + nb_clusters + ");" + CR2;
+
+ // if BUS was not last in input file, update here
+ int i = 0;
+ }
+
+ for (AvatarVgmn vgmn : TopCellGenerator.syscams.getAllVgmn()) {
+ System.out.println("initiators: " + TopCellGenerator.syscams.getNb_init());
+ System.out.println("targets: " + TopCellGenerator.syscams.getNb_target());
+
+ declaration += "soclib::caba::VciVgmn<vci_param> vgmn (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "
+ + nb_clusters + "," + nb_clusters + "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth()
+ + ");" + CR2;
+
+ }
+
+ int i = 0;
+ for (AvatarCrossbar crossbar : TopCellGenerator.syscams.getAllCrossbar()) {
+
+ // currently the number on initiators and targets is fixed
+
+ crossbar.setClusterIndex(i);
+
+ if (crossbar.getClusterIndex() == 0) {
+ crossbar.setNbOfAttachedInitiators(nb_clusters);
+ crossbar.setNbOfAttachedTargets(13);
+ } else {
+ // processor(s) and link to central interconnect are initiators
+ // crossbar.setNbOfAttachedInitiators(2);
+ // crossbar.setNbOfAttachedTargets(2);
+ crossbar.setNbOfAttachedInitiators(1);
+ crossbar.setNbOfAttachedTargets(1);
+ }
+
+ System.out.println("initiators: " + crossbar.getNbOfAttachedInitiators());
+ System.out.println("targets: " + crossbar.getNbOfAttachedTargets());
+
+ declaration += "soclib::caba::VciLocalCrossbar<vci_param> crossbar" + crossbar.getClusterIndex() + "(\""
+ + crossbar.getCrossbarName() + "\"" + " , maptab, IntTab(" + crossbar.getClusterIndex()
+ + "),IntTab(" + crossbar.getClusterIndex() + "), " + crossbar.getNbOfAttachedInitiators() + ", "
+ + crossbar.getNbOfAttachedTargets() + ");" + CR2;
+
+ // if CROSSBAR was not last in input file, update here
+ crossbar.setNbOfAttachedInitiators(TopCellGenerator.syscams.getNb_init());
+ crossbar.setNbOfAttachedTargets(TopCellGenerator.syscams.getNb_target());
+
+ }
+ }
+ int i = 0;
+ // monitoring CPU by logger(1)
+ for (AvatarCPU cpu : TopCellGenerator.syscams.getAllCPU()) {
+
+ if (cpu.getMonitored() == 1) {
+ System.out.println("Spy CPU");
+ declaration += "soclib::caba::VciLogger<vci_param> logger" + i + "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ }
+ }
+
+ int j = 0;
+ // monitoring RAM either by logger(1) ou stats (2)
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM()) {
+ if (ram.getMonitored() == 0) {
+
+ }
+ if (ram.getMonitored() == 1) {
+ System.out.println("Spy RAM : Logger");
+ declaration += "soclib::caba::VciLogger<vci_param> logger" + i + "(\"logger" + i + "\",maptab);" + CR2;
+ i++;
+ } else {
+ if (ram.getMonitored() == 2) {
+ System.out.println("Spy RAM : Stats");
+ String strArray = "";
+
+ for (AvatarRelation ar : avspec.getRelations()) {
+
+ for (i = 0; i < ar.nbOfSignals(); i++) {
+
+ AvatarSignal as1 = ar.getSignal1(i);
+ AvatarSignal as2 = ar.getSignal2(i);
+
+ String chname = generateName(ar, i);
+ strArray = strArray + "\"" + chname + "\",";
+ }
+
+ }
+
+ declaration += "soclib::caba::VciMwmrStats<vci_param> mwmr_stats" + j + "(\"mwmr_stats" + j
+ + "\",maptab, data_ldr, \"mwmr" + j + ".log\",stringArray(" + strArray + "NULL));" + CR2;
+ j++;
+ }
+ }
+ }
+
+ return declaration;
+ }
+
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Header.java b/src/main/java/syscamstranslator/toSysCAMS/Header.java
new file mode 100644
index 0000000000..088972a197
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Header.java
@@ -0,0 +1,97 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package syscamstranslator.toSysCAMS;
+
+import java.util.List;
+
+import syscamstranslator.*;
+import ui.syscams.SysCAMSBlockTDF;
+
+/**
+ * Class Header
+ * En-t�te des fichiers .h et .cpp
+ * Creation: 14/05/2018
+ * @version 1.0 14/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class Header {
+ static private String headerPrimitive;
+ static private String headerCluster;
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ Header() {}
+
+ public static String getPrimitiveHeader(SysCAMSTBlockTDF tdf) {
+ if (tdf != null) {
+ headerPrimitive = "//-------------------------------Header------------------------------------" + CR2
+ + "#ifndef " + tdf.getBlockTDFName().toUpperCase() + "_H"+ CR
+ + "#define " + tdf.getBlockTDFName().toUpperCase() + "_H" + CR2
+ + "#include <cmath>" + CR + "#include <iostream>" + CR + "#include <systemc-ams>" + CR2;
+ } else {
+ headerPrimitive = "";
+ }
+ return headerPrimitive;
+ }
+
+ public static String getClusterHeader(SysCAMSTCluster cluster) {
+ if (cluster != null) {
+ List<SysCAMSBlockTDF> blocks = cluster.getBlocks();
+
+ headerCluster = "//-------------------------------Header------------------------------------" + CR2
+ + "#include <systemc-ams>" + CR2;
+
+ for (SysCAMSBlockTDF b : blocks) {
+ headerCluster = headerCluster + "#include \"" + b.getValue() + ".h\"" + CR;
+ }
+ headerCluster = headerCluster + CR;
+ } else {
+ headerCluster = "";
+ }
+ return headerCluster;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Loader.java b/src/main/java/syscamstranslator/toSysCAMS/Loader.java
new file mode 100644
index 0000000000..f8b7dac312
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Loader.java
@@ -0,0 +1,148 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+/* authors: v1.0 Daniela GENIUS, Julien HENON 2015 */
+
+
+package ddtranslatorSoclib.toTopCell;
+import avatartranslator.AvatarRelation;//DG 23.06.
+import avatartranslator.AvatarSpecification;//DG 23.06.
+import ddtranslatorSoclib.AvatarChannel;
+
+public class Loader {
+public static AvatarSpecification avspec;
+ static private String loader;
+ private final static String NAME_CLK = "signal_clk";
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public Loader(AvatarSpecification _avspec){
+
+ avspec =_avspec;
+ }
+
+ public static String getLoader(AvatarSpecification _avspec) {//DG 23.06.
+ avspec =_avspec;//DG 23.06.
+ int nb_clusters=TopCellGenerator.syscams.getAllCrossbar().size();
+ //nb_clusters=2;
+
+ loader = CR2 + "//-------------------------Call Loader---------------------------------" + CR2 ;
+ loader = loader + "std::cerr << \"caba-vgmn-mutekh_kernel_tutorial SoCLib simulator for MutekH\" << std::endl;"
+ + CR2 ;
+
+ loader = loader + "if ( (argc < 2) || ((argc % 2) == 0) ) {" + CR ;
+
+ loader = loader + "exit(0); }" + CR ;
+
+ loader = loader + " argc--;" + CR ;
+ loader = loader + " argv++;" + CR2 ;
+ loader = loader + "bool heterogeneous = (argc > 2);" + CR2 ;
+
+ loader = loader + " for (int i = 0; i < (argc - 1); i += 2){" + CR ;
+ loader = loader + " char *cpu_p = argv[i];" + CR ;
+ loader = loader + " const char *kernel_p = argv[i+1];" + CR ;
+ loader = loader + " const char *arch_str = strsep(&cpu_p, \":\");" + CR ;
+ loader = loader + " int count = cpu_p ? atoi(cpu_p) : 1;" + CR ;
+
+ loader = loader + " common::Loader *text_ldr; " + CR ;
+
+ loader = loader + " if (heterogeneous) {" + CR ;
+ loader = loader + " text_ldr = new common::Loader(std::string(kernel_p) + \";.text\");" + CR ;
+ loader = loader + " text_ldr->memory_default(0x5a);;" + CR ;
+ loader = loader + " data_ldr.load_file(std::string(kernel_p) + \";.rodata;.boot;.excep\");" + CR ;
+ loader = loader + " if (i == 0)" + CR ;
+ loader = loader + " data_ldr.load_file(std::string(kernel_p) + \";.data;";
+ // We generated so far until arriving at first channel segment, if any
+ //current hypothesis : one segment per channel
+ int j=0;
+ //for (AvatarChannel channel : TopCellGenerator.avatardd.getAllMappedChannels()) {
+ //DG 23.06. per signal!!hack pour l'instant
+ int i=0;
+ //for (i=0;i<30;i++){
+
+ for(AvatarRelation ar: avspec.getRelations()) {
+
+ for(i=0; i<ar.nbOfSignals() ; i++) {
+
+ loader = loader + ".channel" + j + ";";
+ j++;
+ }
+}
+ // We resume the generation of the fixed code
+ loader = loader + ".cpudata;.contextdata\");" + CR ;
+ loader = loader + " } else {" + CR ;
+ loader = loader + " text_ldr = new common::Loader(std::string(kernel_p));" + CR ;
+ loader = loader + " text_ldr->memory_default(0x5a);" + CR ;
+ loader = loader + " data_ldr.load_file(std::string(kernel_p));" + CR ;
+ loader = loader + " }" + CR2 ;
+
+ loader = loader + " common::Loader tools_ldr(kernel_p);" + CR ;
+ loader = loader + " tools_ldr.memory_default(0x5a);" + CR2 ;
+
+ loader = loader + " for (int j = 0; j < count; j++) {" + CR ;
+ loader = loader + " int id = cpus.size();" + CR ;
+ loader = loader + " std::cerr << \"***\" << cpus.size() << std::endl;" + CR ;
+
+ loader = loader + " CpuEntry *e = newCpuEntry(arch_str, id, text_ldr);" + CR ;
+
+ loader = loader + " if (j == 0)" + CR ;
+ loader = loader + " e->init_tools(tools_ldr);" + CR ;
+
+ loader = loader + " e->cpu = e->new_cpu(e);" + CR ;
+ loader = loader + " cpus.push_back(e);" + CR ;
+ loader = loader + " }" + CR ;
+ loader = loader + " }" + CR2 ;
+ int nb_tty =1; //DG currently only one (multi) tty
+
+if(nb_clusters==0){
+ loader = loader + " const size_t xicu_n_irq = "+(1+nb_tty+3)+";" + CR2 ;
+}else{
+ loader = loader + " const size_t xicu_n_irq = "+(5*nb_clusters)+";" + CR2 ;
+}
+ return loader;
+ }
+
+ String getNAME_CLK(){
+ return NAME_CLK;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/NetList.java b/src/main/java/syscamstranslator/toSysCAMS/NetList.java
new file mode 100644
index 0000000000..daf263cdad
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/NetList.java
@@ -0,0 +1,508 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCPU;
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+
+public class NetList {
+ public static final String NAME_CLK = "signal_clk";
+ public static final String CR = "\n";
+ public static final String CR2 = "\n\n";
+ private static final String NAME_RST = "signal_resetn";
+ private static boolean tracing;
+
+ public static String getNetlist(String icn, boolean _tracing) {
+ int nb_clusters=TopCellGenerator.syscams.getAllCrossbar().size();
+
+ tracing = _tracing;
+
+ String netlist;
+
+ netlist = CR2 + "//------------------------------Netlist---------------------------------" + CR2;
+
+ netlist = netlist + "// icu" + CR2;
+ netlist = netlist + " vcifdtrom.add_property(\"interrupt-parent\", vcifdtrom.get_device_phandle(\"vci_xicu\"));" + CR2;
+
+ netlist = netlist + " vcixicu.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcixicu.p_resetn(signal_resetn);" + CR2;
+ netlist = netlist + " vcixicu.p_vci(signal_vci_xicu);" + CR2;
+
+ netlist = netlist + " vcifdtrom.begin_device_node(\"vci_rttimer\", \"soclib:vci_rttimer\");" + CR;
+
+ netlist = netlist + " vcifdtrom.add_property(\"interrupts\", 4);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " vcifdtrom.begin_device_node(\"vci_xicu\", \"soclib:vci_xicu\");" + CR2;
+ netlist = netlist + " int irq_map[cpus.size() * 3];" + CR;
+ netlist = netlist + " for ( size_t i = 0; i < cpus.size(); ++i )" + CR;
+ netlist = netlist + " {" + CR;
+ netlist = netlist + " irq_map[i*3 + 0] = i;" + CR;
+ netlist = netlist + " irq_map[i*3 + 1] = vcifdtrom.get_cpu_phandle(i);" + CR;
+ netlist = netlist + " irq_map[i*3 + 2] = 0;" + CR;
+ netlist = netlist + " }" + CR2;
+ netlist = netlist + " vcifdtrom.add_property(\"interrupt-map\", irq_map, cpus.size() * 3);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"frequency\", 1000000);" + CR2;
+
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-pti-count\", 1);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-hwi-count\", xicu_n_irq);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-wti-count\", cpus.size());" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"param-int-irq-count\", cpus.size());" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " for ( size_t i = 0; i < xicu_n_irq; ++i )" + CR;
+ netlist = netlist + " vcixicu.p_hwi[i](signal_xicu_irq[i]);" + CR2;
+
+ netlist = netlist + "///////////////// cpus" + CR2;
+
+ netlist = netlist + "vcifdtrom.begin_cpus();" + CR2;
+ netlist = netlist + "for ( size_t i = 0; i < cpus.size(); ++i ){" + CR;
+ netlist = netlist + " // configure het_rom" + CR;
+ netlist = netlist + " vcihetrom.add_srcid(*cpus[i]->text_ldr, IntTab(i));" + CR;
+
+ netlist = netlist + " // add cpu node to device tree" + CR;
+ netlist = netlist + " vcifdtrom.begin_cpu_node(std::string(\"cpu:\") + cpus[i]->type, i);" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"freq\", 1000000);" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + "// connect cpu" + CR;
+ netlist = netlist + " cpus[i]->connect(cpus[i], signal_clk, signal_resetn, signal_vci_m[i]);" + CR;
+ if(icn=="vgmn")
+ {
+ netlist = netlist + "vgmn.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+ else{
+ netlist = netlist + "vgsb.p_to_initiator[i](signal_vci_m[i]);" + CR;
+ }
+
+ netlist = netlist + "vcixicu.p_irq[i](cpus[i]->irq_sig[0]);" + CR;
+ netlist = netlist + " }" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR2;
+
+ netlist = netlist + " vcihetrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcifdtrom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirom.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcisimhelper.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vcirttimer.p_clk(signal_clk);" + CR;
+
+ netlist = netlist + " vcihetrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcifdtrom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirom.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcisimhelper.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcirttimer.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vcihetrom.p_vci(signal_vci_vcihetrom);" + CR;
+
+ netlist = netlist + " vcifdtrom.p_vci(signal_vci_vcifdtrom);" + CR;
+ netlist = netlist + " vcirom.p_vci(signal_vci_vcirom);" + CR;
+ netlist = netlist + " vcisimhelper.p_vci(signal_vci_vcisimhelper);" + CR;
+ netlist = netlist + " vcirttimer.p_vci(signal_vci_vcirttimer);" + CR;
+ netlist = netlist + " vcirttimer.p_irq[0](signal_xicu_irq[4]);" + CR2;
+
+ if(icn=="vgmn"){
+ netlist = netlist + " vgmn.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgmn.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vgmn.p_to_target[0](signal_vci_vcihetrom);" + CR;
+ netlist = netlist + " vgmn.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist = netlist + " vgmn.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist = netlist + " vgmn.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist = netlist + " vgmn.p_to_target[5](signal_vci_vcirttimer);" + CR2;
+ netlist = netlist + " vgmn.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
+ netlist = netlist + " vgmn.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist = netlist + " vgmn.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
+ netlist = netlist + " vgmn.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
+ }
+ else{
+ netlist = netlist + " vgsb.p_clk(signal_clk);" + CR;
+ netlist = netlist + " vgsb.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + " vgsb.p_to_target[0](signal_vci_vcihetrom);" + CR;
+ netlist = netlist + " vgsb.p_to_target[1](signal_vci_vcirom);" + CR;
+ netlist = netlist + " vgsb.p_to_target[3](signal_vci_vcisimhelper);" + CR2;
+ netlist = netlist + " vgsb.p_to_target[4](signal_vci_xicu);" + CR;
+ netlist = netlist + " vgsb.p_to_target[5](signal_vci_vcirttimer);" + CR2;
+ netlist = netlist + " vgsb.p_to_target[6](signal_vci_vcifdtrom);" + CR2;
+ netlist = netlist + " vgsb.p_to_initiator[cpus.size()](signal_vci_bdi);" + CR;
+ netlist = netlist + " vgsb.p_to_initiator[cpus.size()+1](signal_vci_vcifdaccessi);" + CR;
+ netlist = netlist + " vgsb.p_to_initiator[cpus.size()+2](signal_vci_etherneti);" + CR2;
+ }
+
+ if(nb_clusters==0){
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM()) {
+
+ netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ }
+ else{
+ netlist = netlist + "vgsb.p_to_target["+(ram.getNo_target())+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ }
+ }
+ }
+
+ /* clustered version */
+ /* one or several ram, one locks engine, one mwmr ram and one mwmrd ram per cluster*/
+ else{
+ int i;
+ netlist = netlist + "// RAM netlist" + CR2;
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM()) {
+
+ netlist = netlist + ram.getMemoryName()+".p_clk(" + NAME_CLK + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_resetn(" + NAME_RST + ");" + CR;
+ netlist = netlist + ram.getMemoryName()+".p_vci(signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ //target number for local cluster: this is set at avatardd creation
+ netlist = netlist + "crossbar"+ram.getNo_cluster()+".p_to_target["+ram.getNo_target()+"](signal_vci_vciram"+ram.getIndex()+");" + CR2;
+ }
+
+ //one mwmr ram and one mwmrdram per cluster are added transparently
+
+ /*convention for local target ids on cluster :
+ channel: 0
+ mwmr_ram: 1
+ mwmrd_ram: 2
+ locks: 3
+ ram: 4
+ tty: 5
+ */
+
+ /* for(i=0;i<nb_clusters;i++){
+ netlist = netlist + "crossbar"+i+".p_to_target["+1+"](signal_vci_mwmr_ram"+i+");" + CR2;
+ //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
+ netlist = netlist + "crossbar"+i+".p_to_target["+2+"](signal_vci_mwmrd_ram"+i+");" + CR2;
+ //netlist = netlist +"mwmr_ram"+i+".p_irq[0](signal_xicu_irq[0]);" + CR2;
+ } */
+ }
+
+ if(nb_clusters==0){
+ // we can have several TTYs and each is associated to the fdtrom
+
+ /* if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
+ }else{ //vgsb
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target())+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+1)+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(TopCellGenerator.avatardd.getNb_target()+3)+"](signal_vci_vcilocks);" + CR;
+ }*/
+
+ int l=8; //number of last tty ToDo
+ if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+(l)+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(l+1)+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(l+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+(l+3)+"](signal_vci_vcilocks);" + CR;
+ int i;
+ //DG 14.09.
+ int coproc_count=0;
+ for(i=0;i<coproc_count;i++){
+
+ netlist = netlist + "vgmn.p_to_target["+(l+4+i)+"](signal_mwmr_"+i+"_target);" + CR;
+ }
+ }else{ //vgsb
+ netlist = netlist + "vgsb.p_to_target["+(l)+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(l+1)+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(l+2)+"](signal_vci_bdt);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+(l+3)+"](signal_vci_vcilocks);" + CR;
+
+ //DG 14.09.
+ int coproc_count=0;
+ int i;
+ for(i=0;i<coproc_count;i++){
+ netlist = netlist + "vgmn.p_to_target["+(l+4+i)+"](signal_mwmr_"+i+"_target);" + CR;
+ }
+ }
+
+ }else{
+ /* cluster case */
+ if(icn=="vgmn"){
+ netlist = netlist + "vgmn.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+6+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgmn.p_to_target["+7+"](signal_vci_bdt);" + CR;
+ }else{
+ netlist = netlist + "vgsb.p_to_target["+5+"](signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+6+"](signal_vci_ethernett);" + CR;
+ netlist = netlist + "vgsb.p_to_target["+7+"](signal_vci_bdt);" + CR;
+ }
+ }
+ //netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty\",\"soclib:vci_multi_tty\");" + CR2;
+
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 0);" + CR2;
+ netlist = netlist + "vcifdtrom.end_node();;" + CR2;
+
+ netlist = netlist + "// TTY netlist" + CR2;
+ int i=0;
+
+ for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()){
+ netlist = netlist + tty.getTTYName()+".p_clk(signal_clk);" + CR;
+ netlist = netlist + tty.getTTYName()+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist + tty.getTTYName()+".p_vci(signal_vci_tty"+i+");" + CR2;
+ int no_irq_tty=0;
+ if(nb_clusters==0){
+
+ if(icn=="vgmn"){
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+i+"\");" + CR2;
+ netlist = netlist + "vgmn.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
+ netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
+ }else{
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_multi_tty"+i+"\",\"soclib:vci_multi_tty"+tty.getNo_tty()+"\");" + CR2;
+ netlist = netlist + "vgsb.p_to_target["+tty.getNo_target()+"](signal_vci_tty"+i+");" + CR2;
+ netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+no_irq_tty+"]);" + CR2;
+ }
+ }
+
+ //we have a clustered architecture: identify local crossbar
+ else{
+ int j;
+ for(j=0;j<nb_clusters;j++){
+ netlist = netlist + "crossbar"+j+".p_to_target["+tty.getNo_target()+"](signal_vci_tty"+j+");" + CR2;
+ //recalculate irq addresses, 5 devices generating irq per cluster
+ netlist = netlist + tty.getTTYName()+".p_irq[0](signal_xicu_irq["+(tty.getNo_cluster()*5)+"]);" + CR2;
+ }
+ }
+ i++;
+ //One ICU per cluster per default
+ no_irq_tty+=6;//if there is more than one tty, irq >5
+ }
+
+ //////////////// fdrom
+
+ netlist = netlist + "{" + CR2;
+ netlist = netlist + " vcifdtrom.begin_node(\"aliases\");" + CR; netlist = netlist + " vcifdtrom.add_property(\"timer\", vcifdtrom.get_device_name(\"vci_rttimer\") + \"[0]\");" + CR;
+ netlist = netlist + " vcifdtrom.add_property(\"console\", vcifdtrom.get_device_name(\"vci_multi_tty0\") + \"[0]\");" + CR;
+ netlist = netlist + " vcifdtrom.end_node();" + CR;
+ netlist = netlist + "}" + CR2;
+
+ //////////////// ethernet
+
+ netlist = netlist + "vcieth.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcieth.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcieth.p_irq(signal_xicu_irq[3]);" + CR;
+ netlist = netlist + "vcieth.p_vci_target(signal_vci_ethernett);" + CR;
+ netlist = netlist + "vcieth.p_vci_initiator(signal_vci_etherneti);" + CR;
+
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_ethernet\", \"soclib:vci_ethernet\");" + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 3);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// block device
+
+ netlist = netlist + "vcibd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcibd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcibd.p_irq(signal_xicu_irq[1]);" + CR;
+ netlist = netlist + "vcibd.p_vci_target(signal_vci_bdt);" + CR;
+ netlist = netlist + "vcibd.p_vci_initiator(signal_vci_bdi);" + CR;
+
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_block_device\", \"soclib:vci_block_device\");" + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 1);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR;
+
+ //////////////// fd access
+ netlist = netlist + "vcihetrom.add_srcid(*cpus[0]->text_ldr, IntTab(cpus.size()+1));" + CR; /* allows dma read in rodata */
+
+ netlist = netlist + "vcifd.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcifd.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcifd.p_irq(signal_xicu_irq[2]);" + CR;
+ netlist = netlist + "vcifd.p_vci_target(signal_vci_vcifdaccesst);" + CR;
+ netlist = netlist + "vcifd.p_vci_initiator(signal_vci_vcifdaccessi);" + CR;
+
+ netlist = netlist + "vcifdtrom.begin_device_node(\"vci_fd_access\", \"soclib:vci_fd_access\");" + CR;
+ netlist = netlist + "vcifdtrom.add_property(\"interrupts\", 2);" + CR;
+ netlist = netlist + "vcifdtrom.end_node();" + CR2;
+
+ //////////////// locks
+
+ netlist = netlist + "vcilocks.p_clk(signal_clk);" + CR;
+ netlist = netlist + "vcilocks.p_resetn(signal_resetn);" + CR;
+ netlist = netlist + "vcilocks.p_vci(signal_vci_vcilocks);" + CR;
+
+ ////////////////MWMR controller; hypothesis 1 per coprocessor
+ // if(nb_cluster == 0){
+ i=0;
+ int coproc_count=0;
+
+ for (AvatarCoproMWMR copro : TopCellGenerator.syscams.getAllCoproMWMR()){
+ //a coprocessor with its FIFO interface built from HWA
+ netlist = netlist +"hwa"+i+".p_clk(signal_clk);" + CR;
+ netlist = netlist +"hwa"+i+".p_resetn(signal_resetn);" + CR;
+ netlist = netlist +"hwa"+i+".p_from_ctrl["+i+"](signal_fifo_"+i+"_from_ctrl);" + CR;
+ netlist = netlist +"hwa"+i+".p_to_ctrl["+i+"](signal_fifo_"+i+"_to_ctrl);" + CR2;
+
+ //MWMR controller of the HWA
+ netlist = netlist +copro.getCoprocName() +".p_clk(signal_clk);" + CR;
+ netlist = netlist +copro.getCoprocName() +".p_resetn(signal_resetn);" + CR;
+ netlist = netlist +copro.getCoprocName() +".p_vci_initiator(signal_mwmr_"+i+"_initiator);" + CR;
+ netlist = netlist + copro.getCoprocName()+".p_vci_target(signal_mwmr_"+i+"_target);" + CR2;
+ netlist = netlist +copro.getCoprocName() +".p_from_coproc["+i+"](signal_fifo_"+i+"_from_ctrl);" + CR;
+netlist = netlist +copro.getCoprocName() +".p_to_coproc["+i+"](signal_fifo_"+i+"_to_ctrl);" + CR;
+//DG 5.9.
+// netlist = netlist +copro.getCoprocName() +".status();" + CR;
+// netlist = netlist +copro.getCoprocName() +".config();" + CR;
+i++;
+coproc_count++;
+ }
+
+
+ //If there is a spy, add logger or stats to vci interface
+
+ i=0;
+ for (AvatarCPU cpu : TopCellGenerator.syscams.getAllCPU()) {
+ int number = cpu.getNo_proc();
+ if(cpu.getMonitored()==1){
+ netlist=netlist+CR+
+ "logger"+i+".p_clk(signal_clk);" +CR+
+ "logger"+i+".p_resetn(signal_resetn);" +CR+
+ "logger"+i+".p_vci(signal_vci_m["+number+"]);" +CR2;
+ i++;
+ }
+
+ }
+ int j=0;
+
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM()) {
+ if (ram.getMonitored()==1){
+ int number = number = ram.getIndex();
+ netlist += "logger"+i+".p_clk(signal_clk);" + CR;
+ netlist += "logger"+i+".p_resetn(signal_resetn);" + CR;
+ netlist += "logger"+i+".p_vci(signal_vci_vciram"+number+");" + CR2;
+ i++;
+ }
+ else{
+
+ if (ram.getMonitored()==2){
+ int number = number = ram.getIndex();
+ netlist += "mwmr_stats"+j+".p_clk(signal_clk);" + CR;
+ netlist += "mwmr_stats"+j+".p_resetn(signal_resetn);" + CR;
+ netlist += "mwmr_stats"+j+".p_vci(signal_vci_vciram"+number+");" + CR2;
+ j++;
+ }
+ }
+ }
+
+ //if (with_hw_accellerator>0){
+
+ int p=0;
+ //for testing: vci_synthetic_initiator.h and vci_synthetic_target.h
+ //for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
+ /* netlist += "mwmr"+HWAccelerator.getNo()+".p_clk(signal_clk);" + CR;
+ netlist += "mwmr"+HWAccelerator.getNo()+".p_resetn(signal_resetn);" + CR;
+ netlist += "mwmr"+HWAccelerator.getNo()+".p_vci_initiator(signal_mwmr"+HWAccelerator.getNo()+"_initiator);" + CR;
+ netlist += " mwmr"+HWAccelerator.getNo()+".p_vci_target(signal_mwmr"+HWAccelerator.getNo()+"_target);" + CR;
+ netlist += " mwmr"+HWAccelerator.getNo()+".p_from_coproc["+HWAccelerator.getNo()+"](signal_fifo_to_ctrl);" + CR;
+ netlist += " mwmr"+HWAccelerator.getNo()+".p_to_coproc["+HWAccelerator.getNo()+"](signal_fifo_from_ctrl);" + CR;*/
+
+ /* netlist += "mwmr"+p+".p_clk(signal_clk);" + CR;
+ netlist += "mwmr"+p+".p_resetn(signal_resetn);" + CR;
+ netlist += "mwmr"+p+".p_vci_initiator(signal_mwmr"+p+"_initiator);" + CR;
+ netlist += " mwmr"+p+".p_vci_target(signal_mwmr"+p+"_target);" + CR;
+ netlist += " mwmr"+p+".p_from_coproc["+p+"](signal_fifo_"+p+"_to_ctrl);" + CR;
+ netlist += " mwmr"+p+".p_to_coproc["+p+"](signal_fifo_"+p+"_from_ctrl);" + CR;
+ } */
+// }
+
+ //generate trace file if marked trace option
+
+ if(tracing){
+ netlist += "sc_trace_file *tf;" + CR;
+ netlist += "tf=sc_create_vcd_trace_file(\"mytrace\");" + CR;
+ netlist += "sc_trace(tf,signal_clk,\"CLK\");" + CR;
+ netlist += "sc_trace(tf,signal_resetn,\"RESETN\");" + CR;
+
+ netlist += "sc_trace(tf, signal_vci_xicu,\"signal_vci_xicu\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcifdtrom,\"signal_vci_vcifdtrom\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcihetrom,\"signal_vci_vcihetrom\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcirom ,\"signal_vci_vcirom\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcisimhelper,\"signal_vci_vcisimhelper\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcirttimer ,\"signal_vci_vcirttimer\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_vcifdaccessi,\"signal_vci_vcifdaccessi\");" + CR;
+ netlist += "sc_trace(tf,signal_vci_vcifdaccesst ,\"signal_vci_vcifdaccesst\");" + CR;
+ netlist += "sc_trace(tf,signal_vci_bdi ,\"signal_vci_bdi\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_bdt,\"signal_vci_bdt\");" + CR;
+ netlist += "sc_trace(tf, signal_vci_etherneti,\"signal_vci_etherneti\");" + CR;
+ netlist += "sc_trace(tf,signal_vci_ethernett ,\"signal_vci_ethernett\");" + CR;
+
+ for(i=0;i<TopCellGenerator.syscams.getNb_init();i++){
+ netlist += "sc_trace(tf,signal_vci_m["+ i +"] ,\"signal_vci_m["+ i +"]\");" + CR;
+ }
+
+ i=0;
+ for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
+
+ netlist += "sc_trace(tf,signal_vci_tty"+tty.getNo_tty()+",\"TTY"+tty.getNo_tty()+"\");" + CR;
+ netlist += "sc_trace(tf,signal_xicu_irq["+ i +"] ,\"signal_xicu_irq["+ i +"]\");" + CR;
+ i++;
+ }
+
+ netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
+ netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
+ netlist += "sc_trace(tf,signal_xicu_irq["+i+"] ,\"signal_xicu_irq["+i+"]\");" + CR;
+
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM()) {
+ if (ram.getMonitored()==0){
+ netlist += "sc_trace(tf,signal_vci_vciram"+ram.getIndex()+",\"Memory"+ram.getIndex()+"\");" + CR;
+ }
+ }
+ }
+ netlist = netlist + " sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = false;" + CR;
+ netlist = netlist + " sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));" + CR;
+ netlist = netlist + " signal_resetn = true;" + CR;
+ netlist = netlist + " sc_core::sc_start();" + CR;
+ if(tracing){
+ netlist += "sc_close_vcd_trace_file(tf);" + CR;
+ }
+ netlist = netlist + CR + " return EXIT_SUCCESS;"+ CR;
+ netlist = netlist +"}" + CR;
+ return netlist;
+ }
+}
\ No newline at end of file
diff --git a/src/main/java/syscamstranslator/toSysCAMS/PrimitiveCode.java b/src/main/java/syscamstranslator/toSysCAMS/PrimitiveCode.java
new file mode 100644
index 0000000000..bfe11d9f48
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/PrimitiveCode.java
@@ -0,0 +1,96 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package syscamstranslator.toSysCAMS;
+
+import java.util.List;
+
+import syscamstranslator.*;
+import ui.syscams.SysCAMSBlockTDF;
+import ui.syscams.SysCAMSPortConverter;
+import ui.syscams.SysCAMSPortTDF;
+
+/**
+ * Class Header
+ * En-t�te des fichiers .h et .cpp
+ * Creation: 14/05/2018
+ * @version 1.0 14/05/2018
+ * @author Irina Kit Yan LEE
+*/
+
+public class PrimitiveCode {
+ static private String codePrimitive;
+ static private String corpsCluster;
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ PrimitiveCode() {}
+
+ public static String getPrimitiveCode(SysCAMSBlockTDF tdf) {
+ if (tdf != null) {
+ codePrimitive = Header.getPrimitiveHeader(tdf) + Corps.getPrimitiveCorps(tdf);
+ } else {
+ codePrimitive = "";
+ }
+ return codePrimitive;
+ }
+
+ public static String getClusterCorps(SysCAMSTCluster cluster) {
+ if (cluster != null) {
+ List<SysCAMSBlockTDF> blocks = cluster.getBlocks();
+
+ corpsCluster = "//-------------------------------Header------------------------------------" + CR2
+ + "#include <systemc-ams>" + CR2;
+
+ for (SysCAMSBlockTDF b : blocks) {
+ corpsCluster = corpsCluster + "#include \"" + b.getValue() + ".h\"" + CR;
+ }
+ corpsCluster = corpsCluster + CR;
+ } else {
+ corpsCluster = "";
+ }
+ return corpsCluster;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Signal.java b/src/main/java/syscamstranslator/toSysCAMS/Signal.java
new file mode 100644
index 0000000000..73fd281b10
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Signal.java
@@ -0,0 +1,163 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+/* This class generates the lines of the topcell where the signals are declared*/
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+import ddtranslatorSoclib.AvatarCoproMWMR;
+import ddtranslatorSoclib.AvatarRAM;
+import ddtranslatorSoclib.AvatarTTY;
+
+public class Signal {
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+ private final static String NAME_CLK = "signal_clk";
+ private static final String NAME_RST = "signal_resetn";
+
+ public static String getSignal() {
+ int nb_clusters = TopCellGenerator.syscams.getAllCrossbar().size();
+ // nb_clusters=2;
+ String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
+
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");" + CR;
+
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");" + CR;
+ signal = signal + " caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");" + CR;
+ signal = signal + " caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");" + CR;
+ signal = signal + " caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");" + CR;
+ // signal = signal +"caba::VciSignals<vci_param>
+ // signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
+ // signal = signal +"caba::VciSignals<vci_param>
+ // signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdaccessi;" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdaccesst;" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_bdi;" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_bdt;" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_etherneti;" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_vci_ethernett;" + CR;
+ signal = signal + "" + CR;
+ signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
+ signal = signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" + CR2;
+ int i = 0;
+ for (AvatarCoproMWMR copro : TopCellGenerator.syscams.getAllCoproMWMR()) {
+ signal = signal + "caba::VciSignals<vci_param> signal_mwmr_" + i + "_initiator;" + CR;
+ signal = signal + "caba::VciSignals<vci_param> signal_mwmr_" + i + "_target;" + CR;
+ signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_" + i + "_from_ctrl;" + CR;
+ signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_" + i + "_to_ctrl;" + CR;
+ i++;
+ }
+
+ if (TopCellGenerator.syscams.getAllCrossbar().size() == 0) {
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
+ i = 0;
+
+ for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
+ // signal = signal + "soclib::caba::VciSignals<vci_param>
+ // signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" +
+ // CR2;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty" + i + "(\"signal_vci_tty" + i
+ + "\");" + CR2;
+ i++;
+ }
+
+ signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+ System.out.print("number of processors : " + TopCellGenerator.syscams.getNbCPU() + "\n");
+ }
+
+ else {
+ for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ + "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
+ i = 0;
+ for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
+ // signal = signal + "soclib::caba::VciSignals<vci_param>
+ // signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" +
+ // CR2;
+ signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty" + i + "(\"signal_vci_tty" + i
+ + "\");" + CR2;
+ i++;
+ }
+ int p = 0;
+ // if (with_hw_accellerator>0){ //DG 23.08.
+ for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.syscams.getAllCoproMWMR()) {
+ // les accellerateurs sont caches car apparaissent uniquement au niveau
+ // DIPLODOCUS
+ // signal = signal + " soclib::caba::VciSignals<vci_param>
+ // signal_mwmr"+HWAccelerator.getNo()+"_target(\"signal_mwmr"+HWAccelerator.getNo()+"_target\""+CR;
+ // signal = signal + " soclib::caba::VciSignals<vci_param>
+ // signal_mwmr"+HWAccelerator.getNo()+"_initiator(\"signal_mwmr"+HWAccelerator.getNo()+"_initiator\""
+ // +CR;
+
+ // signal = signal + " soclib::caba::FifoSignals<uint32_t>
+ // signal_fifo_to_ctrl"+HWAccelerator.getNo()+"(\"signal_fifo_to_ctrl"+HWAccelerator.getNo()+"\");"+CR;
+ // signal = signal + " soclib::caba::FifoSignals<uint32_t>
+ // signal_fifo_from_ctrl"+HWAccelerator.getNo()+"(\"signal_fifo_from_ctrl"+HWAccelerator.getNo()+"\");"+CR;
+
+ signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr" + p + "_target(\"signal_mwmr" + p
+ + "_target\"" + CR;
+ signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr" + p + "_initiator(\"signal_mwmr"
+ + p + "_initiator\"" + CR;
+
+ signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_to_ctrl" + p
+ + "(\"signal_fifo_to_ctrl" + p + "\");" + CR;
+ signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_from_ctrl" + p
+ + "(\"signal_fifo_from_ctrl" + p + "\");" + CR;
+ p++;
+ }
+
+ signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
+ // System.out.print("number of processors : " +
+ // TopCellGenerator.avatardd.getNbCPU()+"\n");
+ System.out.print("number of clusters : " + TopCellGenerator.syscams.getNbClusters() + "\n");
+
+ }
+ return signal;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/Simulation.java b/src/main/java/syscamstranslator/toSysCAMS/Simulation.java
new file mode 100644
index 0000000000..8ab750f451
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/Simulation.java
@@ -0,0 +1,74 @@
+/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ * Daniela Genius, Lip6, UMR 7606
+ *
+ * ludovic.apvrille AT enst.fr
+ * daniela.genius@lip6.fr
+ *
+ * This software is a computer program whose purpose is to allow the
+ * edition of TURTLE analysis, design and deployment diagrams, to
+ * allow the generation of RT-LOTOS or Java code from this diagram,
+ * and at last to allow the analysis of formal validation traces
+ * obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ * from INRIA Rhone-Alpes.
+ *
+ * This software is governed by the CeCILL license under French law and
+ * abiding by the rules of distribution of free software. You can use,
+ * modify and/ or redistribute the software under the terms of the CeCILL
+ * license as circulated by CEA, CNRS and INRIA at the following URL
+ * "http://www.cecill.info".
+ *
+ * As a counterpart to the access to the source code and rights to copy,
+ * modify and redistribute granted by the license, users are provided only
+ * with a limited warranty and the software's author, the holder of the
+ * economic rights, and the successive licensors have only limited
+ * liability.
+ *
+ * In this respect, the user's attention is drawn to the risks associated
+ * with loading, using, modifying and/or developing or reproducing the
+ * software by the user in light of its specific status of free software,
+ * that may mean that it is complicated to manipulate, and that also
+ * therefore means that it is reserved for developers and experienced
+ * professionals having in-depth computer knowledge. Users are therefore
+ * encouraged to load and test the software's suitability as regards their
+ * requirements in conditions enabling the security of their systems and/or
+ * data to be ensured and, more generally, to use and operate it in the
+ * same conditions as regards security.
+ *
+ * The fact that you are presently reading this means that you have had
+ * knowledge of the CeCILL license and that you accept its terms.
+ */
+
+
+
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package ddtranslatorSoclib.toTopCell;
+
+public class Simulation {
+
+ private static String simulation;
+
+ private final static String CR = "\n";
+ private final static String CR2 = "\n\n";
+
+ public Simulation(){
+ }
+
+ public static String getSimulation(){
+ simulation = CR2+ CR2+
+ "/***************************************************************************" + CR +
+ "----------------------------simulation-------------------------" + CR +
+ "***************************************************************************/"+CR2 ;
+ simulation =simulation+"int sc_main (int argc, char *argv[])" + CR + "{" + CR;
+ simulation = simulation +" try {" + CR +" return _main(argc, argv);" + CR + " }" + CR2;
+ simulation =simulation +" catch (std::exception &e) {" + CR + " std::cout << e.what() << std::endl;" + CR + " throw;"+ CR+" }";
+ simulation =simulation+" catch (...) {" + CR;
+ simulation =simulation+"std::cout << \"Unknown exception occured\" << std::endl;" + CR;
+ simulation =simulation+"throw;" + CR;
+ simulation =simulation+"}" + CR;
+ simulation = simulation+ CR +" return 1;"+ CR + "}" ;
+ return simulation;
+ }
+}
diff --git a/src/main/java/syscamstranslator/toSysCAMS/TopCellGenerator.java b/src/main/java/syscamstranslator/toSysCAMS/TopCellGenerator.java
new file mode 100644
index 0000000000..36a2a6aebf
--- /dev/null
+++ b/src/main/java/syscamstranslator/toSysCAMS/TopCellGenerator.java
@@ -0,0 +1,154 @@
+/**Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
+ Daniela Genius, Lip6, UMR 7606
+
+ ludovic.apvrille AT enst.fr
+ daniela.genius@lip6.fr
+
+ This software is a computer program whose purpose is to allow the
+ edition of TURTLE analysis, design and deployment diagrams, to
+ allow the generation of RT-LOTOS or Java code from this diagram,
+ and at last to allow the analysis of formal validation traces
+ obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
+ from INRIA Rhone-Alpes.
+
+ This software is governed by the CeCILL license under French law and
+ abiding by the rules of distribution of free software. You can use,
+ modify and/ or redistribute the software under the terms of the CeCILL
+ license as circulated by CEA, CNRS and INRIA at the following URL
+ "http://www.cecill.info".
+
+ As a counterpart to the access to the source code and rights to copy,
+ modify and redistribute granted by the license, users are provided only
+ with a limited warranty and the software's author, the holder of the
+ economic rights, and the successive licensors have only limited
+ liability.
+
+ In this respect, the user's attention is drawn to the risks associated
+ with loading, using, modifying and/or developing or reproducing the
+ software by the user in light of its specific status of free software,
+ that may mean that it is complicated to manipulate, and that also
+ therefore means that it is reserved for developers and experienced
+ professionals having in-depth computer knowledge. Users are therefore
+ encouraged to load and test the software's suitability as regards their
+ requirements in conditions enabling the security of their systems and/or
+ data to be ensured and, more generally, to use and operate it in the
+ same conditions as regards security.
+
+ The fact that you are presently reading this means that you have had
+ knowledge of the CeCILL license and that you accept its terms.
+*/
+
+/* Generator of the top cell for simulation with SoCLib virtual component
+ library */
+
+/* authors: v1.0 Raja GATGOUT 2014
+ v2.0 Daniela GENIUS, Julien HENON 2015 */
+
+package syscamstranslator.toSysCAMS;
+
+import syscamstranslator.*;
+import syscamstranslator.toSysCAMS.*;
+import ui.syscams.SysCAMSBlockTDF;
+
+import java.io.*;
+import java.util.ArrayList;
+import java.util.LinkedList;
+import java.util.List;
+
+public class TopCellGenerator {
+ // --------------- accessing Avatardd -----------------
+ public static SysCAMSSpecification syscams;
+ // ---------------------------------------------------
+
+ public String VCIparameters;
+ public String config;
+ public String mainFile;
+ public String src;
+ public String top;
+ public String deployinfo;
+ public String deployinfo_map;
+ public String deployinfo_ram;
+ public String platform_desc;
+ public String procinfo;
+ public String nbproc;
+ public final String DOTH = ".h";
+ public final String DOTCPP = ".cpp";
+ public final String SYSTEM_INCLUDE = "#include \"systemc.h\"";
+ public final String CR = "\n";
+ public final String CR2 = "\n\n";
+ public final String SCCR = ";\n";
+ public final String EFCR = "}\n";
+ public final String EFCR2 = "}\n\n";
+ public final String EF = "}";
+ public final String COTE = "";
+ public final String NAME_RST = "signal_resetn";
+ public final String TYPEDEF = "typedef";
+
+ private final static String GENERATED_PATH = "generated_topcell" + File.separator;
+ private boolean tracing;
+
+ public TopCellGenerator(SysCAMSSpecification sys, boolean _tracing) {
+ syscams = sys;
+ tracing = _tracing;
+ }
+
+ public String generateTopCell(SysCAMSTBlockTDF tdf) {
+ /* first test validity of the hardware platform */
+ if (TopCellGenerator.syscams.getNbCluster() == 0) {
+ System.out.println("***Warning: require at least one cluster***");
+ }
+ if (TopCellGenerator.syscams.getNbBlockTDF() == 0) {
+ System.out.println("***Warning: require at least one TDF block***");
+ }
+ if (TopCellGenerator.syscams.getNbPortTDF() == 0) {
+ System.out.println("***Warning: require at least one TDF port***");
+ }
+ if (TopCellGenerator.syscams.getNbBlockDE() == 0) {
+ System.out.println("***Warning: require at least one DE block***");
+ }
+ if (TopCellGenerator.syscams.getNbPortDE() == 0) {
+ System.out.println("***Warning: require at least one DE port***");
+ }
+ if (TopCellGenerator.syscams.getNbPortConverter() == 0) {
+ System.out.println("***Warning: require at least one converter port***");
+ }
+ String top = Header.getPrimitiveHeader(tdf) + Corps.getPrimitiveCorps(tdf);
+ return (top);
+ }
+
+ public static void saveFile(String path) {
+// try {
+// System.err.println(path + GENERATED_PATH + "top.cc");
+// FileWriter fw = new FileWriter(path + GENERATED_PATH + "/top.cc");
+// top = generateTopCell();
+// fw.write(top);
+// fw.close();
+// } catch (IOException ex) {
+// }
+ saveFileBlockTDF(path);
+ }
+
+ public static void saveFileBlockTDF(String path) {
+ LinkedList<SysCAMSTCluster> clusters = TopCellGenerator.syscams.getAllCluster();
+ String code;
+
+ for (SysCAMSTCluster c : clusters) {
+ List<SysCAMSBlockTDF> tdf = c.getBlocks();
+ for (SysCAMSBlockTDF t : tdf) {
+ try {
+ System.err.println(path + GENERATED_PATH + t.getValue() + ".h");
+ FileWriter fw = new FileWriter(path + GENERATED_PATH + "/" + t.getValue() + ".h");
+ code = PrimitiveCode.getPrimitiveCode(t);
+ fw.write(code);
+ fw.close();
+ } catch (Exception ex) {
+ ex.printStackTrace();
+ }
+ }
+ }
+ }
+
+ public static void main (String[] args) {
+ saveFile("/main/syscamstranslator/");
+ }
+}
--
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