Merge requests · mbe-tools / TTool

add blank between braces and else

!428 · created Jun 23, 2022 by Jawher Jerray
- MERGED
- 0
updated Jun 23, 2022
add save-status-in-file command

!427 · created Jun 23, 2022 by Jawher Jerray
- MERGED
- Approved
- 0
updated Jun 23, 2022
Definitions.h

!426 · created Mar 11, 2022 by Ludovic Apvrille
- MERGED
- Approved
- 0
updated Mar 11, 2022
Bug resolution on String parsing in avatartranslator/AvatarGuard.java

!425 · created Oct 22, 2021 by Bastien Sultan AVATAR
- MERGED
- Approved
- 0
updated Oct 22, 2021
restore original state when uncheck time duration box

!424 · created Aug 09, 2021 by Le Van Truong
- MERGED
- 0
updated Aug 09, 2021
add validate button to timeline diagram

!423 · created Aug 09, 2021 by Le Van Truong
- MERGED
- Approved
- 0
updated Aug 09, 2021
Issue #313: Add option to display the trace in a selected duration

!421 · created Jul 02, 2021 by Le Van Truong
- MERGED
- 0
updated Jul 15, 2021
Issue #327: CPU issues with penalty

!420 · created Jul 01, 2021 by Le Van Truong
- MERGED
- Approved
- 0
updated Jul 01, 2021
Issue #322: Bus Slicetime has wrong configuration, and remove terminated status and blank lines when using -help, -helpserver, -helpcomamnd

!419 · created Jun 21, 2021 by Le Van Truong
- MERGED
- Approved
- 0
updated Jun 23, 2021
Bug resolution on TML to UPPAAL translation

!418 · created Jun 21, 2021 by Bastien Sultan
- MERGED
- 0
updated Jun 21, 2021
Issue #324 and #325: detect invalid parameters and remove redundant information

!416 · created Jun 17, 2021 by Le Van Truong
- MERGED
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updated Jun 17, 2021
Issue #317: Upgrade TTool help

!415 · created Jun 16, 2021 by Le Van Truong
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updated Jun 16, 2021
Issue #317 - Integrated helpserver and helpcommand

!414 · created Jun 07, 2021 by Le Van Truong
- MERGED
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updated Jun 08, 2021
Adding new displaying option for timeline diagram (with and without reduce idle time) and Moving tests from ui.tml to tmltranslator

!413 · created Apr 29, 2021 by Le Van Truong
- MERGED
- 0
updated Apr 30, 2021
Revert "Merge branch 'revert-883077ef' into 'master'"

!412 · created Apr 27, 2021 by Ludovic Apvrille
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updated Apr 27, 2021
Adding new displaying option for timeline diagram (with and without reduce idle time) and Moving tests from ui.tml to tmltranslator

!411 · created Apr 23, 2021 by Le Van Truong
- MERGED
- 0
updated Apr 27, 2021
Issue #306: add clock divider value to FPGA

!410 · created Apr 12, 2021 by Le Van Truong
- MERGED
- Approved
- 0
updated Apr 13, 2021
Lip6

!409 · created Mar 18, 2021 by Daniela Genius
- MERGED
- 0
updated Mar 24, 2021
Fix Multi-core Cross Scheduling And Modify The Tests

!408 · created Mar 17, 2021 by Le Van Truong
- MERGED
- 0
updated Mar 18, 2021
Plan test

!406 · created Mar 12, 2021 by Maysam Zoor
- MERGED
- 0
updated Mar 12, 2021