Commit a82f08b7 authored by Ludovic Apvrille's avatar Ludovic Apvrille

Update on tests

parent f37b25cb
// Master clock frequency - in MHz
MASTERCLOCKFREQUENCY 200
NODE MEMORY Memory0
SET Memory0 byteDataSize 4
NODE BUS Bus0
SET Bus0 byteDataSize 4
SET Bus0 pipelineSize 1
SET Bus0 arbitration 0
NODE CPU CPU1
SET CPU1 nbOfCores 1
SET CPU1 byteDataSize 4
SET CPU1 pipelineSize 5
SET CPU1 goIdleTime 10
SET CPU1 maxConsecutiveIdleCycles 10
SET CPU1 taskSwitchingTime 20
SET CPU1 branchingPredictionPenalty 2
SET CPU1 cacheMiss 5
SET CPU1 schedulingPolicy 0
SET CPU1 sliceTime 10000
SET CPU1 execiTime 1
SET CPU1 execcTime 1
NODE CPU CPU0
SET CPU0 nbOfCores 1
SET CPU0 byteDataSize 4
SET CPU0 pipelineSize 5
SET CPU0 goIdleTime 10
SET CPU0 maxConsecutiveIdleCycles 10
SET CPU0 taskSwitchingTime 20
SET CPU0 branchingPredictionPenalty 2
SET CPU0 cacheMiss 18
SET CPU0 schedulingPolicy 0
SET CPU0 sliceTime 10000
SET CPU0 execiTime 1
SET CPU0 execcTime 1
NODE HWA HWA0
SET HWA0 byteDataSize 4
SET HWA0 execiTime 1
SET HWA0 execcTime 1
NODE LINK link_CPU0_to_Bus0
SET link_CPU0_to_Bus0 node CPU0
SET link_CPU0_to_Bus0 bus Bus0
SET link_CPU0_to_Bus0 priority 0
NODE LINK link_CPU1_to_Bus0
SET link_CPU1_to_Bus0 node CPU1
SET link_CPU1_to_Bus0 bus Bus0
SET link_CPU1_to_Bus0 priority 0
NODE LINK link_Memory0_to_Bus0
SET link_Memory0_to_Bus0 node Memory0
SET link_Memory0_to_Bus0 bus Bus0
SET link_Memory0_to_Bus0 priority 0
NODE LINK link_HWA0_to_Bus0
SET link_HWA0_to_Bus0 node HWA0
SET link_HWA0_to_Bus0 bus Bus0
SET link_HWA0_to_Bus0 priority 0
TMLSPEC
#include "spec.tml"
ENDTMLSPEC
TMLARCHI
#include "spec.tarchi"
ENDTMLARCHI
TMLMAPPING
MAP CPU1 AppC__InterfaceDevice
SET AppC__InterfaceDevice priority 0
MAP CPU0 AppC__TCPIP
SET AppC__TCPIP priority 0
MAP CPU0 AppC__Application
SET AppC__Application priority 0
MAP CPU0 AppC__SmartCard
SET AppC__SmartCard priority 0
MAP HWA0 AppC__Timer
SET AppC__Timer priority 0
ENDTMLMAPPING
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