Commit b5ebf4a7 authored by Ludovic Apvrille's avatar Ludovic Apvrille

Merge branch 'fpga_change_simulator' into 'master'

Fpga change simulator

See merge request !163
parents f1bda6a9 7615c6b9
...@@ -24,7 +24,7 @@ OS := $(shell uname) ...@@ -24,7 +24,7 @@ OS := $(shell uname)
MODULE = run MODULE = run
include Makefile.src include Makefile.src
SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/RRPrioScheduler.cpp arch/OrderScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp SRCS_base = app/TMLTask.cpp app/TMLCommand.cpp TMLTransaction.cpp app/TMLChannel.cpp arch/SchedulableDevice.cpp arch/CPU.cpp arch/FPGA.cpp arch/SingleCoreCPU.cpp arch/MultiCoreCPU.cpp app/TMLWriteCommand.cpp app/TMLWriteMultCommand.cpp app/TMLStateChannel.cpp app/TMLbrbwChannel.cpp app/TMLnbrnbwChannel.cpp app/TMLbrnbwChannel.cpp app/TMLReadCommand.cpp app/TMLExeciCommand.cpp app/TMLExeciRangeCommand.cpp app/TMLActionCommand.cpp app/TMLChoiceCommand.cpp app/TMLRandomChoiceCommand.cpp app/TMLWaitCommand.cpp app/TMLSendCommand.cpp app/TMLSelectCommand.cpp app/TMLRequestCommand.cpp app/TMLNotifiedCommand.cpp app/TMLRandomCommand.cpp app/TMLStopCommand.cpp arch/Bus.cpp definitions.cpp arch/Bridge.cpp arch/Memory.cpp Comment.cpp sim/Server.cpp sim/ServerLocal.cpp sim/Simulator.cpp sim/SimComponents.cpp sim/ServerIF.cpp evt/ListenersSimCmd.cpp arch/PrioScheduler.cpp arch/RRScheduler.cpp arch/OrderScheduler.cpp arch/RRPrioScheduler.cpp arch/WorkloadSource.cpp TEPE/AliasConstraint.cpp TEPE/EqConstraint.cpp TEPE/FSMConstraint.cpp TEPE/PropertyConstraint.cpp TEPE/PropertyStateConstraint.cpp TEPE/PropLabConstraint.cpp TEPE/PropRelConstraint.cpp TEPE/SignalConstraint.cpp TEPE/ThreeSigConstraint.cpp TEPE/TimeMMConstraint.cpp TEPE/TimeTConstraint.cpp TEPE/TwoSigConstraint.cpp
SRCS_base_DIR = src_simulator SRCS_base_DIR = src_simulator
SRCS_generated = . SRCS_generated = .
......
...@@ -107,7 +107,7 @@ bool Bus::addTransaction(TMLTransaction* iTransToBeAdded){ ...@@ -107,7 +107,7 @@ bool Bus::addTransaction(TMLTransaction* iTransToBeAdded){
#endif #endif
_nextTransaction = 0; _nextTransaction = 0;
_schedulingNeeded=true; _schedulingNeeded=true;
//std::cout << "End Bus add trans\n"; std::cout << "End Bus add trans\n";
return true; return true;
} }
......
This diff is collapsed.
...@@ -71,9 +71,6 @@ public: ...@@ -71,9 +71,6 @@ public:
\param iID ID of the device \param iID ID of the device
\param iName Name of the device \param iName Name of the device
\param iScheduler Pointer to the scheduler object \param iScheduler Pointer to the scheduler object
\param iTimePerCycle 1/Processor frequency
\param iMapCapacity Pointer to the overall mapping capacity ????
\param iMapPenalty Pointer to the mapping penalty ????
\param iReconfigTime reconfiguration time \param iReconfigTime reconfiguration time
\param iChangeIdleModeCycles Cycles needed to switch into indle mode \param iChangeIdleModeCycles Cycles needed to switch into indle mode
\param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle \param iCyclesBeforeIdle Pointer to the max consecutive cycles before idle in cycle
...@@ -81,7 +78,7 @@ public: ...@@ -81,7 +78,7 @@ public:
\param iCyclesPerExecc Cycles needed to execute one EXECC unit \param iCyclesPerExecc Cycles needed to execute one EXECC unit
*/ */
FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iTimePerCycle, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc); FPGA(ID iID, std::string iName, WorkloadSource* iScheduler, TMLTime iReconfigTime, unsigned int iChangeIdleModeCycles, unsigned int iCyclesBeforeIdle,unsigned int iCyclesPerExeci, unsigned int iCyclesPerExecc);
///Destructor ///Destructor
virtual ~FPGA(); virtual ~FPGA();
///Determines the next FPGA transaction to be executed ///Determines the next FPGA transaction to be executed
...@@ -130,10 +127,18 @@ public: ...@@ -130,10 +127,18 @@ public:
_taskList.push_back(iTask); _taskList.push_back(iTask);
if (_scheduler!=0) _scheduler->addWorkloadSource(iTask); if (_scheduler!=0) _scheduler->addWorkloadSource(iTask);
} }
inline void setTransNumber(unsigned int num) { _transNumber=num;}
inline unsigned int getTransNumber() { return _transNumber;}
double averageLoad (TMLTask* currTask) const;
void drawPieChart(std::ofstream& myfile) const;
void showPieChart(std::ofstream& myfile) const;
void schedule2HTML(std::ofstream& myfile) const;
inline const TaskList& getTaskList() const{return _taskList;}
inline void setHtmlCurrTask(TMLTask *t) { _htmlCurrTask=t;}
protected: protected:
///List of all tasks running on the FPGA ///List of all tasks running on the FPGA
TaskList _taskList; TaskList _taskList;
TMLTask* _htmlCurrTask;
/** /**
\param iTime Indicates at what time the transaction should be truncated \param iTime Indicates at what time the transaction should be truncated
*/ */
...@@ -142,12 +147,11 @@ protected: ...@@ -142,12 +147,11 @@ protected:
/** /**
\param iTimeSlice FPGA Time slice granted by the scheduler \param iTimeSlice FPGA Time slice granted by the scheduler
*/ */
void calcStartTimeLength(TMLTime iTimeSlice); void calcStartTimeLength();
///1/Processor frequency
TMLTime _timePerCycle;
TMLTime _reconfigTime; TMLTime _reconfigTime;
///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy ///Determines the correct bus master of this CPU connected to the same bus as bus master iDummy
/** /**
\param iDummy Dummy Bus Master \param iDummy Dummy Bus Master
...@@ -159,22 +163,25 @@ protected: ...@@ -159,22 +163,25 @@ protected:
TMLTransaction* _lastTransaction; TMLTransaction* _lastTransaction;
///List of bus masters ///List of bus masters
BusMasterList _busMasterList; BusMasterList _busMasterList;
#ifdef PENALTIES_ENABLED
///Cycles needed to switch to idle mode ///Cycles needed to switch to idle mode
unsigned int _changeIdleModeCycles; unsigned int _changeIdleModeCycles;
///Idle cycles which elapse before entering idle mode ///Idle cycles which elapse before entering idle mode
unsigned int _cyclesBeforeIdle; unsigned int _cyclesBeforeIdle;
#endif
///Cycles needed to execute one execi unit ///Cycles needed to execute one execi unit
unsigned int _cyclesPerExeci; unsigned int _cyclesPerExeci;
unsigned int _cyclesPerExecc;
///Time needed to execute one execi unit ///Time needed to execute one execi unit
float _timePerExeci; float _timePerExeci;
#ifdef PENALTIES_ENABLED
///Idle time which elapses before entering idle mode ///Idle time which elapses before entering idle mode
TMLTime _timeBeforeIdle; TMLTime _timeBeforeIdle;
///Time needed to switch into idle mode ///Time needed to switch into idle mode
TMLTime _changeIdleModeTime; TMLTime _changeIdleModeTime;
#endif unsigned int _transNumber;
///State variable for the VCD output ///State variable for the VCD output
vcdFPGAVisState _vcdOutputState; vcdFPGAVisState _vcdOutputState;
}; };
......
...@@ -293,7 +293,13 @@ protected: ...@@ -293,7 +293,13 @@ protected:
\param oResultDevice Pointer to the CPU which is running the returned transaction \param oResultDevice Pointer to the CPU which is running the returned transaction
\return Pointer to transaction with lowest end time \return Pointer to transaction with lowest end time
*/ */
TMLTransaction* getTransLowestEndTime(SchedulableDevice*& oResultDevice) const; TMLTransaction* getTransLowestEndTimeCPU(SchedulableDevice*& oResultDevice) const;
///Returns a pointer to the transaction with the lowest end time proposed by FPGA schedulers
/**
\param oResultDevice Pointer to the FPGA which is running the returned transaction
\return Pointer to transaction with lowest end time
*/
TMLTransaction* getTransLowestEndTimeFPGA(SchedulableDevice*& oResultDevice) const;
///Decodes a simulation command ///Decodes a simulation command
/** /**
\param iCmd Pointer to the command \param iCmd Pointer to the command
......
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