updated test

fr.mem4csd.osatedim.tests/cases/mc-dag/delta-inplace/declarative.aadl

@@ -36,26 +36,6 @@ public
 			Deadline => 1600ms applies to proc;
 			Actual_Processor_Binding => (reference (cpu)) applies to proc;
 			Actual_Memory_Binding => (reference (cpu.internal_memory)) applies to proc;
-
-	RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core2); Start_Time => 600ms;
-					End_Time => 800ms;]) in modes (LO) applies to proc.tg_phase1.GPS;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core2); Start_Time => 800ms;
-					End_Time => 1000ms;]) in modes (LO) applies to proc.tg_phase1.Rec;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core1); Start_Time => 300ms;
-					End_Time => 900ms;]) in modes (LO), ([Computation_Unit => reference (cpu.core1); Start_Time => 300ms;
-					End_Time => 1100ms;]) in modes (HI) applies to proc.tg_phase1.Nav;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core1); Start_Time => 1300ms;
-					End_Time => 1600ms;]) in modes (LO) applies to proc.tg_phase1.Com;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core2); Start_Time => 0ms;
-					End_Time => 600ms;]) in modes (LO) applies to proc.tg_phase1.Video;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core1); Start_Time => 900ms;
-					End_Time => 1100ms;]) in modes (LO), ([Computation_Unit => reference (cpu.core1);
-					Start_Time => 1100ms; End_Time => 1600ms;]) in modes (HI) applies to proc.tg_phase1.Stab;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core1); Start_Time => 1100ms;
-					End_Time => 1300ms;]) in modes (LO) applies to proc.tg_phase1.Log;
-			RAMSES_properties::Execution_Slots => ([Computation_Unit => reference (cpu.core1); Start_Time => 0ms;
-					End_Time => 300ms;]) in modes (LO), ([Computation_Unit => reference (cpu.core1); Start_Time => 0ms;
-					End_Time => 300ms;]) in modes (HI) applies to proc.tg_phase1.Avoid;
 	end main.impl;
 
 	system multicore
@@ -70,7 +50,6 @@ public
 			core2: processor cpu {Frame_Period => 1600ms;};
 			internal_memory: memory mem;
 		properties
-			RAMSES_properties::Is_Processor => true;
 			Scheduling_Protocol => (static);
 	end multicore.impl;
 
@@ -85,7 +64,6 @@ public
 			tfe: in event port;
 			recovery: in event port;
 			to_phase1: in event port;
-		
 	end proc;
 
 	data position extends Integer