Commit ee0480e1 authored by Renaud Pacalet's avatar Renaud Pacalet
Browse files

synthesis tests of ldpc_shuffle

parent 3d81bdea
......@@ -303,6 +303,10 @@ $$($(1)-name).sim: $$($(1)-name)
endef
$(foreach f,$(SRC),$(eval $(call VHD_rule,$(f))))
$(info ldpc/ldpc_shuffle_wrapper.vhd-name = $(ldpc/ldpc_shuffle_wrapper.vhd-name))
$(info ldpc_shuffle_wrapper-lib = $(ldpc_shuffle_wrapper-lib))
$(info VHDL = $(VHDL))
.PHONY: $(addprefix .sim,$(NAME))
# compile all VHDL source files
......
......@@ -18,4 +18,6 @@ ldpc_shuffle: ldpc_pkg
ldpc_shuffle_sim: ldpc_pkg ldpc_shuffle utils_pkg rnd_pkg
ldpc_shuffle_wrapper: ldpc_pkg ldpc_shuffle utils_pkg
# vim: set tabstop=4 softtabstop=4 shiftwidth=4 noexpandtab textwidth=0:
......@@ -29,7 +29,7 @@ use common.utils_pkg.all;
package ldpc_pkg is
constant bit_width: positive := 8; -- bit-width of messages
constant bit_width: positive range 1 to 8 := 8; -- bit-width of messages
constant max_degree: positive := 22; -- maximum row degree of parity check matrix (802.11n R=5/6, Z=54)
constant min_num_block_rows: positive := 4;
constant max_num_block_rows: positive := 46;
......
......@@ -9,8 +9,7 @@ use work.ldpc_pkg.all;
entity ldpc_shuffle is
generic(
m: positive := max_z; -- maximum lifting factor
log2_up_m: natural := log2_up_max_z -- log2 of m
m: positive range min_z to max_z := max_z -- maximum lifting factor
);
port(
din: in message_vector(0 to m - 1);
......@@ -18,6 +17,7 @@ entity ldpc_shuffle is
r: in natural range 0 to m - 1;
dout: out message_vector(0 to m - 1)
);
constant log2_up_m: natural := log2_up(m); -- log2 of m
end entity ldpc_shuffle;
architecture beh of ldpc_shuffle is
......
......@@ -10,15 +10,13 @@ use work.ldpc_pkg.all;
entity ldpc_shuffle_sim is
generic(
m: positive := max_z; -- maximum lifting factor
m: positive range min_z to max_z := max_z; -- maximum lifting factor
n: positive := 10000 -- number of test vectors
);
end entity ldpc_shuffle_sim;
architecture sim of ldpc_shuffle_sim is
constant log2_up_m: natural := log2_up(m);
signal din, dout_beh, dout_rtl: message_vector(0 to m - 1);
signal z: natural range min_z to m;
signal r: natural range 0 to m - 1;
......@@ -27,8 +25,7 @@ begin
s_beh: entity work.ldpc_shuffle(beh)
generic map(
m => m,
log2_up_m => log2_up_m
m => m
)
port map(
din => din,
......@@ -39,8 +36,7 @@ begin
s_rtl: entity work.ldpc_shuffle(rtl)
generic map(
m => m,
log2_up_m => log2_up_m
m => m
)
port map(
din => din,
......
#
# Copyright (C) Telecom Paris
# Copyright (C) Renaud Pacalet (renaud.pacalet@telecom-paris.fr)
#
# This file must be used under the terms of the CeCILL. This source
# file is licensed as described in the file COPYING, which you should
# have received as part of this distribution. The terms are also
# available at:
# http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
#
set frequency_mhz 250
# vim: set tabstop=4 softtabstop=4 shiftwidth=4 noexpandtab textwidth=0:
# MASTER-ONLY: DO NOT MODIFY THIS FILE
#
# Copyright (C) Telecom Paris
# Copyright (C) Renaud Pacalet (renaud.pacalet@telecom-paris.fr)
#
# This file must be used under the terms of the CeCILL. This source
# file is licensed as described in the file COPYING, which you should
# have received as part of this distribution. The terms are also
# available at:
# http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
#
set board [get_board_parts xilinx.com:zc706:part0:1.4]
set part xc7z045ffg900-2
proc usage {} {
puts "
usage: vivado -mode batch -source <script>
<script>: TCL script"
exit -1
}
set script [file normalize [info script]]
set dir [file dirname $script]
set root [file dirname $dir]
regsub {\..*} [file tail $script] "" design
set params $dir/$design.params.tcl
if [file exists $params] {
source $params
} else {
set frequency_mhz 125
}
if { $argc != 0 } {
usage
}
puts "*********************************************"
puts "Summary of build parameters"
puts "*********************************************"
puts "Board: $board"
puts "Part: $part"
puts "Root directory: $dir"
puts "Design name: $design"
puts "Frequency: $frequency_mhz MHz"
puts "*********************************************"
#############
# Create IP #
#############
set_part $part
set_property board_part $board [current_project]
read_vhdl -vhdl2008 $root/common/utils_pkg.vhd
read_vhdl -vhdl2008 $dir/ldcp_pkg.vhd
read_vhdl -vhdl2008 $dir/ldcp_shuffle.vhd
read_vhdl -vhdl2008 $dir/ldcp_shuffle_wrapper.vhd
# set_property top $design [current_fileset]
# reorder_files -auto -disable_unused
ipx::package_project -force_update_compile_order -import_files -root_dir $design -vendor www.telecom-paris.fr -library EMBB -force $design
close_project
############################
## Create top level design #
############################
set top ${design}_top
set_part $part
set_property board_part $board [current_project]
set_property ip_repo_paths [list ./$design] [current_fileset]
update_ip_catalog
create_bd_design $top
set ip [create_bd_cell -type ip -vlnv [get_ipdefs *www.telecom-paris.fr:EMBB:$design:*] $design]
set ps7 [create_bd_cell -type ip -vlnv [get_ipdefs *xilinx.com:ip:processing_system7:*] ps7]
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $ps7
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ $frequency_mhz] $ps7
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP0 {1}] $ps7
set_property -dict [list CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {1}] $ps7
# set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_IRQ_F2P_INTR {1}] [get_bd_cells ps7]
# Interconnections
# ps7 - ip
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/ps7/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins /$ip/s0_axi]
# connect_bd_net [get_bd_pins /$ip/irq] [get_bd_pins ps7/IRQ_F2P]
# Addresses ranges
set_property offset 0x40000000 [get_bd_addr_segs -of_object [get_bd_intf_pins /ps7/M_AXI_GP0]]
set_property range 4K [get_bd_addr_segs -of_object [get_bd_intf_pins /ps7/M_AXI_GP0]]
# Synthesis flow
validate_bd_design
save_bd_design
generate_target all [get_files $top.bd]
make_wrapper -top [get_files $top.bd] -import -force
write_hwdef -file $design.hwdef
synth_design -top $top
# Clocks and timing
set clock [get_clocks]
# Implementation
opt_design
place_design
route_design
# Reports
report_utilization -force -file $design.utilization.rpt
report_timing_summary -file $design.timing.rpt
# Bitstream
write_bitstream -force $design
write_sysdef -force -bitfile $design.bit -hwdef $design.hwdef $design.sysdef
# Messages
puts ""
puts "*********************************************"
puts "\[VIVADO\]: done"
puts "*********************************************"
puts "Summary of build parameters"
puts "*********************************************"
puts "Board: $board"
puts "Part: $part"
puts "Root directory: $dir"
puts "Design name: $design"
puts "Frequency: $frequency_mhz MHz"
puts "*********************************************"
puts " bitstream in $design.bit"
puts " hardware definition file in $design.hwdef"
puts " system definition file in $design.sysdef"
puts " resource utilization report in $design.utilization.rpt"
puts " timing report in $design.timing.rpt"
puts "*********************************************"
# Quit
quit
# vim: set tabstop=4 softtabstop=4 shiftwidth=4 noexpandtab textwidth=0:
--
-- Copyright (C) Telecom Paris
-- Copyright (C) Renaud Pacalet (renaud.pacalet@telecom-paris.fr)
--
-- This file must be used under the terms of the CeCILL. This source
-- file is licensed as described in the file COPYING, which you should
-- have received as part of this distribution. The terms are also
-- available at:
-- http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
--
-- Synthesis test of ldpc_shuffle.
--
-- Address map:
-- 0x000 - 0x17f: input/output data register
-- 0x180 - 0x183: z register
-- 0x184 - 0x187: r register
-- 0x188 - 0x1ff: unmapped
--
-- when the r register is written the z leftmost bytes of the data register are
-- rotated left by r positions and stored back in the data register. the 23
-- leftmost bits of the z and r registers are ignored. the z value shall be in
-- the 2 to 284 range. the r value shall be in the 0 to z-1 range.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ldpc_pkg.all;
entity ldpc_shuffle_wrapper is
generic(
m: positive range min_z to max_z := max_z -- maximum lifting factor
);
port(
aclk: in std_ulogic;
aresetn: in std_ulogic;
s0_axi_araddr: in std_ulogic_vector(11 downto 0);
s0_axi_arvalid: in std_ulogic;
s0_axi_arready: out std_ulogic;
s0_axi_awaddr: in std_ulogic_vector(11 downto 0);
s0_axi_awvalid: in std_ulogic;
s0_axi_awready: out std_ulogic;
s0_axi_wdata: in std_ulogic_vector(31 downto 0);
s0_axi_wstrb: in std_ulogic_vector(3 downto 0);
s0_axi_wvalid: in std_ulogic;
s0_axi_wready: out std_ulogic;
s0_axi_rdata: out std_ulogic_vector(31 downto 0);
s0_axi_rresp: out std_ulogic_vector(1 downto 0);
s0_axi_rvalid: out std_ulogic;
s0_axi_rready: in std_ulogic;
s0_axi_bresp: out std_ulogic_vector(1 downto 0);
s0_axi_bvalid: out std_ulogic;
s0_axi_bready: in std_ulogic
);
end entity ldpc_shuffle_wrapper;
architecture rtl of ldpc_shuffle_wrapper is
constant axi_resp_okay: std_ulogic_vector(1 downto 0) := "00";
constant axi_resp_exokay: std_ulogic_vector(1 downto 0) := "01";
constant axi_resp_slverr: std_ulogic_vector(1 downto 0) := "10";
constant axi_resp_decerr: std_ulogic_vector(1 downto 0) := "11";
type states is (idle, waiting);
signal state_r, state_w: states;
signal reg, dout: message_vector(0 to m - 1);
signal z: natural range min_z to m;
signal r: natural range 0 to m - 1;
signal en: std_ulogic;
begin
u_ldpc_shuffle: entity work.ldpc_shuffle(rtl)
generic map(
m => max_z
)
port map(
din => reg,
z => z,
r => r,
dout => dout
);
process(aclk)
variable add: natural range 0 to 2**10 - 1;
begin
if rising_edge(aclk) then
s0_axi_awready <= '0';
s0_axi_wready <= '0';
en <= '0';
if aresetn = '0' then
reg <= (others => 0);
z <= min_z;
r <= 0;
s0_axi_bresp <= axi_resp_okay;
s0_axi_bvalid <= '0';
state_w <= idle;
else
case state_w is
when idle =>
if s0_axi_awvalid = '1' and s0_axi_wvalid = '1' then
s0_axi_awready <= '1';
s0_axi_wready <= '1';
s0_axi_bvalid <= '1';
add := to_integer(unsigned(s0_axi_awaddr(11 downto 2)));
if add = 96 then
z <= to_integer(unsigned(s0_axi_wdata(8 downto 0)));
elsif add = 97 then
r <= to_integer(unsigned(s0_axi_wdata(8 downto 0)));
en <= '1';
elsif add < 96 then
for i in 0 to 3 loop
reg(4 * add + i) <= to_integer(signed(s0_axi_wdata(8 * i + 7 downto 8 * i)));
end loop;
else
s0_axi_bresp <= axi_resp_slverr;
end if;
state_w <= waiting;
end if;
when waiting =>
if s0_axi_bready = '1' then
s0_axi_bvalid <= '0';
state_w <= idle;
end if;
end case;
if en = '1' then
reg <= dout;
end if;
end if;
end if;
end process;
process(aclk)
variable add: natural range 0 to 2**10 - 1;
begin
if rising_edge(aclk) then
s0_axi_arready <= '0';
if aresetn = '0' then
state_r <= idle;
s0_axi_rresp <= axi_resp_okay;
s0_axi_rvalid <= '0';
s0_axi_rdata <= (others => '0');
else
case state_r is
when idle =>
if s0_axi_arvalid = '1' then
s0_axi_arready <= '1';
s0_axi_rvalid <= '1';
add := to_integer(unsigned(s0_axi_araddr(11 downto 2)));
if add = 96 then
s0_axi_rdata <= std_ulogic_vector(to_unsigned(z, 32));
s0_axi_rresp <= axi_resp_okay;
elsif add = 97 then
s0_axi_rdata <= std_ulogic_vector(to_unsigned(r, 32));
s0_axi_rresp <= axi_resp_okay;
elsif add < 96 then
for i in 0 to 3 loop
s0_axi_rdata(8 * i + 7 downto 8 * i) <= std_ulogic_vector(to_signed(reg(4 * add + i), 8));
end loop;
s0_axi_rresp <= axi_resp_okay;
else
s0_axi_rdata <= (others => '0');
s0_axi_rresp <= axi_resp_slverr;
end if;
state_r <= waiting;
end if;
when waiting =>
if s0_axi_rready = '1' then
s0_axi_rvalid <= '0';
state_r <= idle;
end if;
end case;
end if;
end if;
end process;
end architecture rtl;
-- vim: set tabstop=4 softtabstop=4 shiftwidth=4 expandtab textwidth=0:
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