--* adc_emulator emulates a AD converter. It generates a sampling clock rxclk, a valid signal rxvalid and 32 bits data samples rxdata. The data samples are
--* supposed to be sampled on rising edges of rxclk for which rxvalid is set. rxvalid is generated randomly but in such a way that two consecutive sampling
--* points are separated by at least smplpmin. To allow the checking of the received samples they are generated from a 14 bits counter CNT that starts at 0
--* and wraps back to 0 around 2^14-1. The samples are always {4*CNT+1,4*CNT+3} when rxvalid is set and {2*R1,2*R2} when rxvalid is unset, where R1 and R2 are
--* two random 15-bits values. The receiver shall thus sample consecutive odd natural numbers and shall never sample an even sample. If it does or if the
--* sequence of samples is not a series of consecutive odd natural numbers, it may be the sign that things go wrong.
--* dac_emulator emulates a DA converter. It generates a sampling clock txclk and an acknowledge signal txack and samples its input data txdata on rising edges
--* of txclk for which txack is set. txack is generated randomly but in such a way that two consecutive sampling points are separated by at least smplpmin. The
--* sampled data are checked against expected values:
--* - An error is raised if the first sampled data is non 0.
--* - An error is raised if a series of non 0 samples comprises less than 3 values.
--* - In any series of samples of the form ...,0,S1,...,Sn,Sn+1,Sn+2,0,... where n>=1 and S1,...,Sn+2 are non 0, let C=CRC32(S1,...,Sn).
--* An error is raised if Sn+1 != n or Sn+2 != (C == 0 ?= 1 : C). CRC32 is based on the 0x04C11DB7 polynomial and is implemented in global_lib.sim_utils as
