Commit 8bf28b33 authored by Renaud Pacalet's avatar Renaud Pacalet

Init Embb public

parents
#!/usr/bin/env bash
here=$(dirname $(realpath ${BASH_SOURCE[@]}))
source "$here/tools/hwprj/bash_completion.d/hwprj"
embb () { make -f "$here/hwprj/Makefile" "$@"; }
complete -F _hwprj embb
[submodule "tools/mli"]
path = tools/mli
url = https://github.com/pacalet/mli.git
[submodule "tools/hwprj"]
path = tools/hwprj
url = git@gitlab.enst.fr:renaud.pacalet/hwprj.git
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/*
* Copyright (c) Institut Mines-Telecom / Telecom ParisTech
*
* Embb is a Digital Signal Processor (DSP).
*
* If you want to know more about Embb http://embb.telecom-paristech.fr/
* is the right place to look at. Embb is governed by the CeCILL license under
* French law and abiding by the rules of distribution of free software. You can
* use, modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* http://www.cecill.info/.
*
*/
This diff is collapsed.
#
# Embb ( http://embb-paristech.fr/ ) - This file is part of Embb
# Copyright (C) - Telecom ParisTech
# Contacts: contact-embb@telecom-paristech.fr
#
# This file must be used under the terms of the CeCILL.
# This source file is licensed as described in the file COPYING, which
# you should have received as part of this distribution. The terms
# are also available at
# http://www.cecill.info/licences/Licence_CeCILL_V2.1-en.txt
#
name: adaif_hreg
longname: ADAIF_HREG
address: 0x0
bound: 32
align: 32
%wptrt0
width: 32
%%wptrt0
width: 11
longname: Write PoinTeR Tx0
doc: Write pointer of TX0 FIFO
%%__padding__
width: 21
%wptrr0
width: 32
%%wptrr0
width: 11
longname: Write PoinTeR Rx0
doc: Write pointer of RX0 FIFO
%%__padding__
width: 21
%wptrt1
width: 32
%%wptrt1
width: 11
longname: Write PoinTeR Tx1
doc: Write pointer of TX1 FIFO
%%__padding__
width: 21
%wptrr1
width: 32
%%wptrr1
width: 11
longname: Write PoinTeR Rx1
doc: Write pointer of RX1 FIFO
%%__padding__
width: 21
%wptrt2
width: 32
%%wptrt2
width: 11
longname: Write PoinTeR Tx2
doc: Write pointer of TX2 FIFO
%%__padding__
width: 21
%wptrr2
width: 32
%%wptrr2
width: 11
longname: Write PoinTeR Rx2
doc: Write pointer of RX2 FIFO
%%__padding__
width: 21
%wptrt3
width: 32
%%wptrt3
width: 11
longname: Write PoinTeR Tx3
doc: Write pointer of TX3 FIFO
%%__padding__
width: 21
%wptrr3
width: 32
%%wptrr3
width: 11
longname: Write PoinTeR Rx3
doc: Write pointer of RX3 FIFO
%%__padding__
width: 21
%cntt0
width: 32
%%cntt0
width: 32
longname: CouNTer Tx0
doc: Free running counter of TX0 interface
%cntr0
width: 32
%%cntr0
width: 32
longname: CouNTer Rx0
doc: Free running counter of RX0 interface
%cntt1
width: 32
%%cntt1
width: 32
longname: CouNTer Tx1
doc: Free running counter of TX1 interface
%cntr1
width: 32
%%cntr1
width: 32
longname: CouNTer Rx1
doc: Free running counter of RX1 interface
%cntt2
width: 32
%%cntt2
width: 32
longname: CouNTer Tx2
doc: Free running counter of TX2 interface
%cntr2
width: 32
%%cntr2
width: 32
longname: CouNTer Rx2
doc: Free running counter of RX2 interface
%cntt3
width: 32
%%cntt3
width: 32
longname: CouNTer Tx3
doc: Free running counter of TX3 interface
%cntr3
width: 32
%%cntr3
width: 32
longname: CouNTer Rx3
doc: Free running counter of RX3 interface
%lvlt0
width: 32
%%lvlt0
width: 12
longname: LeVeL Tx0
doc: Filling level of TX0 FIFO
%%__padding__
width: 4
%%uirqt0
width: 1
longname: Underflow Interrupt ReQuest Tx0
doc: Interrupt flag signalling underflow of TX0 FIFO
%%oirqt0
width: 1
longname: Overflow Interrupt ReQuest Tx0
doc: Interrupt flag signalling overflow of TX0 FIFO
%%mirqt0
width: 1
longname: Mid Interrupt ReQuest Tx0
doc: Interrupt flag signalling that TX0 FIFO went half-empty
%%heft0
width: 1
longname: Half Empty/Full Tx0
doc: Status flag indicating that TX0 FIFO is half-empty or less
%%et0
width: 1
longname: Empty Tx0
doc: Status flag indicating that TX0 FIFO is empty
%%ft0
width: 1
longname: Full Tx0
doc: Status flag indicating that TX0 FIFO is full
%%__padding__
width: 10
%lvlr0
width: 32
%%lvlr0
width: 12
longname: LeVeL Tx0
doc: Filling level of TX0 FIFO
%%__padding__
width: 4
%%uirqr0
width: 1
longname: Underflow Interrupt ReQuest Rx0
doc: Interrupt flag signalling underflow of RX0 FIFO
%%oirqr0
width: 1
longname: Overflow Interrupt ReQuest Rx0
doc: Interrupt flag signalling overflow of RX0 FIFO
%%mirqr0
width: 1
longname: Mid Interrupt ReQuest Rx0
doc: Interrupt flag signalling that RX0 FIFO went half-full
%%hefr0
width: 1
longname: Half Empty/Full Rx0
doc: Status flag indicating that RX0 FIFO is half-full or more
%%er0
width: 1
longname: Empty Rx0
doc: Status flag indicating that RX0 FIFO is empty
%%fr0
width: 1
longname: Full Rx0
doc: Status flag indicating that RX0 FIFO is full
%%__padding__
width: 10
%lvlt1
width: 32
%%lvlt1
width: 12
longname: LeVeL Tx1
doc: Filling level of TX1 FIFO
%%__padding__
width: 4
%%uirqt1
width: 1
longname: Underflow Interrupt ReQuest Tx1
doc: Interrupt flag signalling underflow of TX1 FIFO
%%oirqt1
width: 1
longname: Overflow Interrupt ReQuest Tx1
doc: Interrupt flag signalling overflow of TX1 FIFO
%%mirqt1
width: 1
longname: Mid Interrupt ReQuest Tx1
doc: Interrupt flag signalling that TX1 FIFO went half-empty
%%heft1
width: 1
longname: Half Empty/Full Tx1
doc: Status flag indicating that TX1 FIFO is half-empty or less
%%et1
width: 1
longname: Empty Tx1
doc: Status flag indicating that TX1 FIFO is empty
%%ft1
width: 1
longname: Full Tx1
doc: Status flag indicating that TX1 FIFO is full
%%__padding__
width: 10
%lvlr1
width: 32
%%lvlr1
width: 12
longname: LeVeL Tx1
doc: Filling level of TX1 FIFO
%%__padding__
width: 4
%%uirqr1
width: 1
longname: Underflow Interrupt ReQuest Rx1
doc: Interrupt flag signalling underflow of RX1 FIFO
%%oirqr1
width: 1
longname: Overflow Interrupt ReQuest Rx1
doc: Interrupt flag signalling overflow of RX1 FIFO
%%mirqr1
width: 1
longname: Mid Interrupt ReQuest Rx1
doc: Interrupt flag signalling that RX1 FIFO went half-full
%%hefr1
width: 1
longname: Half Empty/Full Rx1
doc: Status flag indicating that RX1 FIFO is half-full or more
%%er1
width: 1
longname: Empty Rx1
doc: Status flag indicating that RX1 FIFO is empty
%%fr1
width: 1
longname: Full Rx1
doc: Status flag indicating that RX1 FIFO is full
%%__padding__
width: 10
%lvlt2
width: 32
%%lvlt2
width: 12
longname: LeVeL Tx2
doc: Filling level of TX2 FIFO
%%__padding__
width: 4
%%uirqt2
width: 1
longname: Underflow Interrupt ReQuest Tx2
doc: Interrupt flag signalling underflow of TX2 FIFO
%%oirqt2
width: 1
longname: Overflow Interrupt ReQuest Tx2
doc: Interrupt flag signalling overflow of TX2 FIFO
%%mirqt2
width: 1
longname: Mid Interrupt ReQuest Tx2
doc: Interrupt flag signalling that TX2 FIFO went half-empty
%%heft2
width: 1
longname: Half Empty/Full Tx2
doc: Status flag indicating that TX2 FIFO is half-empty or less
%%et2
width: 1
longname: Empty Tx2
doc: Status flag indicating that TX2 FIFO is empty
%%ft2
width: 1
longname: Full Tx2
doc: Status flag indicating that TX2 FIFO is full
%%__padding__
width: 10
%lvlr2
width: 32
%%lvlr2
width: 12
longname: LeVeL Tx2
doc: Filling level of TX2 FIFO
%%__padding__
width: 4
%%uirqr2
width: 1
longname: Underflow Interrupt ReQuest Rx2
doc: Interrupt flag signalling underflow of RX2 FIFO
%%oirqr2
width: 1
longname: Overflow Interrupt ReQuest Rx2
doc: Interrupt flag signalling overflow of RX2 FIFO
%%mirqr2
width: 1
longname: Mid Interrupt ReQuest Rx2
doc: Interrupt flag signalling that RX2 FIFO went half-full
%%hefr2
width: 1
longname: Half Empty/Full Rx2
doc: Status flag indicating that RX2 FIFO is half-full or more
%%er2
width: 1
longname: Empty Rx2
doc: Status flag indicating that RX2 FIFO is empty
%%fr2
width: 1
longname: Full Rx2
doc: Status flag indicating that RX2 FIFO is full
%%__padding__
width: 10
%lvlt3
width: 32
%%lvlt3
width: 12
longname: LeVeL Tx3
doc: Filling level of TX3 FIFO
%%__padding__
width: 4
%%uirqt3
width: 1
longname: Underflow Interrupt ReQuest Tx3
doc: Interrupt flag signalling underflow of TX3 FIFO
%%oirqt3
width: 1
longname: Overflow Interrupt ReQuest Tx3
doc: Interrupt flag signalling overflow of TX3 FIFO
%%mirqt3
width: 1
longname: Mid Interrupt ReQuest Tx3
doc: Interrupt flag signalling that TX3 FIFO went half-empty
%%heft3
width: 1
longname: Half Empty/Full Tx3
doc: Status flag indicating that TX3 FIFO is half-empty or less
%%et3
width: 1
longname: Empty Tx3
doc: Status flag indicating that TX3 FIFO is empty
%%ft3
width: 1
longname: Full Tx3
doc: Status flag indicating that TX3 FIFO is full
%%__padding__
width: 10
%lvlr3
width: 32
%%lvlr3
width: 12
longname: LeVeL Tx3
doc: Filling level of TX3 FIFO
%%__padding__
width: 4
%%uirqr3
width: 1
longname: Underflow Interrupt ReQuest Rx3
doc: Interrupt flag signalling underflow of RX3 FIFO
%%oirqr3
width: 1
longname: Overflow Interrupt ReQuest Rx3
doc: Interrupt flag signalling overflow of RX3 FIFO
%%mirqr3
width: 1
longname: Mid Interrupt ReQuest Rx3
doc: Interrupt flag signalling that RX3 FIFO went half-full
%%hefr3
width: 1
longname: Half Empty/Full Rx3
doc: Status flag indicating that RX3 FIFO is half-full or more
%%er3
width: 1
longname: Empty Rx3
doc: Status flag indicating that RX3 FIFO is empty
%%fr3
width: 1
longname: Full Rx3
doc: Status flag indicating that RX3 FIFO is full
%%__padding__
width: 10
#
# Embb ( http://embb-paristech.fr/ ) - This file is part of Embb
# Copyright (C) - Telecom ParisTech
# Contacts: contact-embb@telecom-paristech.fr
#
# This file must be used under the terms of the CeCILL.
# This source file is licensed as described in the file COPYING, which
# you should have received as part of this distribution. The terms
# are also available at
# http://www.cecill.info/licences/Licence_CeCILL_V2.1-en.txt
#
name: adaif
longname: ADAIF
address: 0x000fff00
bound: 64
align: 64
%cfg
width: 64
%%tdd
width: 4
longname: TDD/FDD mode
default: 0
doc: TDD/FDD mode tx/rx for all 4 channels
%%__padding__
width: 12
%%st
width: 16
default: 0
longname: Channel state
doc: State for all 8 channels, 2 bits per channel.
0: off
1: on
2: idle
3: invalid
%ld0
width: 64
%%ldt0
width: 32
default: 0
longname: reLoaD value Tx0
doc: The reaload value of the free running counter of TX0.
%%ldr0
width: 32
default: 0
longname: reLoaD value Rx0
doc: The reaload value of the free running counter of RX0.
%ld1
width: 64
%%ldt1
width: 32
default: 0
longname: reLoaD value Tx1
doc: The reaload value of the free running counter of TX1.
%%ldr1
width: 32
default: 0
longname: reLoaD value Rx1
doc: The reaload value of the free running counter of RX1.
%ld2
width: 64
%%ldt2
width: 32
default: 0
longname: reLoaD value Tx2
doc: The reaload value of the free running counter of TX2.
%%ldr2
width: 32
default: 0
longname: reLoaD value Rx2
doc: The reaload value of the free running counter of RX2.
%ld3
width: 64
%%ldt3
width: 32
default: 0
longname: reLoaD value Tx3
doc: The reaload value of the free running counter of TX3.
%%ldr3
width: 32
default: 0
longname: reLoaD value Rx3
doc: The reaload value of the free running counter of RX3.