/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: HSI 2014.4
 * Today is: Fri Aug 14 10:48:25 2015
*/


/ {
	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		ip_0: axi_bridge_wrapper@40000000 {
			compatible = "xlnx,axi-bridge-wrapper-1.0";
			reg = <0x40000000 0x1000 0x80000000 0x20000000>;
		};
	};
};
