/*
 * SecBus - This file is part of SecBus
 * Copyright (C) 2012 - Telecom ParisTech
 * 
 * This file must be used under the terms of the CeCILL.
 * This source file is licensed as described in the file COPYING, which
 * you should have received as part of this distribution.  The terms
 * are also available at    
 * http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
 *
 */

#ifndef CRYPTO_MODULE_H
#define CRYPTO_MODULE_H

#include <systemc>

#include "secbus_lib.h"
#include "types.h"
#include "my_interfaces.h"

SC_MODULE(CryptoEngine_conf)
{
protected:
  SC_HAS_PROCESS(CryptoEngine_conf);

public:
  sc_in<bool> p_clk;
  sc_in<bool> p_resetn;

  DATA_REGISTER_READ_IN   *r_register;
  DATA_REGISTER_WRITE_OUT *w_register;

  CRYPTO_CMD_IN		p_crypto;

  CryptoEngine_conf(sc_module_name name, size_t nreg);
  ~CryptoEngine_conf();

private:
  enum c_fsm_state_e
  {
    C_IDLE,
    C_STAGE_0,
    C_WAIT_FOR_DATA,
    C_CIPHER_DATA,
    C_DECIPHER_DATA
  };

  void transition();
  void genMoore();

  sc_signal<int> c_fsm_s;

  sc_signal<uint32_t> iv_s[IV_SIZE_IN_WORDS];
  sc_signal<addr_t>   address_s;
  sc_signal<uint32_t> count_s;
  sc_signal<size_t>   src_s;
  sc_signal<size_t>   dest_s;
  sc_signal<size_t>   size_s;

  sc_signal<bool> ack_s;
  sc_signal<bool> val_s;
  sc_signal<bool> write_reg_s;

  sc_signal<size_t>   idx_s;
  uint32_t ci[SIZE_64_IN_WORDS];
  uint32_t key[DES_KEY_SIZE_IN_WORDS];

  size_t m_nreg;
};

SC_MODULE(CryptoEngine_int)
{
protected:
  SC_HAS_PROCESS(CryptoEngine_int);

public:
  sc_in<bool> p_clk;
  sc_in<bool> p_resetn;

  DATA_IN<12> direct_data;
  DATA_OUT<2> out_mac;

  CRYPTO_CMD_IN		p_crypto;

  CryptoEngine_int(sc_module_name name);
  ~CryptoEngine_int();

private:
  enum i_fsm_state_e
  {
    I_IDLE,
    I_STAGE_0,
    I_WAIT_FOR_DATA,
    I_CIPHER_DATA,
  };

  void transition();
  void genMoore();

  sc_signal<int> i_fsm_s;

  sc_signal<uint32_t> iv_s[IV_SIZE_IN_WORDS];
  sc_signal<uint32_t> wr_data_s[LAST_HS_SIZE_IN_WORDS];
  sc_signal<addr_t>   address_s;
  sc_signal<uint32_t> count_s;
  sc_signal<size_t>   src_s;
  sc_signal<size_t>   dest_s;
  sc_signal<size_t>   size_s;
  sc_signal<bool>     direct_data_s;
  sc_signal<bool>     no_init_s;

  sc_signal<bool> ack_s;
  sc_signal<bool> val_s;
  sc_signal<bool> write_reg_s;

  sc_signal<size_t>   idx_s;
  uint32_t ci[SIZE_64_IN_WORDS];
  uint32_t key[DES_KEY_SIZE_IN_WORDS];

  size_t m_nreg;
};

#endif
