/***************************************
* Auto generated by BFGen, do not edit *
***************************************/

/*
   bfgen -o cdefs -I ../../bitfields/hsm.bitfield -O hsm_reg.h
*/

#ifndef _HSM_BFGEN_DEFS_
#define _HSM_BFGEN_DEFS_

#define HSM_CFG_ADDR                                 0x00000000
/** Aligned multiple of 16MB. 8 MSBs only. Must be set prior use of external
   memory. @multiple */
  #define HSM_CFG_MBBA(v)                          ((v) << 0)
  #define HSM_CFG_MBBA_SET(x, v)                   do { (x) = (((x) & ~0xff) | ((v) << 0)); } while(0)
  #define HSM_CFG_MBBA_GET(x)                      (((x) >> 0) & 0xff)
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_EN(v)                            ((HSM_CFG_EN_##v) << 8)
  #define HSM_CFG_EN_SET(x, v)                     do { (x) = (((x) & ~0x100) | ((HSM_CFG_EN_##v) << 8)); } while(0)
  #define HSM_CFG_EN_GET(x)                        (((x) >> 8) & 0x1)
/** Disables HSM */
    #define HSM_CFG_EN_DISABLE                       0x00000000
/** Enables HSM */
    #define HSM_CFG_EN_ENABLE                        0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_IE(v)                            ((HSM_CFG_IE_##v) << 9)
  #define HSM_CFG_IE_SET(x, v)                     do { (x) = (((x) & ~0x200) | ((HSM_CFG_IE_##v) << 9)); } while(0)
  #define HSM_CFG_IE_GET(x)                        (((x) >> 9) & 0x1)
/** Disables interrupt */
    #define HSM_CFG_IE_DISABLE                       0x00000000
/** Enables interrupt */
    #define HSM_CFG_IE_ENABLE                        0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_PCE(v)                           ((HSM_CFG_PCE_##v) << 10)
  #define HSM_CFG_PCE_SET(x, v)                    do { (x) = (((x) & ~0x400) | ((HSM_CFG_PCE_##v) << 10)); } while(0)
  #define HSM_CFG_PCE_GET(x)                       (((x) >> 10) & 0x1)
/** Disables cache */
    #define HSM_CFG_PCE_DISABLE                      0x00000000
/** Enables cache */
    #define HSM_CFG_PCE_ENABLE                       0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_SPCE(v)                          ((HSM_CFG_SPCE_##v) << 11)
  #define HSM_CFG_SPCE_SET(x, v)                   do { (x) = (((x) & ~0x800) | ((HSM_CFG_SPCE_##v) << 11)); } while(0)
  #define HSM_CFG_SPCE_GET(x)                      (((x) >> 11) & 0x1)
/** Disables cache */
    #define HSM_CFG_SPCE_DISABLE                     0x00000000
/** Enables cache */
    #define HSM_CFG_SPCE_ENABLE                      0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_MSCE(v)                          ((HSM_CFG_MSCE_##v) << 12)
  #define HSM_CFG_MSCE_SET(x, v)                   do { (x) = (((x) & ~0x1000) | ((HSM_CFG_MSCE_##v) << 12)); } while(0)
  #define HSM_CFG_MSCE_GET(x)                      (((x) >> 12) & 0x1)
/** Disables cache */
    #define HSM_CFG_MSCE_DISABLE                     0x00000000
/** Enables cache */
    #define HSM_CFG_MSCE_ENABLE                      0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_MTCE(v)                          ((HSM_CFG_MTCE_##v) << 13)
  #define HSM_CFG_MTCE_SET(x, v)                   do { (x) = (((x) & ~0x2000) | ((HSM_CFG_MTCE_##v) << 13)); } while(0)
  #define HSM_CFG_MTCE_GET(x)                      (((x) >> 13) & 0x1)
/** Disables cache */
    #define HSM_CFG_MTCE_DISABLE                     0x00000000
/** Enables cache */
    #define HSM_CFG_MTCE_ENABLE                      0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_IVE(v)                           ((HSM_CFG_IVE_##v) << 14)
  #define HSM_CFG_IVE_SET(x, v)                    do { (x) = (((x) & ~0x4000) | ((HSM_CFG_IVE_##v) << 14)); } while(0)
  #define HSM_CFG_IVE_GET(x)                       (((x) >> 14) & 0x1)
/** Disables IV */
    #define HSM_CFG_IVE_DISABLE                      0x00000000
/** Enables IV */
    #define HSM_CFG_IVE_ENABLE                       0x00000001
/** 0=disable, 1=enable. @multiple */
  #define HSM_CFG_IVCE(v)                          ((HSM_CFG_IVCE_##v) << 15)
  #define HSM_CFG_IVCE_SET(x, v)                   do { (x) = (((x) & ~0x8000) | ((HSM_CFG_IVCE_##v) << 15)); } while(0)
  #define HSM_CFG_IVCE_GET(x)                      (((x) >> 15) & 0x1)
/** Disables cache */
    #define HSM_CFG_IVCE_DISABLE                     0x00000000
/** Enables cache */
    #define HSM_CFG_IVCE_ENABLE                      0x00000001
/** Size of protected memory area: 1=64MB, 2=256MB, 3=1GB, 4=4GB. @multiple */
  #define HSM_CFG_PSIZ(v)                          ((v) << 21)
  #define HSM_CFG_PSIZ_SET(x, v)                   do { (x) = (((x) & ~0xe00000) | ((v) << 21)); } while(0)
  #define HSM_CFG_PSIZ_GET(x)                      (((x) >> 21) & 0x7)
/** Start address of protected memory. Aligned multiple of 16MB. 8 MSBs only.
   @multiple */
  #define HSM_CFG_PADD(v)                          ((v) << 24)
  #define HSM_CFG_PADD_SET(x, v)                   do { (x) = (((x) & ~0xff000000) | ((v) << 24)); } while(0)
  #define HSM_CFG_PADD_GET(x)                      (((x) >> 24) & 0xff)

#define HSM_STATUS_ADDR                              0x00000004
/** 0=idle, 1=busy. @multiple */
  #define HSM_STATUS_BUSY(v)                       ((HSM_STATUS_BUSY_##v) << 0)
  #define HSM_STATUS_BUSY_SET(x, v)                do { (x) = (((x) & ~0x1) | ((HSM_STATUS_BUSY_##v) << 0)); } while(0)
  #define HSM_STATUS_BUSY_GET(x)                   (((x) >> 0) & 0x1)
/** HSM is idle */
    #define HSM_STATUS_BUSY_IDLE                     0x00000000
/** HSM is busy */
    #define HSM_STATUS_BUSY_BUSY                     0x00000001
/** If not 0 on HSM interrupt, indicates the type of error: 0=none, 1=PSPE
   invalid, 2=SP invalid, 3=integrity violation (MAC sets), 4=integrity violation
   (MAC trees). @multiple */
  #define HSM_STATUS_ERRT(v)                       ((HSM_STATUS_ERRT_##v) << 1)
  #define HSM_STATUS_ERRT_SET(x, v)                do { (x) = (((x) & ~0xe) | ((HSM_STATUS_ERRT_##v) << 1)); } while(0)
  #define HSM_STATUS_ERRT_GET(x)                   (((x) >> 1) & 0x7)
/** Not an error */
    #define HSM_STATUS_ERRT_E_NONE                   0x00000000
/** Invalid PSPE */
    #define HSM_STATUS_ERRT_E_PSPE                   0x00000001
/** Invalid SP */
    #define HSM_STATUS_ERRT_E_SP                     0x00000002
/** MAC set integrity violation */
    #define HSM_STATUS_ERRT_E_MAC                    0x00000003
/** MAC tree integrity violation */
    #define HSM_STATUS_ERRT_E_HT                     0x00000004
/** Type of access that caused error: 0=read, 1=write. @multiple */
  #define HSM_STATUS_ERRC(v)                       ((HSM_STATUS_ERRC_##v) << 4)
  #define HSM_STATUS_ERRC_SET(x, v)                do { (x) = (((x) & ~0x10) | ((HSM_STATUS_ERRC_##v) << 4)); } while(0)
  #define HSM_STATUS_ERRC_GET(x)                   (((x) >> 4) & 0x1)
/** Error on read access */
    #define HSM_STATUS_ERRC_LOAD                     0x00000000
/** Error on write access */
    #define HSM_STATUS_ERRC_STORE                    0x00000001
/** Address of group which access caused an error (27 MSBs). @multiple */
  #define HSM_STATUS_ERRA(v)                       ((v) << 5)
  #define HSM_STATUS_ERRA_SET(x, v)                do { (x) = (((x) & ~0xffffffe0) | ((v) << 5)); } while(0)
  #define HSM_STATUS_ERRA_GET(x)                   (((x) >> 5) & 0x7ffffff)

/** Integrity key of Master MAC Tree and MAC trees of RW pages. @multiple */
#define HSM_MIK_ADDR                                 0x00000008
/** 32 LSBs of MIK.K. @multiple */
  #define HSM_MIK_IKEY0(v)                         ((v) << 0)
  #define HSM_MIK_IKEY0_SET(x, v)                  do { (x) = (((x) & ~0xffffffffULL) | ((v) << 0)); } while(0)
  #define HSM_MIK_IKEY0_GET(x)                     (((x) >> 0) & 0xffffffffULL)
/** 24 MSBs of MIK.K (most significant byte ignored). @multiple */
  #define HSM_MIK_IKEY1(v)                         ((v) << 32)
  #define HSM_MIK_IKEY1_SET(x, v)                  do { (x) = (((x) & ~0xffffff00000000ULL) | ((v) << 32)); } while(0)
  #define HSM_MIK_IKEY1_GET(x)                     (((x) >> 32) & 0xffffffULL)
/** 32 LSBs of MIK.K1. @multiple */
  #define HSM_MIK_IKEY2(v)                         ((v) << 64)
  #define HSM_MIK_IKEY2_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 64)); } while(0)
  #define HSM_MIK_IKEY2_GET(x)                     (((x) >> 64) & 0xffffffffULL)
/** 32 MSBs of MIK.K1. @multiple */
  #define HSM_MIK_IKEY3(v)                         ((v) << 96)
  #define HSM_MIK_IKEY3_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 96)); } while(0)
  #define HSM_MIK_IKEY3_GET(x)                     (((x) >> 96) & 0xffffffffULL)
/** 32 LSBs of MIK.K2. @multiple */
  #define HSM_MIK_IKEY4(v)                         ((v) << 128)
  #define HSM_MIK_IKEY4_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 128)); } while(0)
  #define HSM_MIK_IKEY4_GET(x)                     (((x) >> 128) & 0xffffffffULL)
/** 32 MSBs of MIK.K2. @multiple */
  #define HSM_MIK_IKEY5(v)                         ((v) << 160)
  #define HSM_MIK_IKEY5_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 160)); } while(0)
  #define HSM_MIK_IKEY5_GET(x)                     (((x) >> 160) & 0xffffffffULL)

/** Enciphering/deciphering key of SP entries in MB. @multiple */
#define HSM_MCK_ADDR                                 0x00000028
/** 32 LSBs of MCK.K. @multiple */
  #define HSM_MCK_CKEY0(v)                         ((v) << 0)
  #define HSM_MCK_CKEY0_SET(x, v)                  do { (x) = (((x) & ~0xffffffffULL) | ((v) << 0)); } while(0)
  #define HSM_MCK_CKEY0_GET(x)                     (((x) >> 0) & 0xffffffffULL)
/** 24 MSBs of MCK.K (most significant byte ignored). @multiple */
  #define HSM_MCK_CKEY1(v)                         ((v) << 32)
  #define HSM_MCK_CKEY1_SET(x, v)                  do { (x) = (((x) & ~0xffffff00000000ULL) | ((v) << 32)); } while(0)
  #define HSM_MCK_CKEY1_GET(x)                     (((x) >> 32) & 0xffffffULL)
/** 32 LSBs of MCK.K1. @multiple */
  #define HSM_MCK_CKEY2(v)                         ((v) << 64)
  #define HSM_MCK_CKEY2_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 64)); } while(0)
  #define HSM_MCK_CKEY2_GET(x)                     (((x) >> 64) & 0xffffffffULL)
/** 32 MSBs of MCK.K1. @multiple */
  #define HSM_MCK_CKEY3(v)                         ((v) << 96)
  #define HSM_MCK_CKEY3_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 96)); } while(0)
  #define HSM_MCK_CKEY3_GET(x)                     (((x) >> 96) & 0xffffffffULL)
/** 32 LSBs of MCK.K2. @multiple */
  #define HSM_MCK_CKEY4(v)                         ((v) << 128)
  #define HSM_MCK_CKEY4_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 128)); } while(0)
  #define HSM_MCK_CKEY4_GET(x)                     (((x) >> 128) & 0xffffffffULL)
/** 32 MSBs of MCK.K2. @multiple */
  #define HSM_MCK_CKEY5(v)                         ((v) << 160)
  #define HSM_MCK_CKEY5_SET(x, v)                  do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 160)); } while(0)
  #define HSM_MCK_CKEY5_GET(x)                     (((x) >> 160) & 0xffffffffULL)

#define HSM_RMMT_ADDR                                0x00000048
  #define HSM_RMMT_RMMT0(v)                        ((v) << 0)
  #define HSM_RMMT_RMMT0_SET(x, v)                 do { (x) = (((x) & ~0xffffffffULL) | ((v) << 0)); } while(0)
  #define HSM_RMMT_RMMT0_GET(x)                    (((x) >> 0) & 0xffffffffULL)
  #define HSM_RMMT_RMMT1(v)                        ((v) << 32)
  #define HSM_RMMT_RMMT1_SET(x, v)                 do { (x) = (((x) & ~0xffffffff00000000ULL) | ((v) << 32)); } while(0)
  #define HSM_RMMT_RMMT1_GET(x)                    (((x) >> 32) & 0xffffffffULL)

/** Group's or block's byte address for atomic group read-write operations.
   Aligned on group's or block's boundary: LSBs are ignored. Block atomic access
   if address falls in PSPEs, else group atomic access. @multiple */
#define HSM_AGRWADD_ADDR                             0x00000050
/** Group's or block's byte address for atomic group read-write operations.
   Aligned on group's or block's boundary: LSBs are ignored. Block atomic access
   if address falls in PSPEs, else group atomic access. @multiple */
  #define HSM_AGRWADD_AGRWA(v)                     ((v) << 0)
  #define HSM_AGRWADD_AGRWA_SET(x, v)              do { (x) = (((x) & ~0xffffffff) | ((v) << 0)); } while(0)
  #define HSM_AGRWADD_AGRWA_GET(x)                 (((x) >> 0) & 0xffffffff)

/** Read data or data to write for atomic group or block read-write operations.
   Block position depends on block's alignment in group. @multiple */
#define HSM_AGRWDATA_ADDR                            0x00000054
/** Read data or data to write (lowest address in memory). @multiple */
  #define HSM_AGRWDATA_DATA0(v)                    ((v) << 0)
  #define HSM_AGRWDATA_DATA0_SET(x, v)             do { (x) = (((x) & ~0xffffffffULL) | ((v) << 0)); } while(0)
  #define HSM_AGRWDATA_DATA0_GET(x)                (((x) >> 0) & 0xffffffffULL)
/** Read data or data to write. @multiple */
  #define HSM_AGRWDATA_DATA1(v)                    ((v) << 32)
  #define HSM_AGRWDATA_DATA1_SET(x, v)             do { (x) = (((x) & ~0xffffffff00000000ULL) | ((v) << 32)); } while(0)
  #define HSM_AGRWDATA_DATA1_GET(x)                (((x) >> 32) & 0xffffffffULL)
/** Read data or data to write. @multiple */
  #define HSM_AGRWDATA_DATA2(v)                    ((v) << 64)
  #define HSM_AGRWDATA_DATA2_SET(x, v)             do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 64)); } while(0)
  #define HSM_AGRWDATA_DATA2_GET(x)                (((x) >> 64) & 0xffffffffULL)
/** Read data or data to write. @multiple */
  #define HSM_AGRWDATA_DATA3(v)                    ((v) << 96)
  #define HSM_AGRWDATA_DATA3_SET(x, v)             do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 96)); } while(0)
  #define HSM_AGRWDATA_DATA3_GET(x)                (((x) >> 96) & 0xffffffffULL)
/** Read data or data to write. @multiple */
  #define HSM_AGRWDATA_DATA4(v)                    ((v) << 128)
  #define HSM_AGRWDATA_DATA4_SET(x, v)             do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 128)); } while(0)
  #define HSM_AGRWDATA_DATA4_GET(x)                (((x) >> 128) & 0xffffffffULL)
/** Read data or data to write. @multiple */
  #define HSM_AGRWDATA_DATA5(v)                    ((v) << 160)
  #define HSM_AGRWDATA_DATA5_SET(x, v)             do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 160)); } while(0)
  #define HSM_AGRWDATA_DATA5_GET(x)                (((x) >> 160) & 0xffffffffULL)
/** Read data or data to write. @multiple */
  #define HSM_AGRWDATA_DATA6(v)                    ((v) << 192)
  #define HSM_AGRWDATA_DATA6_SET(x, v)             do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 192)); } while(0)
  #define HSM_AGRWDATA_DATA6_GET(x)                (((x) >> 192) & 0xffffffffULL)
/** Read data or data to write (highest address in memory). @multiple */
  #define HSM_AGRWDATA_DATA7(v)                    ((v) << 224)
  #define HSM_AGRWDATA_DATA7_SET(x, v)             do { (x) = (((x) & ~0xffffffffffffffffULL) | ((v) << 224)); } while(0)
  #define HSM_AGRWDATA_DATA7_GET(x)                (((x) >> 224) & 0xffffffffULL)

#define HSM_AGRWCMD_ADDR                             0x00000074
/** 0: none, 1: read, 2: write, 3: init, 4: continue. HSM applies SP defined for
   target group or block. @multiple */
  #define HSM_AGRWCMD_CMD(v)                       ((HSM_AGRWCMD_CMD_##v) << 0)
  #define HSM_AGRWCMD_CMD_SET(x, v)                do { (x) = (((x) & ~0x7) | ((HSM_AGRWCMD_CMD_##v) << 0)); } while(0)
  #define HSM_AGRWCMD_CMD_GET(x)                   (((x) >> 0) & 0x7)
/** No command */
    #define HSM_AGRWCMD_CMD_NONE                     0x00000000
/** Atomic group read operation at AGRWADD.AGRWA */
    #define HSM_AGRWCMD_CMD_READ                     0x00000001
/** Atomic group write operation at AGRWADD.AGRWA */
    #define HSM_AGRWCMD_CMD_WRITE                    0x00000002
/** First initialization for an empty integrity page (address page at AGRWADD.AGRWA) */
    #define HSM_AGRWCMD_CMD_INIT                     0x00000003
/** Initialization of a non-empty integrity page */
    #define HSM_AGRWCMD_CMD_CONTINUE                 0x00000004

#endif

