/*
 * SecBus - This file is part of SecBus
 * Copyright (C) 2012 - Telecom ParisTech
 * 
 * This file must be used under the terms of the CeCILL.
 * This source file is licensed as described in the file COPYING, which
 * you should have received as part of this distribution.  The terms
 * are also available at    
 * http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
 *
 */

#ifndef _VCI_INPUT_CTRL_H
#define _VCI_INPUT_CTRL_H

#include <systemc>
#include "vci_target.h"

#include "my_interfaces.h"

template<typename vci_param>
SC_MODULE(VciInputCtrl)
{
protected:
  SC_HAS_PROCESS(VciInputCtrl);

public:
  sc_in<bool> p_clk;
  sc_in<bool> p_resetn;

  soclib::caba::VciTarget<vci_param> p_vci_initiator;

  MEMORY_CTRL_CMD_OUT     mem_rq;
  SECURITY_CTX_CMD_OUT    ctx_cmd;
  CTX_REGISTER_READ_IN    ctx_register;
  INTEGRITY_CTRL_CMD_OUT  mt_cmd;
  INTEGRITY_CTRL_ACK_IN   mt_ack;
  INTEGRITY_CTRL_ACK_IN   ms_ack; // Michele: Missing in DS?

  SECURITY_RQ_OUT         sc_cmd; // Michele: Missing in DS?


  DATA_REGISTER_READ_IN   r_register_0;
  DATA_REGISTER_WRITE_OUT w_register_0;

  DATA_REGISTER_READ_IN   r_register_3;
  DATA_REGISTER_WRITE_OUT w_register_3;

  IO_BLOCK_IN<8>          io_handler;
  DATA_OUT<8>             io_handler_write; // Michele: Enable never used? io_handler_write missing in DS?
  sc_out<bool>            io_ack;

  IRQ_OUT                 irq;
  sc_out<bool>            busy;

  sc_in<bool>             sc_busy;

  sc_in<uint32_t>         p_mb_address;
  sc_in<uint32_t>         p_size;
  sc_in<uint32_t>         p_b_address;

  VciInputCtrl(sc_module_name);

private:
  void transition();
  void genMoore();

  enum fsm
  {
    FSM_IDLE,
    FSM_UPDATE_CTX,
    FSM_WUPDATE_CTX,
    FSM_IRQ, // 3
    FSM_WIRQ,
    FSM_IO_READ,
    FSM_WIO_READ,
    FSM_IO_WRITE, // 7
    FSM_WIO_WRITE,
    FSM_READ_CTX,
    FSM_WAIT_CTX,
    FSM_FLUSH_REGISTER_0, // 11
    FSM_READ_IO,
    FSM_START_INIT,
    FSM_WAIT_INIT,
    FSM_START_CONTINUE, // 15
    FSM_CMD_READ,
    FSM_CMD_WRITE,
    FSM_CMD_START_WRITE,
    FSM_WREAD,
    FSM_WWRITE, // 20
    FSM_RREAD,
    FSM_RWRITE
  };

  sc_signal<int>     fsm_state_s;
  sc_signal<addr_t>       start_address_s;
  sc_signal<addr_t>       address_s;
  sc_signal<unsigned int> plen_s;
  sc_signal<unsigned int> be_s;
  sc_signal<unsigned int> srcid_s;
  sc_signal<unsigned int> trdid_s;
  sc_signal<unsigned int> pktid_s;
  sc_signal<unsigned int> cells_count_s;
  sc_signal<bool>         eop_s;
  sc_signal<unsigned int> data_s;
  sc_signal<bool>         pending_packet_s;

  sc_signal<bool>         ready_to_read_s;
  sc_signal<unsigned int> count_s;
  sc_signal<bool>         io_mb_s;
  sc_signal<bool>         is_io_s;
  sc_signal<int> cmd_s;
  sc_signal<bool>         cmdack_s;

  sc_signal<unsigned int> idx_s;

  bool   flush;
  size_t m_cycle;
};

#endif
