/* -*- c++ -*-
 *
 * SOCLIB_LGPL_HEADER_BEGIN
 *
 * This file is part of SoCLib, GNU LGPLv2.1.
 *
 * SoCLib is free software; you can redistribute it and/or modify it
 * under the terms of the GNU Lesser General Public License as published
 * by the Free Software Foundation; version 2.1 of the License.
 *
 * SoCLib is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with SoCLib; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * SOCLIB_LGPL_HEADER_END
 *
 * Sebastien Cerdan <sebcerdan@gmail.com>, 2014
 *
 */
#ifndef SOCLIB_VCI_SPI_FTDI_H
#define SOCLIB_VCI_SPI_FTDI_H

#include <stdint.h>
#include <systemc>
#include <deque>

#include "vci_target_fsm.h"
#include "caba_base_module.h"
#include "mapping_table.h"
#include "spi.h"
#include "ftdi.h"

struct ftdi_context;

namespace soclib {
namespace caba {

using namespace sc_core;

#define SOCLIB_SPI_FTDI_SCLK  0
#define SOCLIB_SPI_FTDI_MOSI  1
#define SOCLIB_SPI_FTDI_MISO  2
#define SOCLIB_SPI_FTDI_GPIO  3  /* 3 to 7 */

#define SOCLIB_SPI_FTDI_GPIO_MASK 0xf8
#define SOCLIB_SPI_FTDI_SPI_MASK 0x07

/*

   0  1  2  3  4  5  6  7
   .  .  .  .  .  .  .  .
   |  |  |  |-->     <--| 
   |  |  |  |           |
   |  |  |  |           \----- GPOUT
   |  |  |  \----------------- GPIN
   |  |  \-------------------- MISO
   |  \----------------------- MOSI
   \-------------------------- SCLK

*/

template<typename vci_param>
class VciSpiFtdi
	: public caba::BaseModule
{
private:
    soclib::caba::VciTargetFsm<vci_param, true> m_vci_target_fsm;

    bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);
    bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);
    void transition();
    void genMoore();

    uint8_t _last_out;
    uint8_t _last_in;
    uint32_t _ctrl;
    uint32_t _cstgl;
    uint32_t _irqpend;
    uint32_t _irqmsk;
    uint32_t _gpirqpend;
    uint32_t _gpirqm;
    uint32_t _gpirqmode;
    uint32_t _gpirqpol;
    uint32_t _poll_cycles;
    uint32_t _poll_top;

    sc_signal<uint32_t> s_tlen;
    sc_signal<uint32_t> s_status;
    sc_signal<uint32_t> s_gpin;
    sc_signal<uint32_t> s_gpout;

    /* RX and TX buffer */
    GenericFifo<uint32_t> * _rxb; 
    GenericFifo<uint32_t> * _txb; 

    size_t _ngpout;
    size_t _ngpin;
    size_t _fsize;
    size_t _wsize;
    size_t _ftdi_tx_size;
    uint32_t _ftdi_rx_cycles;
    uint32_t _ftdi_wait;
    std::deque<size_t> _ftdi_tx;

    uint32_t format_data(uint32_t);
    void ftdi_read(struct ftdi_context *ftdi, uint8_t *data, size_t l);

    struct ftdi_context *_ctx;

protected:
    SC_HAS_PROCESS(VciSpiFtdi);

public:
    sc_in<bool> p_clk;
    sc_in<bool> p_resetn;
    sc_out<bool> p_irq;
    soclib::caba::VciTarget<vci_param> p_vci_target;

    /* Set number of cycles between general purpose inputs polling.
       Inputs will also be read when SPI words are read back. */
    void set_poll_period(unsigned int period)
    {
        _poll_top = period;
    }

    /* Set number of simulation cycles to wait between ftdi_write_data
       and ftdi_read_data. */
    void set_ftdi_latency(unsigned int period)
    {
        _ftdi_wait = period;
    }

    VciSpiFtdi(
      sc_module_name name,
      size_t fsize,
      size_t ngpin,
      size_t ngpout,
      const soclib::common::MappingTable &mt,
      const soclib::common::IntTab &tgtid,
      uint16_t usb_vid = 0x0403, uint16_t usb_pid = 0x6001);

    ~VciSpiFtdi();
};

}}

#endif /* SOCLIB_VCI_SPI_H */

